251A137-512 - BAE Systems, Inc.

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Part Number - See Tabulation

REVISIONS

ECO EOA20156 G Refer to Document Change History herein 01-19-04 K. Mason

R E L or E C O R E V D E S C R I P T I O N D A T E A P P R O V E D

OTES:

1. This is a TOP LEVEL DRAWING (TLD).

BAE SYSTEMS - Manassas, VA reference only.

3. All sheets are the same revision status.

F O R M N O W 2 6 M A N 9 4 - 0 0 1 - 0 NONE

A 1 R U 4 4 251A137 G

D R A W I N G N O .C A G E C O D E

S H E E TW TS C A L E

S I Z E R E V

NONE

T I T L E

MCM,CMOS,2.5V/3.3V,SRAM,512Kx40, STACKED, OPT

P R E P A R A T I O N D A T E

P. NIX

D E S I G N C H E C K D A T E

. D

YLE

D R A W I N G C H E C K D A T E

P. NIX

R A D I A T I O N C H E C K D A T E

R. BR

T E C H N O L O G Y C H E C K D A T E

KEN

O T H E R A P P R O V A L D A T E

REMB

OWS

(

)

O T H E R A P P R O V A L D A T E

. KRA

(

RNIN

)

C O N T R A C T N O.

9300 Wellington Road

Manas sa s, VA 20110

N/A

O T H E R A P P R O V A L D A T E

(

MIL

REEN

)

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Table of Contents

Document Change History.................................................................................................................................4

1 SCOPE....................................................................................................................................................5

1.1 SCOPE ..................................................................................................................................................6

1.2 BAE SYSTEMS PART NUMBER AND IDENTIFICATION ............................................................................. 6

1.3 ABSOLUTE MAXIMUM RATINGS ...............................................................................................................8

1.4 RECOMMENDED OPERATING CONDITIONS............................................................................................... 9

1.5 POWER SEQUENCING............................................................................................................................. 9

2 Applicable Documents ..........................................................................................................................10

2.1 GOVERNMENT SPECIFICATION S AN D STANDARDS..................................................................................10

2.2 BAE SYSTEMS DOCUMENTATION ......................................................................................................10

2.3 OTHER DOCUMENTS ............................................................................................................................10

2.4 ORDER OF PRECEDENCE...................................................................................................................... 10

3 Requirements........................................................................................................................................ 11

3.1 ITEM REQUIREMENTS...........................................................................................................................11

3.2 DESIGN, CONSTRUCTION, AND PHYSICAL DIMENSIONS..........................................................................11

3.3 ELECTRICAL PERFORMANCE CHARACTERISTI CS AND POSTIRRADIATION PARAMETER LIMITS ...................14

3.4 ELECTRICAL TEST REQUIREMENTS .......................................................................................................16

3.5 MARKING.............................................................................................................................................26

4 Qual it y Assurance Pro visi ons ...............................................................................................................27

4.1 SAMPLING AND INSPECTION..................................................................................................................27

4.2 SCREENING .........................................................................................................................................27

4.3 TECHNOLOGY CONFORMANCE INSPECTION (TCI) FOR DEVICE CLASSES H (T) AND K (T+)..................... 29

4.4 QUALITY CONFORMANCE INSPECTION (QCI).........................................................................................29

4.5 BURN-IN CIRCUIT.................................................................................................................................32

5 Packaging/Shipping...............................................................................................................................34

5.1 PACKAGING/SHIPPING REQUIREMENTS .................................................................................................34

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Figures

FIGURE 1. CASE OUTLINE: 84-LEAD FP PACKAGE – TOP, SIDE AND BOTTOM VIEWS (DRAWING NO. -

249A428-1) ...............................................................................................................................................12

FIGURE 2. CASE OUTLINE: 84-LEAD FP PACKAGE CROSS SECTION ....................................................................13

FIGURE 3. SINGLE CHIP FUNCTIONAL BLOCK DIAGRAM....................................................................................... 15

FIGURE 4. TYPICAL STANDBY CUR R ENT VS. TEMPERATURE FOR PASS 2 ............................................................. 18

FIGURE 5. OUTPUT LOAD CIRCUIT ..................................................................................................................... 22

FIGURE 6. READ CYCLE TIMING DIAGRAM .......................................................................................................... 23

FIGURE 7. WRITE CYCLE TIMING DIAGRAM.........................................................................................................24

FIGURE 8. PART MARK (TOP LID).......................................................................................................................26

FIGURE 9. BURN-IN CIRCUIT DIAGRAM F O R EA CH SRAM DIE...............................................................................33

Tables

TABLE 1. TABULATION .........................................................................................................................................6

TABLE 2. ABSOLUTE MAXIMUM RATINGS ..............................................................................................................8

TABLE 3. RECOMMENDED OPERATING CONDITIONS..............................................................................................9

TABLE 4. TRUTH TABLE .....................................................................................................................................14

TABLE 5. CHANGE IN RISING OUT PUT PERFORMANCE VS. ADDITIONAL OUTPUT LOADING.....................................17

TABLE 6. CHANGE IN FALLING OUTPUT PERFORMANCE VS. ADDITIONAL OUTPUT LOADING...................................17

TABLE IA. ELECTRICAL PERFORMANCE CHARACTERISTICS..................................................................................19

TABLE IB. RADIATION REQUIREMENTS (TEST D A TA TBD) ....................................................................................25

TABLE 7. SCREENING FLOWS.............................................................................................................................28

TABLE 8. QUALIFICATION TESTING REQUIREMENTS.............................................................................................30

TABLE IIA. ELECTRICAL TEST REQUIREMENTS....................................................................................................31

TABLE 9. TERMINAL CONNECTIONS FOR 512K X 40 MCM IN 84-FP....................................................................35

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Document Change Histor y

Date R

vECO Description of Changes Originator

02/2002 +N/A Advanced preliminary draft copy (unreleased). P. Nixon,

S. Doyle

05/2002 +N/A Advanced preliminary draft copy; multiple updates (unreleased). P. Nixon,

S. Doyle

10/23/02 −

−−

−EOA11044 • Delete all sections except 1.1 and 1.2 including Table 1.

• Release Table 1 list of part numbers for Production Control ordering purposes. All technical requirements will

be relea sed as Revi sion A or lat er.

This ECO releases -513, -522, -523, -527, -533 parts t o Rev −.

P. Nixon

11/18/02 AEOA11596 • Add -53x dash level to Table 1 and Table IA to cover Pass 1 design.

• Correct the part number for LICA capacitor in table in section 1.2.1.

• In Table 2, added max burn-in temp and corrected max solder temp to 180C.

• Correct VDD power supply range from 2.25-2.75V to 2.3-2.7V per IBM 6SF design rules maximum use

condition in Table 3, Table IA and throughout document.

• Add individual chip identification to Figure 2 (U1-U5).

• Add new section 3.4.4 Pass 1 Design Application Notes and renumbered subsequent section.

• In Table IA, change VIL from 0.800V to 0.750V due to Pass 1 process splits.

• Add ESD triangles to part mark section 3.5.

• Update flows in Table 7 to rem ove rework and to strea mline test requirements. Add Y2 direction to Mechanical

Shock test condition.

• Update burn-in section 4.5 and Figure 7.

• Updated Figure 1 cross sectional view.

This ECO releases on ly the -533 part to Rev A.

P. Nixon

02/10/03 BEOA12897  Update drawing for Pass 2 design and delete Pass 1 references.

 Delete -53x dash parts from Table 1 and Table IA.

 Correct capacitor part number and add note 1 to Manufacturing Tree table in section 1.2.1.

 Correct maximum values for VDD and VDD2 to 3.80V and 5.70V respectively in Table 2.

Update theta-jc and note 6 based on ANSYS model data.

 Correct minimum values VDD and VDD2 in Table 3 and i n Table IA.

 Clarify that Op erating Temperature is based on TJ in Tables 2, 3, and IA.

 Clarify Power Sequencing in section 1.5 that either power supply may be brought up or down in the

middle sequence.

 Update Tables 5 and 6 and section 3.4.3 with Pass 2 values for ch ange in performance based on

 Delete section 3.4. 4 and replace with new section an d with Figure 4 to show change in standby

current over temperature.

 Update Table IA for IDD1, IDR, VIL, Cin, Cout. Updated values for Read performance for tSLQX,

tGLQX, tAXQX, tSHQZ, tGHQZ. Add new Read performance parameter tLVQV. Update Write

performance for tWLWH, tWHDX, tAVWL, tWHAX, tWHQX, tWLQZ. Delete notes 8-11.

 Add section 4.3.1 and Table 8

 Add burn-in requirement for Prototype (-xx2) parts to Table 7. Add note 2 and 3 to Table 7 to

define accelerated bu rn-in conditions. Change pre-burnin to optional test. Change sequence to

move bur n-in prior to lid seal to after li d seal for manufactur ing ease.

This ECO releases only -523 part to Rev B.

P. Nixon,

S. Doyle

02/13/03 C EOA13146  Update Table 1 and Table IA to specify performance parameters, x1x becomes 14ns part (from

TBD) and x2x becomes 17ns part (from 20ns).

 Update Table 3 and Table IA to change max temp to 110C from 125C.

 Update Table 2, Table 3 and notes in Table 7 to clarify temperature references to case or junction.

 Table IA clarify note 1 and add note 8.

Table IA remove note 4 and renumber notes 4 through 7.

Table IA change tDVWH from 8 ns to 6 ns.

Table IA reformat equation at end of notes section.

 Update section 3.4.4 and Figu re 4 with preliminary Iddq vs Temperature data for Pass 2.

 Add section 4.2.2 to describe accelerated burn-in condition used in Table 7.

This ECO releases -512, -517, -519, -529 and updates, -513, -522, -523, -527 parts all to Rev C.

P. Nixon,

S. Doyle

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Date R

vECO Description of Changes Originator

04/08/03 D EOA14096  Add new dash levels –592, -593 to Table 1.

 Correct typo for capacitor part number and description in section 1.2.1.

 Table 2 update Power dissipation calculation and note 3. Table 2 update theta-jc calculation and

note 6. Table 2 update lead solder temperature to 265C.

 Add notes 1 and 2 to section 1.5 Power Sequencing.

 Delete cross-section at top of Figure 2. This was a duplication of the cross-section in Figure 1.

 Add reference to Table 4 note 1 clarifying that the definitions of “Low” and “High” are shown in

Table 3.

 Add clarification to section 3.4.4 that t ypical Iddq measuremen t s are pre-irradiati on.

 Table IA updates for –x9x devices including Vil and note 8/. Delete room temp spec for Idd2 and

Idd3.

 Correct TID maximum from 100Krad to 200Krad in Table IB and Table 1. Update Table IB for RS

to 1E+11, SEU to 1E-09, note 3 modeling information, note 4 LET to 80, and note 6 to technology

capability – all match customer requirements.

 Update part mark diagram in section 3.5; correct line 6 sequence to line 2 (also, correct note 1/ in

Table 1). Add Figure caption for part mark diagram and renumber subsequent figures.

 Add column to help clarify burn-in conditions table in section 4.2.2.

 Correct typo for burn-in time tolerance in Table 7 note 2 and voltage tolerances in section 4.5.1.

This ECO updates -512, -513, -517, -519, -522, -523, -527 –529 and releases –592, -593 parts all to Rev

P. Nixon

05/22/03 EEOA14969  Moved ‘Prototype’ and ‘Engineering’ part mark labels from line 5 to 4 in Table 1.

 Corrected Input and Output Voltage reference to Vd d2 and clarified note 3/ in Table 2.

 Updated note 2/ in section 1.5 to match wording in other R25 electrical spec documents.

 Replaced case ou tline drawing in Figure 1 with updated drawing, including top, side an d bottom

views. Dimensions are in mm. Moved cross-section view to top of Figure 2; added Note 3.

 Moved Tab le 4 before Figure 3 to save layout space.

 Corrected Voh at Ioh=-200u A to reference Vdd2 (vs Vdd) in Table IA.

 Corrected Vdd=2.70V and Vdd2=3.60V for RTD test conditions in Table IB.

 Updated Part Mark drawing in Figure 8 (added leads to top and bottom of drawing, moved serial

number to lid, removed Kovar Ring marking, updated No tes to clarify). Added line 5 customer

specific part number for NGST deliveries.

 Added “Wafer Fabrication” row to Table 7 Screening Flows. Corrected note for pre-burnin option.

 In Tables 7 and 8, changed Mechanical Shock from Cond B (1500g) to Co nd C (3000g) to satisfy

customer requ est. Also, correct t hat Mechanical Shock is done in 6-axes instead of two.

 Corrected and updated pin assignments in Table 9 for pins # 55,58,61,62,64,65,68,71.

This ECO upda tes -512, -513, -517, -519, -522, -523, -527 –529, –592, and -593 parts all to Rev E.

P. Nixon

09/30/03 FEOA17810  Delete dash levels –592, -593 from Table 1 and Table IA.

 Updated Table 4 to set LS=LD to Don’t Care for Chip Selected Standby mode.

 Update Figure 4 typical Iddq vs Te mperature chart with P ass 2.1 data.

 Update Table IA spec values for IDD1, IDD1S, IDD2, IDD3, IDR, tGLQV, tSHQZ, tGHQZ,

tAVWH, tSLWH, tWLWH. Added tLVQX, tLXQZ and tLVWH parameters and specs.

 Updated Figure 6 Read Cycle and Figure 7 Write Cycle t o include LD/LS signals.

 Added accelerated life test time into table in section 4.2.2.

 Rearrange assembly steps to match manufacturing production flow in Table 7.

This ECO updates -512, -513, -517, -519, -522, - 523, -527 and –529 par ts.

P. Nixon

01/19/04 GEOA20156  Clarified in Table 1 t hat –xx2, -xx7 and –xx9 are all processed with accelerat ed burn-in condi tions

 Update table in section 1.2.1 to add new part number for Class S capacitors.

 Update Table 1 and Table IA for –51x devices from 14ns to 15ns (update parameters tAVAV,

tAVQV, tSLQV, tAVAV, tAVWH, tSLWH, tLVWH, tWLWH).

 Delete static burn-in from section 4.5.

This ECO updates -512 , -513, -5 17, -519, -522, -523, -527 and –529 pa rts all to Rev G.

P. Nixon

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1 SCOPE

1.1 Scope

This T op Leve l Dr a wing ( T LD) des cr ibes an d spec if ies th e r e quirem ents for a 0.25µm Leff, monolithic silicon,

memory device with commercial space capability. The memory device configuration is a 512Kx40 SRAM

(five stacked 4M SRAM die) in a single, double-sided ceramic substrate.

1.2 BAE SYSTEMS Part Number and Identification

The following “tabulation” table defines exceptions to the listed sections of this document. Exceptions

include: BAE SYSTEMS qualification levels, case outline specifications, radiation test requirements,

electrical test requirements, part marking requirements, screening requirements, and technology

conformance inspection provisions.

Table 1. Tabulation

Section Name Rev Device

Type Qualification

Level per

internal spec

MAN-STC-Q002

Radiation Test

Requirements Test

Requirements

(Access Time)

Part Marking

Requirements

Screening

Requirements

per internal spec

MAN-STC-Q002

Technology

Conformance

Inspection per

internal spec

MAN-STC-Q002

Section

Number 4.0 3.3 3.4.3 3.5 4.2 4.3

Part

Number

251A137-512 G512 Prototype Limits not

guaranteed 15 ns 251A137-512

Prototype

(USA) datecd

”Prototype” f l ow

with accelerated

burn-in condit i ons

Not required

251A137-513 G513 Engineering Limits not

guaranteed 15 ns 251A137-513

Engineering

(USA) datecd

”Engineering” fl ow Not required

251A137-517 G517 Pre-qualified ≥ 200Krad 15 ns 251A137-517

Pre-qualified

(USA) datecd

Commercial

Space "T+"

("modified K-

screen") flow

with accelerated

burn-in condit i ons

As required

251A137-519 G519 Pre-qualified ≥ 200Krad 15 ns 251A137-519

Pre-qualified

(USA) datecd

Commercial

Space "T"

("modified H-

screen ") flow

with accelerated

burn-in condit i ons

As required

251A137-522 G522 Prototype Limits not

guaranteed 17 ns 251A137-522

Prototype

(USA) datecd

”Prototype” f l ow

with accelerated

burn-in condit i ons

Not required

251A137-523 G523 Engineering Limits not

guaranteed 17 ns 251A137-523

Engineering

(USA) datecd

”Engineering” fl ow Not required

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Section Name Rev Device

Type Qualification

Level per

internal spec

MAN-STC-Q002

Radiation Test

Requirements Test

Requirements

(Access Time)

Part Marking

Requirements

Screening

Requirements

per internal spec

MAN-STC-Q002

Technology

Conformance

Inspection per

internal spec

MAN-STC-Q002

Section

Number 4.0 3.3 3.4.3 3.5 4.2 4.3

Part

Number

251A137-527 G527 Pre-qualified ≥ 200Krad 17 ns 251A137-527

Pre-qualified

(USA) datecd

Commercial

Space "T+"

("modified K-

screen") flow

with accelerated

burn-in condit i ons

As required

251A137-529 G529 Pre-qualified ≥ 200Krad 17 ns 251A137-529

Pre-qualified

(USA) datecd

Commercial

Space "T"

("modified H-

screen ") flow

with accelerated

burn-in condit i ons

As required

Notes:

1/ Part marking requirements are for the 3rd, 4th, 5th and 6th rows as detailed in Section 3.5 herein. "datecd" =

date code. Reference Case Outline shown in Figure 1 on sheet 12 herein.

2/ The test requirements for each device type are delineated in Table IA.

1.2.1 Manufacturing Tree for 251A137

Part Description Part Number Device Type Qty Part Supplier

Module Assembly DWG. No. 249A428-1 All 1 BAE SYSTEMS

512Kx8 SRAM die 250A783 (WB die)

250A783 (C4 die) 1/ All 5 BAE S YST EMS

(commercial

foundry)

8388297-1 [or

LICA3T253M1FC4xA]

(Class R screened)

Only

-xx2,

-xx3

Capacitors (Low Inductance decoupling

Capacitor Arrays), 100nF

8388297-2, -3

(upscr eened parts ) or

8388297-4

(Class S screened)

All

10 AVX Corporation

Notes:

1/ the C4 di e us es th e s ame mask set as the WB (wirebo nd) d ie with the ex ception of the T V mask leve l which

is replaced by the LV reticle for the C4 die.

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1.3 Absolute Maximum Ratings

Table 2. Absolute Maximum Ratings

A pplied Conditions 1/ Minimum Maximum

Storage Temperature Range (Ambient) −65°C +150°C

Operating Temperature Range (TJ) 5/ −55°C +140°C

Positiv e Sup ply Voltage (VDD)−0.5V +3.80V

Positive I/O Supply Voltage (VDD2)−0.5V +5.70V

Input Voltage 2/ −0.5V VDD2 + 0.5V

Output Voltage 2/ −0.5V VDD2 + 0.5V

Power Dissipation 3/ 2.4W

Module Thermal Resistance, junction-to-case (θjc) 6/ 7.8°C/W

Lead Temperature (Soldering 5 sec) +265°C

Electrostatic Discharge Sensitivity 4/ Class 2 (TBD)

Notes:

1/ Stresses at or beyond the absolute maximum ratings may cause permanent damage to the device.

Extended operation at the maximum or minimum levels may degrade performance and affect reliability.

All voltages are referenced to the module ground leads.

2/ Maximum applied voltage shall not exceed 3.80V for VDD or 5.70V for VDD2.

3/ Not tested. This value is based on a steady-state wave form analysis at worst case conditions for an

active chip current spike approximately 1.5ns wide that goes to no current approximately 2.3ns into the

cycle (at 2.70V) and an I/O current spike approximately 3.0ns wide that goes to no current approximately

7.0ns into the cycle (at 3.60V). This analysis assumes a 14ns access and 20ns standby cycle. The

steady state power for these conditions is calculated to be 2.4W for the entire module.

4/ Class as defined in MIL-STD-883, Method 3015.

5/ Operation outside the recommended operating conditions specified in Table 3 may cause degradation in

the electrical parameters as defined herein.

6/ Thermal resistance is based on all five die dissipating a total of 2.4W per module. The worst case

steady-state temperature rise from the bottom of the case to the junction of the topmost die is 18.566°C.

A maximum transient delta temperature can be added to the maximum steady state temperature rise to

establish a true maximum junction temperature rise at the sub-block level. The transient analysis of a

sub-block shows the delta case to junction temperature to be 0.225°C. Therefore, the maximum case to

junction temperature rise for 2.4W dissipated by the entire module will be 18.791°C.

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1.4 Recommended Operating Conditions

Table 3. Recommended Operating Conditions

Symbol Parameters 1/ Minimum Nominal Maximum Units

VDD Suppl y Voltag e +2.30 +2.50 +2.70 Volt

VDD2 I/O Supply Voltage +3.00 +3.30 +3.60 Volt

GND Sup ply Voltage Reference 0.00 0.00 Volt

Tcase Case Temperature −55 +25 +110 Celsius

VIL Input Logic “Low” 0.00 +0.80 Volt

VIH Input Logic “High” +2.00 VDD2 Volt

Note:

1/ All voltages referenced to GND.

1.5 Power Sequencing

The substrate of this module is connected directly to Ground. Power shall be applied to the device only in

the following sequences to prevent damage due to excessive currents.

Power-up sequence: GND, VDD and/ or VDD2, Inputs

Power-down sequence: Inputs, VDD2 and/or VDD, GND

NOTES:

1) Delay between power up or down for VDD and VDD2 can be between –10ms to +50ms.

2) The loss of the 2.5V power supply (3.3V power supply active) coupled with an external event (e.g. SEU

hit on a critical I/O circuit) may result in a shorting condition. This combined event can not exist for more

than 5 minutes (cumulative time) without reliability impact. A safety margin is included in this analysis,

contact BAE SYSTEMS if this limit has been exceeded. If there is no external event, the loss of the 2.5V

power supply alone will not result in a n y reliab ility impac t.

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2 Applicable Documents

2.1 Government Specifications and Standards

Unless otherwise specified, the following specifications and standards form a part of this drawing to the

extent specified herein.

Specifications, Military

DOD-HDBK-263 - “Electrostatic Discharge Control Handbook For Protection of Electrical and

Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated

Explosive Devices)”

MIL-PRF-38534 - “Hybrid Microcircuits, General Specification For”

MIL-PRF-38535 - “Integrated Circuits (Microcircuits), Manufacturing General Specification For”

Standards , Mi lit ar y

DOD-STD-1686 - “Electrostatic Discharge Control Program for Protection of Electrical and

Electronic Parts, Assemblies, and Equipment (Excluding Electrically Initiated

Explosive Devices)”

MIL-STD-883 - “Test Methods and Procedures for Microelectronics”

MIL-STD-1835 - “Electronic Component Case Outlines”

2.2 BAE SYSTEMS Documentation

MAN-STC-Q001 - “Quality Management (QM) Program”

MAN-STC-Q002 - “Quality and Qualification Requirements for Microcircuits”

2.3 Other Documents

ASTM standard F1192M-95 - “Measurement of Single Event Phenomena (SEP) Induced by

Heavy Ion Irradiation of Semiconductor Devices (Metric)”

2.4 Order of Precedence

In the event of conflict between the text of this drawing and the references cited herein, the text of this

drawing shall take precedence.

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3 Requirements

3.1 Item Requirements

The individual item requirements for device classes H (T) and K (T+) shall be in accordance with M IL-PRF-

38534, the device manufacturer’s Qualit y M anagement (QM) plan (BAE SYSTE MS specification MAN-ST C-

Q001), BAE SYSTEMS specification MAN-STC-Q002, and as specified herein.

3.2 Design, Construction, and Ph ysical Dimensions

The design, construction, and physical dimensions shall b e as spec ified in MIL-PRF-38535, MIL-STD-1835,

and herein.

3.2.1 Case Outline

The case outline shall be as specified in this section. The case outline for a particular device type shall be as

delineated in Section 1.2 herein.

3.2.1.1 84-LEAD Flat Pack Package: The case outline shall be in accordance with Figure 1 on sheet 12.

3.2.2 Terminal Connections

The terminal connections shall be as specified in Table 9, starting on sheet 35.

3.2.3 Functional Description

A Functional Block Diagram shall be as specified Figure 3 on sheet 15.

3.2.4 Truth Table

The Truth Table shall be as specified in Table 4 on sheet 14.

3.2.5 Materials

All devic es supplied under this specificati on shall be hermetical ly sealed in m etal and/ or ceram ic packages.

Organic or pol ymerized materials may be used inside the microcircuit package provided that the pack age is

capable of meeting the internal water-vapor content requirement of MIL-STD-883, Test Method 1018.

The requir em ents f or the lid, s ubstr ate, an d the de vice le ads are def ined in the m odul e ass em bly dr awi ng as

cited in Section 1.2.1 herein.

3.2.5.1 Lead Base Material The base lead material shall be type A kovar as specified in MIL-PRF-38535

paragraph 3.6.2.5.

3.2.5.2 Lead Finish The lead finish material shall be 100 micro inches of gold plated over 100 to 300

micro inches of nickel.

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Notes:

1. For part mark, reference section 3.5, sheet 26 herein and Table 1, sheet 6 herein.

2. Dimensions are in millimeters, unless otherwise specified.

3. Lead Width: 0.008 ± 0.002 inches.

Lead Height: 0.005 + 0.002 / – 0.001 inches.

Lead Pitch: 0.020 + 0.004 inches.

Figure 1. Case Outline: 84-lead FP Package – Top, Side and Bottom Views (Drawing No. - 249A428-1)

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Notes:

1. -5xx device t ype utilizes 5 die and an interposer per each cavity of the package (5 die total).

2. 2 die use C4 flip chip to attach to the package substrate; 3 die use gold ball bond to attach from

the die to the package substrate.

3. Dimensions are in inches (mm).

Figure 2. Case Outline: 84-lead FP Package Cross Section

Filled Organic

Adhesive 2x

Silicon

Interpose

Bulk Silicon Chip

3X Places

97Pb / 3Sn

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3.3 Electrical Performance Characteristics and Postirradiation Parameter Limits

The electrical performance characteristics specified in Table IA are guaranteed for post-irradiation to those

radiation levels specified in Table IB. Device latchup will not occur for radiation levels specified in Table IB

and operating conditions less than or equal to those specified in Table 3. The applicability of these post-

irradiation guarantees for a particular device type is as specified in section 1.2 herein.

Table 4. Truth Table

Mode Inputs 1/, 2/ Power

LS, LD 3/ S W G I/O

W RIT E LS = LD LOW LOW X DATA- IN ACTI VE

READ LS = LD LOW HIGH LOW DATA-OUT ACTIVE

STANDBY 4/ X HIGH X X HIGH-Z STANDBY

STANDBY LS ≠ LD X X X HIGH-Z STANDBY

Notes:

1/ Logic “Low” and “High” are defined by VIL or VIH in Table 3. VIN for Don’t Care (X) inputs = VIL or VIH.

2/ When G = HIGH, I/O is High-Z.

3/ LS0, LS1 (select) and LD0, LD1 (decode) inputs provide externally programmable bank-select decode

capability.

A match between the LS and LD bits will pass control of the module to chip select; a mismatch between

the LS and LD bits overrides chip select and puts the entire module into standby mode.

4/ To dissipate the minimum amount of standby power when in standby mode: CS > VDD; LD0 and LD1 >

VDD or = GND, LS0 and LS1 > VDD or = GND. All other in put le ve ls m a y float.

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Notes:

1. Address and control signals (including LD/LS pins) are common with all SRAM devices.

2. E is tied to Vdd internal to the package.

Figure 3. Single Chip Functional Block Diagram

Block

Decoder

Sub-Block

Decode

Row Address

Decoder ((256 x 32) x 16 x 4) x 8

Memory Cell Array

8 Bit Word

Input/Output

Column

Address

Decoder

A17-A18

DQ0-DQ7

A13-A16

A0-A7

A8-A12

LS0

LD0

LS1

LD1

XNOR

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3.4 Electrical Test Requirements

3.4.1 Manufacturing Electrical Tests

The manufacturing electrical test requirements shall consist of functional test patterns as defined below. All

tests shall be performed across the temperature and supply voltage range as specified in 1.4 herein. Any

single functional fail shall be cause for device rejection.

The dynamic tests specified below assure test coverage for the 512Kx40 SRAM MCM device. T he patterns

are used with device specific address descrambling and various timing conditions to insure sound device

performance. The MARCH pattern, which is 13N, covers defects or faults in the memory. Such faults are

stuck cell, open cell, lack of address decode uniqueness and adjacent cell coupling. The RCGAL pattern,

which is n(3/2), covers additional performance problems that may be missed by the MARCH pattern. With

address desc rambling, th is pattern c overs the po tential per formance pr oblems that the tr aditional N patterns

did when used witho ut address descram bling. The D ADD pat tern, or data e quals addres s patt ern, wri tes a nd

reads sequential bytes of data to and from the memory under test which are equal to the eight least

significant address signals. The purpose is to check for data word uniqueness versus byte address.

MARCH:

a. Write a background of 0’s into all cells.

b. Starting at address 0, read 0, write it to a 1, read it as a 1.

c. Increment address and repeat step b. for entire memory.

d. Starting at maximum address, read 1, write it to a 0, read it as a 0.

e. Decrement address and repeat step d. for entire memory.

RCGAL:

a. Write a background of 0’s into all cells.

b. Write 1 into address Test Bit (Test Bit starts at cell zero and is incremented through the entire memory).

c. Alternately read Test Bit and each cell on the row of the Test Bit.

d. Alternately read Test Bit and each cell on the column of the Test Bit.

e. Write Test Bit back to 0, then increment the test bit.

f. Repeat Step b - e until Test Bit has been at every cell in memory.

DADD:

a. Starting at address 0, write 0 into RAM.

b. Increment address and data word.

c. Writ e RAM.

d. Repeat steps b and c until address and data equal 255 (base 10).

e. Increment address, reset data word to 0, write RAM.

f. Increment address and data word.

g. Write RAM.

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h. Repeat steps f and g until entire RAM is written.

i. Reset address back to 0.

j. Sequentially read entire RAM and check for correct data.

3.4.2 Switching Tests

Switching tests shall be as specified in Table IA.

3.4.3 Performance vs. Output Load

The following tables show the change in MCM performance based on change in output loading above and

beyond the output load as shown in Figure 5.

Table 5. Change in Rising Output Performance vs . Additional Output Loading

Condition

Tcase VDD VDD2 +50pF +100pF +200pF +300pF

+125°C2.25V 2.97V 1.841ns 3.666ns 7.319ns 10.725ns

+100°C2.25V 2.97V 1.823ns 3.637ns 7.237ns 10.703ns

+25°C2.50V 3.30V 1.516ns 3.026ns 6.053ns 9.040ns

−30°C2.75V 3.63V 1.234ns 2.468ns 4.927ns 7.383ns

−55°C2.75V 3.63V 1.132ns 2.260ns 4.520ns 6.735ns

Table 6. Change in Falling Output Performance vs. Additional Output Loading

Condition

Tcase VDD VDD2 +50pF +100pF +200pF +300pF

+125°C2.25V 2.97V 1.820ns 3.613ns 7.216ns 10.604ns

+100°C2.25V 2.97V 1.709ns 3.385ns 6.743ns 10.003ns

+25°C2.50V 3.30V 1.330ns 2.636ns 5.249ns 7.820ns

−30°C2.75V 3.63V 1.093ns 2.170ns 4.332ns 6.470ns

−55°C2.75V 3.63V 0.997ns 1.981ns 3.963ns 6.002ns

These performance values are based on an initial module loading of 30pf, which includes the module device

self capacitance. These tables are provided for user reference and the values are not tested.

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3.4.4 Standby Current vs. Temperature

The following figure shows the change in MCM standby current over temperature. This figure is based on

the typical measurements (pre-irradiation) for eight devices from the Pass 2.1 design and therefore is only for

reference.

Figure 4. Typical Standby Current vs. Temperature for Pass 2.1

3.4.5 Test Requirements

The electrical test requirements shall be as specif ied in Table IIA on sheet 31. The e lectrica l tests for each

subgroup are defined in Table IA.

512Kx40 SRAM Pass 2.1

Iddq vs Temperature

1.4 2.7 5.4 10.8

21.6

43.8

82.2

120.2

100

120

140

20C

25C

30C

35C

40C

45C

50C

55C

60C

65C

70C

75C

80C

85C

90C

95C

100C

105C

110C

115C

120C

125C

Temperature (degrees C)

Iddq (mA)

2.30V/3.00V 2.50V/3.30V 2.70V/3.60V

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Table IA. Electrical Performance Characteristics

LimitsTest Symbol Test Conditions 1/

−

−−

−55C < Tcase < +110C

2.30V < VDD < 2.70V

3.00V < VDD2 < 3.60V

unless otherwise specified

Group A

Sub-

groups

Device

Type 2/

Min. Max

Units

IDD1 F = 25MHz

/S = VIL = GND, E = VIH = VDD

No output load,

Random Pattern

1, 2, 3 All 850 mASupply Current

(Cycli ng Se lec ted)

IDD1S F = 25MHz

/S = VIL = GND, E = VIH = VDD

No output load,

Sequential Pattern

1, 2, 3 All 650 mA

Supply Current

(Cycling

De-Selected)

IDD2 F = 25MHz

/S = VIH = VDD, E = VIL = GND 1, 2, 3 All 100 mA

Supply Current

(Standby) IDD3 F = 0 MHz

/S = VIH = VDD, E = VIL = GND 1, 2, 3 All 100 mA

Data Retention

Current (Standby) IDR VDD = VDD2 = 1.5V 1, 2, 3 All 75 mA

High Level

Output Volta ge VOH IOH = -4 mA 1, 2, 3 All 2.4 V

High Level

Output Volta ge VOH IOH = -200 µA1, 2, 3 All VDD2 −

0.1V V

Low Level

Output Volta ge VOL IOL = 8 mA 1, 2, 3 All 0.4 V

Low Level

Output Volta ge VOL IOL = 200 µA1, 2, 3 All 0.1 V

Data Retention

Voltage VDR VDD = VDD2 = VDR 1, 2, 3 All 1.5 V

High Level

Input Voltage VIH 1, 2, 3 All 2.0 V

Low Level

Input Voltage VIL 1, 2, 3 All 0.8 V

Input Leakage

except LDx, LSx,

IILK 0V < VIN < 3.6V 1, 2, 3 5xx −25 25 µA

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LimitsTest Symbol Test Conditions 1/

−

−−

−55C < Tcase < +110C

2.30V < VDD < 2.70V

3.00V < VDD2 < 3.60V

unless otherwise specified

Group A

Sub-

groups

Device

Type 2/

Min. Max

Units

Output Leak age IOLK 0V < VOUT < 3.6V 1, 2, 3 5xx −25 25 µA

Cin, except LDx 3/ 4 All 35 pF

Cin for LDx pins 3/ 4 All 40 pF

Cout 3/ 4 All 12 pF

Functional Tests See 3.4.1 herein 7, 8A, 8B All

Read Cycle AC Specifications x1x 15 nsRead Cycle Time tAVAV 9, 10, 11 x2x 17 ns

x1x 15 ns

Address Access

Time tAVQV 9, 10, 11 x2x 17 ns

x1x 16 nsChip Select

Access Time tSLQV 9, 10, 11 x2x 18 ns

x1x 17 nsLS/LD

Access Time tLVQV 9, 10, 11 x2x 19 ns

Output Enabl e

Access Time tGLQV 9, 10, 11 All 6 ns

Chip Select to

Output Acti ve tSLQX 9, 10, 11 All 3 ns

LS/LD to

Output Acti ve tLVQX 9, 10, 11 All 3 ns

Output Enabl e to

Output Acti ve tGLQX 9, 10, 11 All 1 ns

Output Hold after

Address Change tAXQX 9, 10, 11 All 3 ns

Chip Select to

Output Disab le tSHQZ 9, 10, 11 All 5 ns

LS/LD to

Output Disab le tLXQZ 9, 10, 11 All 7 ns

Output Enabl e to

Output Disab le tGHQZ 9, 10, 11 All 5 ns

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LimitsTest Symbol Test Conditions 1/

−

−−

−55C < Tcase < +110C

2.30V < VDD < 2.70V

3.00V < VDD2 < 3.60V

unless otherwise specified

Group A

Sub-

groups

Device

Type 2/

Min. Max

Units

Write Cycle AC Specifications 4/ to 6/ x1x 15 nsWrite Cycle Time tAVAV 9, 10, 11 x2x 17 ns

Address Setup to

End of Wr ite tAVWH 9, 10, 11 All 10 ns

Chip Select to

End of Wr ite tSLWH 9, 10, 11 All 10 ns

LS/LD to

End of Wr ite tLVWH 9, 10, 11 All 11 ns

Write Pulse Width tWLWH 9, 10, 11 All 10 ns

Data Setup to End

of Write tDVWH 9, 10, 11 All 6 ns

Data Hold after

End of Wr ite tWHDX 9, 10, 11 All 2 ns

Address Setup to

Start of W rite tAVWL 9, 10, 11 All 0 ns

Address Hold after

End of Wr ite tWHAX 9, 10, 11 All 1 ns

Output Active after

End of Wr ite tWHQX 9, 10, 11 All 3 ns

Write Enable to

Output Disab le tWLQZ 9, 10, 11 All 6 ns

Write Disable

Pulse Width tWHWL 9, 10, 11 All 5 ns

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LimitsTest Symbol Test Conditions 1/

−

−−

−55C < Tcase < +110C

2.30V < VDD < 2.70V

3.00V < VDD2 < 3.60V

unless otherwise specified

Group A

Sub-

groups

Device

Type 2/

Min. Max

Units

Notes:

1/ Tes t conditio ns ar e def ine d at incepti on of tes t. The device is f irs t s tabi lized at the desired tem per ature in

an unpower ed state to e nsure that the m odule is at the desired T case bef ore param eters are measured.

The case temperature (Tcase) is maintained during testing at the specified temperature by a forced air

test environment.

Test conditions for AC measurements are listed below.

Input Levels: 0V to VDD, VDD2

Input rise and fall time: < 1.0ns/Volt

Input and output timing reference levels (except for tristate parameters): 1.5V

Input and output timing reference levels for tristate parameters: VOL = 1.23V,

VOH = 2.23V.

Output load: See Figure 5 below and section 0 on sheet 17.

Read Cycle timing diagram is shown in Figure 6 on sheet 23.

Write Cycle timing diagram is shown in Figure 7 on sheet 24.

LS and LD: See Table 4 on sheet 14.

2/ The device t ypes are as defined in 1.2 herein. The delineation in this table is by device speed, thus the

x1x and x2x nomenclature. x1x represents a 15 ns device; x2x represents a 17 ns device.

3/ Guaranteed by design and verif ied by period ic charac teri za tio n.

4/ S high and W high must occur while address transitions.

5/ The worst case timing sequence of tWLWH + tWHWL = tAVAV (write cycle time).

6/ G high will prevent the I/O output from becoming active (tWLQZ)..

7/ IDD1 is measured at 25MHz and 110C. User may extrapolate to other frequencies b y removing the fixed

standby current component and rescaling according to the following formula:

active current at frequency (FNEW) = [((IDD1 - IDD3) ÷

÷÷

÷ (F=25MHz)) * FNEW] + IDD3

1.73V

162Ω

ΩΩ

Ω ± 1%

30 pF

± 10%

Figure 5. Output Load Circuit

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Figure 6. Read Cycle Timing Diagram

t AVAV

VALID ADDRESS

ADDRESS

t AVQV

t SLQV

HIGH IMPEDANCE VA L ID DATA

t AXQX

DATA

OUT

t SHQZ

t SLQX

t GLQV

t GHQZ

t GLQX

t LVQV

LS,LD VALID COMPARE

t LXQZ

t LVQX

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Figure 7. Write Cycle Timing Diagram

t AVAV

VA LID ADDR E SS

ADDRESS

t AVWH

t SLWH

t WLWH

t WHWL

t WHQX

HIGH

IMPEDANCE

t WLQZ

t AVWL

HIGH

IMPEDANCE t DVWH t WHDX

HIGH IMPEDANCE VALID DATA HIGH

IMPEDANCE

t WHAX

DATA

OUT

DATA

t LVWH

LS,LD VALID COMPARE

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Table IB. Radiation Requirements

Symbol Characteristics Conditions 1/, 2/ Device Type Min. Max Units

All 2.0E+05 rad(Si)RTD Total Dose 5/ VDD = 2.70V, VDD2 = 3.6 0V

during irradiating, static bias

All 1E+08 rad(Si)/sRPRU Prompt Dose Upset

8/ 20ns-50ns pulse width

Tcase = 25C and 110C,

VDD = 2.30V, VDD2 = 3.0 0V

All 1E+11 rad(Si)/sRS Survivability 7/ 20ns-50ns pulse width

Tcase = 110C,

VDD = 2.70V, VDD2 = 3.6 0V

All 1E-09 upsets/bit-

day

SEU Single Event Upset

3/ -55C <Tcase < 110C,

VDD = 2.30V, VDD2 = 3.0 0V

All Immune

SEL Single Event Induced

Latchup 3/ -55C < Tcase < 110C,

VDD = 2.70V, VDD2 = 3.6 0V

All 1E+13 N/cm2RNF Neutron Fluence 6/ Tcase = 25C, unbiased

during exposure

Note:

1/ Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan.

2/ Device electrical characteristics are guaranteed for post irradiation levels at 25C.

3/ Calculation performed assuming CREME96 GCR Heavy Ion Spectrum with 0.100” of Aluminum shielding

with an absorpt ion depth of 2µm. Testing performed according to ASTM Standard F1192.

4/ Immune for LET < 80 Mev-cm2/mg.

5/ Irradiation performed according to MIL-STD-883, Test Method 1019.5, Condition A. Specification

guaranteed for dose rates between 50 and 300 rad(Si)/s.

6/ Technology Capability. No specific testing is performed on this part type.

7/ Testing performed according to MIL-STD-883, Test Method 1021.2.

8/ Testing performed according to MIL-STD-883, Test Method 1020.1 and 1021.2.

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3.5 Marking

The part shall be marked with the markings shown below and as specified in section 1.2 herein. The

ma rk ing orientation to the c ase outlines s h al l be as s pec if ie d i n th e c as e o utl in e des c rib ed in s ec t ion 3.2 .1 on

sheet 11. Additional markings shall include the ESD symbol as a lead one designator. The ESD

classification level is a specified in section 1.3 herein.

Marking shall be in accordance with MIL-PRF-38535 as implemented according to the approved BAE

SYSTEMS QML Qualit y Management Program . ESD marking shall be in accorda nce with DOD-STD-1686.

Marking permanence verification shall be in accordance with MIL-STD-883, Test Method 2015.

Top Lid Markings **

Pin 84 









Pin 43 

Mark line 1: BAE SYSTEMS

Mark line 2: 1RU44

Mark line 3 *: 251A137-XXX

Mark line 4 *: XXXXXXXXXXXX

Mark line 5 *: XXXXXXXXXXXX ******

Mark line 6 *: QML*** (USA) datecode

***** SSSSS****



Pin 1







Pin 42

Notes:

* For lines 3 through 6, reference ‘Part Marking Requirements’ of Table 1, Section 1.2

herein. Lines 4 and 5 may be blank. Datecode is formatted YYWW.

** Reference Case Outline shown in Figure 1 on sheet 12.

*** ‘QML’ may not be required.

**** Non repeating seria l number. Serial number may also appear on selvage strip.

***** ESD indicators are located near pin 1.

****** Customer specific part number is placed on line 5 for NGST according to the following:

BAE Number => NGST Number on line 5 (Comment)

251A137-512 => 251A137-001EM (for 15nS EM)

251A137-522 => 251A137-101EM (for 17nS EM)

251A137-517 => 251A137-001-PS001 (for 15nS Flight)

251A137-527 => 251A137-101-PS001 (for 17nS Flight)

Figure 8. Part Mark (Top Lid)

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4 Quality Assurance Provisions

All quality assurance provisions shall be as documented in BAE SYSTEMS specification MAN-STC-Q002

and MAN-ST C-Q001. BA E SYSTEMS s pecific ation MAN-STC- Q002 defin es three qua lity levels of devices ,

or ’device clas ses’. They are: B AE S YSTEM S QM L (Clas s H /T and K/T +), Pr otot ype, and Engi neering. T he

qualif ication leve l of each partic ular device t ype manuf actured to this dra wing shall be as specif ied in s ection

1.2 herein.

4.1 Sampling and Inspection

For clas s H (T) and K (T+) par ts, sam pling an d inspectio n procedur es shal l be in acc ordanc e with MIL-PRF-

38534 as implemented by BAE SYSTEMS’ approved Quality Management (QM) plan and as specified in

BAE SYSTEMS specif ic ati on MAN- ST C- Q 002 .

4.2 Screening

For Class H (T) and K (T+) parts, sc reening sha ll be in ac cordanc e with MI L-PRF-385 34 as im plemented by

BAE SYSTEMS’ approved Quality Management (QM) plan and as specified in Table 7. Screening shall be

conducted on all devices prior to qualification and technology conformance inspection. The screening

requirements f or eac h p ar tic ul ar de v ic e type manuf actur ed t o this dra win g s ha ll be as s p ec if ied in s ection 1.2

herein.

4.2.1 Screening Flows are defined in Table 7 on sheet 28.

4.2.2 Accelerated Burn-in Conditions

Equivalent burn-in stress is calculated using foundry reliability acceleration factors. The maximum junction

temperature for burn-in is specified as 140C. The following burn-in conditions are equivalent:

Temp (T

)Vdd (core) Vdd2 (I/O) Time (Flight) Time (Prototype/

Pre burn-in) Time (Life Test)

Standard: 125C 2.70V 3.60V 160 hours 24 hours 1000 hours

Accelerated: 125C 3.00 V 3.75V 19.67 hours 2.95 hours 123 hours

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Table 7. Screening Flows

Assembly and

Screening Flow 883 Test

Method

Commercial Space

"T+" (" modified K-

screen") Flight flow

Commercial Space

"T" ("modified H-

screen") Flight flow

Prototype,

Engineering

flow Comments

BAE SYSTEMS

part number 251A137-xx7 251A137-xx9 251A137-xx2,

251A137-xx3

Wafer Fabrication -- Foundry “B” Foundry “B” Foundry “B” Commercial Foundry procedures

Wafer Lot Acceptance 5007 per MAN-STC-

Q014 per MAN-STC-

Q014 N/A Internal procedures

Chip Inspection 2010 Cond A, per

MAN-STC-A014 Cond A, per

MAN-STC-A014 N/A

Serialization -- 100% 100% 100% Internal procedures

C4 attach/flux clean

the 2 innermost die and

capacitors

-- 100% 100% 100% Internal procedures

Interposer attach,

Die attach 2 top die,

Wire bond (Gold Ball Bond)

-- 100% 100% 100% Internal procedures

Die attach outmost die,

Wire bond (Gold Ball Bond),

C4 Encapsulation/Cure

-- 100% 100% 100% Internal procedures

Wirebond Pull Tests 2011 Setup Samples Setup Samples N/A Destructive test

Die Pull Tests 2027/2031 Setup Samples Setup Samples N/A Destructive test

Dynamic Burn-in 1/ 4/

(Pre-Burnin condition) 1030 3.0 (-0,+1.0)

hours, 125C or

equivalent

3.0 (-0,+1.0)

hours, 125C or

equivalent

N/A Use accelerated voltage conditions

of VDD = 3.00V, VDD2 = 3.75V.

This pre-burnin is optional ONLY if

the accelerated voltage conditions

are used for the 160-hour burn-ins

defined below. 3/

T1A Test 4/ Per TLD 25C

(Optional 3 temp) 25C

(Optional 3 temp) N/A

Pre-Lid Inspection

(Internal Visual) 2010,

2017 Cond A, per

MAN-STC-A013 Cond A, per

MAN-STC-A013 per

MAN-STC-A013

Customer Source

Inspection (CSI) Per SOW *** As Req'd *** *** As Req'd *** N/A

Vacuum Bake,

Lid seal -- 100% 100% 100% Internal procedures.

Fine Leak 1014 100% 100% Optional Cond A;

Rework failing lid if necessary

Temperature Cycle 1010 Cond C,

20 cycles Cond C,

20 cycles N/A Cond C = -65C to +150C

Mechanical Shock 2002 Cond C, 2-axes Cond C, 2-axes N/A Cond C = 3000G

PIND 2020 Cond A, 100% Cond A, 100% N/A

X-ray 2012 100% 100% N/A

T1B Test Pe r TLD 25C 25 C N/A

Dynamic Burn-in 1 1/ 1015 160hrs, 125C or

equivalent 2/ N/A N/A

T1C Test 4/ Per TLD 25C N/A N/A This test is optional. If the two

burn-ins are combined then PDA

applies to the combined burn-in.

Dynamic Burn-in 2 1/ 1015 160hrs, 125C or

equivalent 2/ 160hrs, 125C or

equivalent 2/ 24hrs, 125C or

equivalent 3/

T2 Test (Final Test) Per TLD (3 temp) (3 temp) -xx2 (3 temp)

-xx3 25C

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Assembly and

Screening Flow 883 Test

Method

Commercial Space

"T+" (" modified K-

screen") Flight flow

Commercial Space

"T" ("modified H-

screen") Flight flow

Prototype,

Engineering

flow Comments

BAE SYSTEMS

part number 251A137-xx7 251A137-xx9 251A137-xx2,

251A137-xx3

PDA -- 2%\one device

or pattern failure

option

10%\one device

or pattern failure

option

N/A MAN-STC-Q016 (ref. MIL-PRF-

38534) based on number of die

Partmark per TLD see Section 3.5 see Section 3.5 see Section 3.5

Fine/Gross Leak 1014 100% 100% N/A Cond A, C

Final Inspection 2009 100%, per

MAN-STC-A501 100%, per

MAN-STC-A501

Customer Source

Inspection (CSI) Per SOW *** As Req'd *** *** As Req'd *** N/A

Stock/Ship -- Per Purchase

Order Per Purchase

Order

Note:

1/ Burn-in conditions as defined in Section 4.5 on sheet 32.

2/ Burn-in for 160 hours at VDD= 2.70V, VDD2=3.60V, and TA=125C calculates to an equivalent accelerated stress of 19.67

hours at VDD=3.00V, VDD2=3.75V and TA=125C. For manufacturing, time in burn-in may be performed for 19.7 -0/+2.0 hours

at accelerated conditions. This calculation is based on commercial foundry reliability data with temperature acceleration

constant Ea=0.7eV and voltage acceleration constant Beta=7.0/V. This 160-hour burn-in (or equivalent) is done 2X for the

Commercial Space "T+" modified Class K flow and 1X for the Commercial Space "T" modified Class H flow.

3/ Pre burn-in or Prototype burn-in for 24 hours at VDD= 2.70V, VDD2=3.60V, and TA=125C calculates to an equivalent

accelerated stress of 2.95 hours at VDD=3.00V, VDD2=3.75V and TA=125C. For manufacturing, time in burn-in may be

performed for 3.0 -0/+1.0 hours at accelerated conditions. This calculation is based on commercial foundry reliability data with

temperature acceleration constant Ea=0.7eV and voltage acceleration constant Beta=7.0/V. This 24-hour burn-in is done for

the Prototype flow (-xx2) or for pre burn-in on the Flight flows. No burn-in is performed on Engineering parts (-xx3).

4/ This is an optional step in the flow.

4.3 Technology Conformance Inspection (TCI) for Device Classes H (T) and K (T+)

Inspection for device classes H (T) and K (T+) shall be in accordance with MIL-PRF-38534. Inspections to

be performed shall be those specified in MIL-PRF-38534 as implemented by BAE SYSTEMS’ approved

Qualit y Managem ent (QM) plan. T he TCI requ irements f or each particu lar devic e type manufac tured to this

drawing shall be as specified in section 1.2 herein.

4.3.1 Qualification Testing Requirements are defined in Table 8 on sheet 30.

4.4 Quality Conformance Inspection (QCI)

Quality conformance inspection shall be implemented as specified in BAE SYSTEMS specification MAN-

STC-Q002.

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Table 8. Qualification Testing Requirements

Group Description Test Method Condition Sample Min Part Rqmts Notes

A1-3,7-11 100% Electrical Test per TLD 3 temp 100% Full Screen

B1 Physical Dimensions 883 TM 2016 2 (0) Elect . Rejects MCM

B2 PIND 883 TM 2020 A 15 (0) El ect. Rejects MCM

B3 Resist ance to Solvents 883 TM 2015 A, B and D 3 (0) Elect . Rejects MCM

B4 Internal Visual 883 TM 2014 1 (0) Elect. Rejects MCM

B5c Bond Strength 883 TM 2011 D (wirebond) or F

(flip chip ) 2 (0) Elect. Rejects MCM

B6 Die Shear 883 TM 2019 2 (0) Elect. Rej e cts MCM

B7 Solderability 883 TM 2003 solder temp

+245+/-5C 1 (0) El e ct. Rejects MCM

B8 Seal 15 (0) Elect. Reje cts MCM

-- Fine 883 TM 1014 A

-- Gross 883 TM 1014 C

B9 ESD 883 TM 3015 Group A-1 3 (0) + 2 setups room temp good SCM

C1a External Vis ual 883 TM 2009 5 (0) F ul l Screen MCM

C1b PIND 883 TM 2020 A, 5 passes " Full Screen MCM

C1c Temperature Cycl e 883 TM 1010 C, 100 cycles " Ful l Screen MCM

C1e Constant Acceleration 883 TM 2001 B (10K G), Y1

and Y2 direction " Full Screen MCM

and/or Mechanical Shock 883 TM 2002 C (3000 G), 6

axes " Full Screen MCM

C1f Seal (fi ne and gross) 883 TM 1014 A and C " Full Screen MCM

C1g PIND 883 TM 2020 A, 1 pass " Full Screen MCM

C1i Visual Examination 883 TM 1010/2009 " Full Screen MCM

C1j End Point Electrical per TLD room temp " Full Screen MCM

C2a Steady-state Life Test 883 TM 1005 1000hrs at +125C 77 (1) Full Screen SCM 1/

C2b End Point Electrical per TLD 3 temp Full Screen SCM

C3 Internal water vapor 883 TM 1018 at +100C < 5000ppm 3 (0) from C1

C4a Internal Visual 883 TM 2014 2 (0) from C3

C4b Wirebond strength/Element

shear 883 TM 2011 (wirebond) or

2019 2 (0) from C4a

D1a Thermal Shock 883 TM 1011 C 5 (0) Elect. Rejects MCM 2/

D1b Stabilization Bake 883 TM 1008 +150C, 24 hours 5 (0)

D1c Lead Integrity 883 TM 2004 B2 (l ead fatigue),

15 leads min 1 (0)

D1d Seal 5 (0)

-- Fine 883 TM 1014 A

-- Gross 883 TM 1014 C

D2 Moisture Res istance 883 TM 1004 5 (0)

D3 Salt Atmosphere 883 TM 1009 A 5 (0)

E2 Total Ionizing Dose 883 TM 1019 at 25C 22(0)+1 (Initial

qual); 5(0)+1

(periodic QCI)

Full Screen SCM

E4 Single Event Phenomena ASTM F1192 at 110C 5(0)+1 (Initial

qual) Full Screen SCM

Notes:

1/ Life test may substitute 16 5-high stack MCMs in place of 77 single chip modules. Electrical readouts are tested at 0, 168. 504 and 1000 hours.

2/ Sealed empty MCM packages may be used for Group D. These packages must follow the screening and handling flows for flight hardware but

electrical test is not required.

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Table IIA. Electrical Test Requirements

Test Requirements Subgroups 1/, 5/

(In accordance with MIL-STD-883 and MAN-STC-Q002)

3/ Qualification Level: Commercial Space

modified Class K (T+) Commerc ial Spac e

modified Class H (T) Prototype Engineering

(251A137-xx7) (251A137-xx9) (251A137-xx2) (251A137-xx3)

Interim electrical parameters 1, 7, 9 1, 7, 9

Final electrical parameters 1-3, 7-11 2/ 1-3, 7-11 2/ 1-3, 7-11 1, 7, 9

Group A test requirements 1-3, 7-11 1-3, 7-11

Group C1 end-point electrical

parameters 4/ 1, 7, 9 1, 7, 9

Group C2 end-point electrical

parameters 4/ 1-3, 7-11 1-3, 7-11

Group E end-point electrical

parameters 4/ 1, 7, 9 1, 7, 9

Notes:

1/ Blank spaces indicate tests are not applicable.

2/ PDA applies to subgroups 1 and 7.

3/ Qualification level is defined per section 1.2 herein.

4/ Group A electrical test subgroups applied after applicable Group C, D, and E tests are completed.

5/ Group A electrical test subgroups:

Subgroup Parameters

1 Static tests at +25C

2 Static tests at maximum rated operating temperature

3 Static tests at minimum rated operating temperature

4 Dynamic tests at +25C

5 Dynamic tests at maximum rated operating temperature

6 Dynamic tests at minimum rated operating temperature

7 Functional tests at 25C

8a Functional tests at maximum rated operating temperature

8b Functional tests at minimum rated operating temperature

9 Switching tests at +25C

10 Switching tests at maximum rated operating temperature

11 Switching tests at minimum rated operating temperature

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4.5 Burn-in Circuit

The applicable burn-in stresses are as specified below and are required per BAE SYSTEMS specification

MAN-STC-Q002 and section 1.2 herein.

4.5.1 Stress Methodology

For ”Dynamic” burn-in, all possible addresses are written with alternating High and Low data.

All I/O p ins spec ified in t he dynam ic burn- in pin l ists are driven throug h ind ividual series resistors (1. 6KΩ +/-

10%). Burn-in voltages are defined using the following notation:

Pre-Burnin and Accelerated Voltage Levels:

Vin(0): 0.00 V to +0.40 V VIL= LOW level for all programmed signals

Vin(1) : +3.65 V to +4.00 V VIH = HIGH level for all programmed signals

V1: + 3.00 V (-0%/+0.100V) All VDD pins are tied to this level

V2: + 3.75 V (-0%/+0.100V) All VDD2 pins are tied to this lev el

Vsx: Float or GND All GND pins are tied to this level

Burnin Vo ltage Levels:

Vin(0): 0.00 V to +0.40 V VIL= LOW level for all programmed signals

Vin(1) : +3.50 V to +3.85 V VIH = HIGH level for all programmed signals

V1: + 2.70 V (-0%/+0.100V) All VDD pins are tied to this level

V2: + 3.60 V (-0%/+0.100V) All VDD2 pins are tied to this lev el

Vsx: Float or GND All GND pins are tied to this level

The burn-in circuit diagram is shown in Figure 9 on sheet 33.

4.5.2 Dynamic Burn-in

Pin Listing:

The dynamic burn-in pin listing is shown below. F = square wave, 100 KHz to 1.0 MHz.

Input Signal Input Signal Input Signal Input Signal

A0 F/2 A6 F/128 A12 F/8192 A18 F/524288

A1 F/4 A7 F/256 A13 F/16384 W F/1048576

A2 F/8 A8 F/512 A14 F/32768 DQ0..39 F/2097152

A3 F/16 A9 F/1024 A15 F/65536 S F

A4 F/32 A10 F/2048 A16 F/131072 G VIL

A5 F/64 A11 F/4096 A17 F/262144 LS = LD G ND

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Figure 9. Burn-in Circuit Diagram for each SRAM die

SRAM

LS/LD

A0 R

A18

DQ0

DQ7

V1 C1 = 0.1 µF(±10%)

R = 1.6KΩ ( ±10% )

512Kx8

SRAM

LS/LD

A0 R

A18

DQ8

DQ15

V1 C1 = 0.1 µF(±10%)

R = 1.6KΩ ( ±10 % )

512Kx8

SRAM

LS/LD

A0 R

A18

DQ16

DQ23

V1 C1 = 0.1 µF(±10%)

R = 1.6KΩ ( ±10% )

512Kx8

SRAM

LS/LD

A0 R

A18

DQ24

DQ31

V1 C1 = 0.1 µF(±10%)

R = 1.6KΩ ( ±10 % )

512Kx8

SRAM

LS/LD

A0 R

A18

DQ32

DQ39

V1 C1 = 0.1 µF(±10%)

R = 1.6KΩ ( ±10% )

512Kx8

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5 Packaging/Shipping

5.1 Packaging/Shipping Requirements

All deliverable hardware shall be handled, stored and packaged to properly identify the item, to prevent

handling damage and to protect against electrostatic damage. Proper ESD control procedures shall be

followed.

The requirements for packaging/shipping shall be in accordance with BAE SYSTEMS specification MAN-

STC-Q001.

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Table 9. Terminal Connections for 512K x 40 MCM in 84-FP

Package

Pin Package

Signal Package

Pin Package

Signal

1LS0 84 LS1

2A10 83 A12

3A8 82 A11

4A2 81 A9

5A0 80 A3

6/OE 79 A1

7/WE 78 /CS

8VDD 77 VDD

9GND 76 GND

10 DQ8 (U2) 75 DQ15 (U2)

11 DQ9 (U2) 74 DQ14 (U2)

12 DQ16 (U3) 73 DQ23 (U3)

13 DQ17 (U3) 72 DQ22 (U3)

14 DQ32 (U5) 71 DQ39 (U5)

15 GND 70 GND

16 VDD2 69 VDD2

17 DQ33 (U5) 68 DQ38 (U5)

18 DQ0 (U1) 67 DQ7 (U1)

19 DQ1 (U1) 66 DQ6 (U1)

20 DQ24 (U4) 65 DQ31 (U4)

21 DQ25 (U4) 64 DQ30 (U4)

22 GND 63 GND

23 DQ26 (U4) 62 DQ29 (U4)

24 DQ27 (U4) 61 DQ28 (U4)

25 DQ2 (U1) 60 DQ5 (U1)

26 DQ3 (U1) 59 DQ4 (U1)

27 DQ34 (U5) 58 DQ37 (U5)

28 VDD2 57 VDD2

29 GND 56 GND

30 DQ35 (U5) 55 DQ36 (U5)

31 DQ18 (U3) 54 DQ21 (U3)

32 DQ19 (U3) 53 DQ20 (U3)

33 DQ10 (U2) 52 DQ13 (U2)

34 DQ11 (U2) 51 DQ12 (U2)

35 GND 50 GND

36 VDD 49 VDD

37 A4 48 A5

38 A6 47 A7

39 A18 46 A17

40 A16 45 A15

41 A14 44 A13

42 LD0 43 LD1

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Notes:

/CS = S = Chip Se lect Bar

/WE = W = Write Enable Bar

/OE = G = Output Enable Bar

LD0-LD1 = Decoder Programming

LS0-LS1 = Decoder Selects

A0-A18 = Address Inputs

DQ0-DQ39 = Data Input/Outputs

VDD = 2.5V Core Power

VDD2 = 3.3V I/O Power

GND = Ground

N/C = No Connect

2/ See Table 4 on sheet 14 for the truth table.