ANALOG LC?M0S DEVICES Dual 12-Bit ppP-Compatible DAC AD7549 FEATURES FUNCTIONAL BLOCK DIAGRAM Two Doubled Buffered 12-Bit DACs 4-Quadrant Multiplication Voo Low Gain Error (3LSBs max) DAC Ladder Resistance Matching: 1% Space Saving Skinny DIP and Surface Mount Packages Latch-Up Proof Extended Temperature Range Operation APPLICATIONS Programmable Filters Automatic Test Equipment Microcomputer Based Process Control Audio Systems Programmable Power Supplies Synchro Applications DAC A REGISTER loura Area Vrera v, CONTROL ners LOGIC Pres AGND DAC B REGISTER GENERAL DESCRIPTION The AD7549 is a monolithic dual, 12-bit, current output D/A converter. It is packaged in both 0.3 wide 20-pin DIPs and in 20-terminal surface mount packages. Both DACs provide four quadrant multiplication capabilities with a separate reference input and feedback resistor for each DAC. The monolithic construction ensures excellent thermal tracking and gain error tracking between the two DACs. The DACs in the AD7549 are each loaded in three 4-bit nibbles. The control logic is designed for easy processor interfacing. PRODUCT HIGHLIGHTS 4 DB3-DB0 DGAD Input and DAC register loading is accomplished using address 1. Small package size: the loading structure adopted for the lines AO, Al, A2 and CS, WR lines. A logic high level on the AD7549 enables two 12-Bit DACs to be packaged in either a CLR input clears all registers. Both DACs may be simultaneously small 20-pin 0.3" DIP or in 20-terminal surface mount updated using the UPD input. packages. The AD7549 is manufactured using the Linear Compatible 2. DAC to DAC matching: since both DACs are fabricated on CMOS(LC2MOS) process. It is speed compatible with most the same chip, precise matching and tracking is inherent. microprocessors and accepts TTL, 74HC or 5V CMOS logic This opens up applications which otherwise would not be level inputs. considered, i.e., Programmable Filters, Audio Systems, etc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tal: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS(Voo = + 15V +5%?, Viera = Vecre = 10V; loura = lous = AGND = OV. All specifications Tyg, tO Tia unless otherwise specified.) AD7549 SPECIFICATIONS JA K, Parameter Versions Versions SVersion {| TVersion | Units Test Conditions/Comments ACCURACY Resolution 12 12 12 12 Bits Relative Accuracy 1 +2 +1 +12 LSB max Differential Nonlinearity 1 +1 +1 +1 LSB max All grades guaranteed monotonic over temperature. Full Scale Error +6 +3 +6 +3 LSB max Measured using internal Rpg and includes effects of leakage current and gain TC. Gain Temperature Coefficient; AGain/ATemperature +5 +5 +5 +5 ppm/C max Typical value is lppm/*C Output Leakage Current Toura (Pin 17) +25C 20 20 20 20 nA max DAC A Register loaded with all 0s Trin tO Trax 150 150 250 250 oA max louts (Pin 15) +25C 20 20 20 20 nA max DAC B Register loaded with all 0s Trin t0 Tnox 150 150 250 250 nA max REFERENCE INPUT Input Resistance (Pin 19, Pin 13) 7 7 7 kO min Typical Input Resistance = 11k0. 18 18 18 18 kO max Vrera/VREFB Input Resistance Match +3 +2 +3 +2 % max Typically + 1% DIGITAL INPUTS Vin (Input High Voltage) 2.4 2.4 2.4 2.4 Vmin Vi Unput Low Voltage) 0.8 0.8 0.8 0.8 V max Ty (input Current) +25C +1 1 1 1 pA max Vin = Vpp T nin tO Tmax +10 +10 +10 +10 pA max Cy (Input Capacitance)* 7 7 pF max POWER SUPPLY Ibp 5 5 5 5 mA max AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test. (Yoo = + 15; Vecra = Vers = + 10V, lou = lou = AGND = OV, Output Amplifiers are AD644 except where stated.) Parameter Ta= +25C Ta=Tmin; Tmax } Units Test Conditions/C Output Current Settling Time Ls - [Ss max To 0.01% of full scale range. Ionut load = 1000; Cex = 13pF. DAC output measured from falling edge of WR. Typical value of Settling Time is 0.8ps. Digital-to-Analog Glitch Measured with Verra = Vers = OV. Iouta; lout load = 1000, Cext = L3pF. Impulse 10 - nV-sec typ DAC registers alternately loaded with all 0s and all 1's. AC Feedthrough* Varera to Ilouta 70 65 dB max Vrera: Veen = 20V p-p 10kHz sine wave. Vrers to lous 70 65 dB max DAC registers loaded with all 0s. Power Supply Rejection AGain/AVppy +6.01 +0.02 % per % max AVpn = +5% Output Capacitance Couta 80 80 pF max DAC A, DACB loaded with all 0s. Couts 80 80 pF max Couta 160 160 pF max DAC A, DACB loaded with all 1s. Couts 160 160 pF max Channel-to-Channel Isolation Verera tolouts -62 - dBtyp Vrera = 20V p-p 100kHz sine wave, Var = 0V Vrers to louta ~62 - dB typ Vrern = 20V p-p 100kHz sine wave, Vrrra =0V Digiul Crossalk 10 - nV-sec typ Measured for a Code Transition of all 0s toail 1's Output Noise Voltage Density (10Hz-100kHz) 15 ~ nV/V Hz typ Measured between Rrra and [outa or Reps and Iours Harmonk Distortion -9 - dB typ Vin = 6V rms kHz NOTES Temperature range 2a follows: J, K, Versions: 40C to + 85C A,B, Versions: 40C to + 85C S,T, Versions: 55C to + 125C. 7A Vpp = 5V, the device is fully 3Guarantced by Product Assurance by testing. . . Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND. Specifications subject to change without notice. REV. Aeee eee AD7549 TIMING CHARACTERISTICS isp =+15V, Vasa = Veco = +10; un = lum = ABND = OV, unless otherwise tated Limit at Limit at Limit at Ta=-40C Ta= 55C Parameter Ta=25C to +85C to +125C Units Test Conditions/Comments q 50 80 110 ns min Address Valid to Write Setup Time tz 0 0 0 ns min Address Valid to Write Hold Time ts 180 200 240 ns min Data Setup Time & 0 0 0 ns min Data Hold Time ts 20 20 20 ns min Chip Select or Update to Write Setup Time te 0 0 0 ns min Chip Select or Update to Write Hold Time ty 170 200 250 ns min Write Pulse Width tg 170 200 250 ns min Clear Pulse Width Specifications subject to change without notice. al 3| A0-A2 DATA CLR NOTES 5vV ov 5Vv ov 5V ov 5V en Fs 1. All INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. t,=t;=20ns. 2. TIMING MEASUREMENT REFERENCE LEVEL IS Vet Mu ABSOLUTE MAXIMUM RATINGS* (Ta = +25C unless otherwise noted) Operating Temperature Range 40C to +85C 40C to +85C Commercial (J, K Versions) Industrial (A, B Versions) Vpp (Pin 20)to DGND............-. 0.3V, +17V Vv Vv ins 19,13)toAGND ......... tO ee Fs Von. von Pine 81 > 1o AGND 28y Extended (S, T Versions)... ......- ~55C to +125C Di gital I nput Voltage (Pins Li 0ttttti<Cis=iisS ~ Storage Temperature ..........-.. 65C to + 150C to DGND ~0.3V, Vpp +0.3V Lead Temperature (Soldering, 10secs) ........ + 300C Se ee ee 3V, . Vemis, Vpri7z, to DGND........ 0.3V, Vpp +0.3V *Stresses above those listed under Absolute Maximum Ratings may AGNDtoDGND.......... 0.3V, Vpp +0.3V cause permanent damage to the device. This is a stress rating only and P Dissipati An Packa. > functional operation of the device at these or any other conditions above ower Dissipation (Any Package) those indicated in the operational sections of this specification is not TO +75 2. ee ee es 450mW implied. Exposure to absolute maximum rating conditions for extended Derates above. + 75C 2... 1.2... ee ee ee es 6mW/C periods may affect device reliability. CAUTION WARNING! ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- ed; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. Ser LSD SENSITIVE DEVICE REV.AAD7549 ORDERING GUIDE Temperature Relative Full Scale Package Model! Range Accuracy Error Option? AD7549JN 40C to + 85C +1LSB +6LSB N-20 AD7549KN 40C to + 85C + 1/2LSB +3LSB N-20 AD7549JP 40C to + 85C +1LSB +6LSB P-20A AD7549KP 40C to + 85C + 1/2LSB +3LSB P-20A AD7549AQ 40C to + 85C +1LSB +6LSB Q-20 AD7549BQ 40C to + 85C + 1/2LSB +3LSB Q-20 AD7549SQ 55C to + 125C +1LSB +6LSB Q-20 AD7549TQ 55C to + 125C + 1/2LSB +3LSB Q-20 AD7549SE 55C to +: 125C +1LSB +6LSB E-20A AD7549TE 55C to + 125C +1/2LSB +3LSB E-20A NOTES 'To order MIL-STD-883, Class B process parts, add /883B to part number. Contact your local sales office for military data sheet. ?E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip. TERMINOLOGY RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full scale error and is normally expressed in Least Significant Bits or as a percentage of full scale reading. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. A specified differential nonlinearity of 1LSB max over the operating temperature range ensures montonicity. FULL-SCALE ERROR Full scale error or gain error is a measure of the output error between an ideal DAC and the actual device output. Full scale error is adjustable to zero. OUTPUT CAPACITANCE This is the capacitance from Ioyra or Iourg to AGND. DIGITAL-TO-ANALOG GLITCH IMPULSE The amount of charge injected into the analog output when the inputs change state is called Digital-to-Analog Glitch Impulse. This is normally specified as the area of the glitch in either pA- secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Digital charge injection is measured with Vrrra, and Vrers equal to AGND. OUTPUT LEAKAGE CURRENT Output Leakage Current is current which appears at Ioytra or Iours with the DAC registers loaded to all zeros. MULTIPLYING FEEDTHROUGH ERROR This is the error due to capacitive feedthrough from Vrera to Ioura OF Vrers tO Iourg with the DAC registers loaded to all zeros. CHANNEL-TO-CHANNEL ISOLATION Channel-to-Channel Isolation refers to the proportion of input signal from one DACs reference input which appears at the output of the other DAC, expressed as a ratio in dB. DIGITAL CROSSTALK The glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as Digital Crosstalk and is specified in nV-secs. PIN CONFIGURATIONS DIP LCCC PLCC o a s nw, g sa2.2 i oa ao a a (mss) 083 [7 | o [20] Voo sugal a86 3 > ao ao a c pez [2 [13] Veer aoa 5 > > BIBIDIEID 3.2 1 20 19 DBI 3 lia] Rega a peo | 4 | 18] Resa DBO | 4 7] fouta DBO 4 - 18 Pron oF o FF 1 ups [5 ap7549 [76] aGnp wD 5 47 loura AD7549 our TOP VIEW AD7549 a2 [6 | TOP VIEW 116] AGND az [6] inotta Seale) [15] toure Az 6 TOP VIEW 16 AGND (Not to Scale} 77 (Not to Scale) 18 lo at [7] 15) loure Al 7 iia] Aras UT aR ao [s] 14] Pree AO CE] a3) Vara Ao 8 Fee ts | 9 12] DGND SQ 3 9 10 11 12 13 ay t2}Ls3) wa [0 11) ctr Ce BES? BES? & 9 > Qs a a 4- REV.A| AD7549 PIN FUNCTION DESCRIPTION 1 DB3 Data Bit 3, Data Bit 7 or Data Bit 11 (MSB) 2 DB2 Data Bit 2, Data Bit 6 or Data Bit 10. 3 DBI Data Bit 1, Data Bit 5 or Data Bit 9. 4 DBO Data Bit 0, Data Bit 4 or Data Bit 8. 5 UPD Updates DAC Registers from 4-bit input registers. DAC A and DAC B both updated simultaneously. 6 A2 Address line 2. 7 Al Address line 1. 8 AO Address line 0. 9 cs Chip Select Input. Active low. 10 WR Write Input. Active low. 11 CLR Clear Input. Active High. Clears all registers. 12 DGND Digital Ground. 13 VREFB Voltage reference input to DAC B. 14 Reap Feedback resistor of DACB. 15 lours Current output terminal of DAC B. 16 AGND Analog ground. 17 Touta Current output terminal of DAC A. 18 Resa Feedback resistor of DAC A. 19 VREFA Voltage reference input to DAC A. 20 Vpp + 15V supply input. cLR UPD CS WR aA2 Al A0/| FUNCTION 0 x xX 1 x x x No data transfer. 0 1 1 xX x x xX No data transfer. 1 xX x xX xX x x All registers cleared. 0 1 0 LW 0 0 0 DAC A LOW NIBBLE REGISTER loaded from Data Bus. 0 1 0 WT 0 0 1 DAC A MID NIBBLE REGISTER loaded from Data Bus. 0 1 0 WO 1 0 DAC A HIGH NIBBLE REGISTER loaded from Data Bus. ~ 0 1 0 Woo 1 1 DAC A Register loaded from Input Registers. 0 1 0 LE 1 0 0 DAC B LOW NIBBLE REGISTER loaded from Data Bus. 0 1 0 LL 1 0 1 DAC B MID NIBBLE REGISTER loaded from Data Bus. 0 1 0 LT 1 1 0 DAC B HIGH NIBBLE REGISTER loaded from Data Bus. 0 1 0 Wi 1 1 DACB Register loaded from Input Registers. 0 0 1 a 4 x x DAC A, DACB Registers updated simultaneously from Input Registers. NOTE: X = Don'tCare Table |. AD7549 Truth Table REV.A -5-AD7549 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Figure 2 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 2 is given in Table II. Operational amplifiers Al and A2 can be in a single package (i.e. AD644) or separate packages (AD544). Capacitors Cl and C2 provide phase compensation to help prevent overshoot and ringing when high speed op-amps are used. For zero offset adjustment, the appropriate DAC register is loaded with all Os and amplifier offset adjusted so that Voura or Vouts is at a minimum (i.e. <120V). Full scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 (R3) so that Voura (Vours) = Vin (4095/4096). In fixed reference applications, full scale can also be adjusted by omitting R1, R2, R3, R4 and trimming the reference voltage magnitude. Figure 2. AD7549 Unipolar Binary Operation BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) The recommended circuit diagram for bipolar operation is shown in Figure 3. Offset binary coding is used. With the appropriate DAC register loaded to 1000 0000 0000, adjust R1 (R3) so that Voura (Vours) = OV. Alternatively, R1, R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10) varied for Vouta (Vouts) = OV. Full scale trimming can be accomplished by adjusting the amplitude of Vpy or by varying the value of R5 (R8). Resistors R5, R6, R7 (R8, R9, R10) must be ratio matched to 0.01%. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. The code table for Figure 3 is given in Table III. RS, 20k82 RG, 20ki2 R10, 20ki2 Vee, CONTROL CIRCUITRY OMITTED FOR CLARITY Figure 3. Bipolar Operation (Offset Binary Coding) Binary Number in Binary Number in DAC Register Analog Output, Voura or Vouts DAC Register Analog Output, Voura or Vouts MSB LSB MSB LSB 1121 12111 1121 4095 L111 1211 1111 Ving (2047 -Vin{ ap08 + Vin \ 3048 f 1 1000 0000 0000 Vin (3988 } = - 12Vie 1000 0000 0001 +Vin(seae) 0000 0000 0001 Vv ( 1 ) 1000 0000 0000 OV Vin| gage ] 0000 0000 0000 OV 0111 1112 1111 - Vin (sou) Table Il. Unipolar Binary Code Table for Circuit of 2048 Figure 2 0000 0000 0000 Vaw (348) Table Ill. Bipolar Code Table for Offset Binary Circuit of Figure 3 REV.AAD7549 APPLICATION HINTS Output Offset: CMOS D/A converters in circuits such as Figures 2 and 3 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this offset, which adds to the D/A converter nonlinearity, depends on Vos where Vos is the amplifier input offset voltage. To maintain mono- tonic operation, it is recommended that Vos be no greater than (25 x 10-) (Vpeg) over the temperature range of operation. Suitable op amps are AD644L, AD517L and AD544L. The AD517L is best suited for fixed reference applications with low bandwidth requirements: it has extremely low offset (501V) and in most applications will not require an offset trim. The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset trim on the AD544L may be necessary in some circuits. Temperature Coefficients: The gain temperature coefficient of the AD7549 has a maximum value of 5ppm/C and typical value of Ippm/C. This corresponds to worst case gain shifts of 2LSBs and 0.4LSBs respectively over a 100C temperature range. When trim resistors R1(R3) and R2(R4) are used to adjust full scale range, the temperature coefficient of R1(R3) and R2(R4) should also be taken into account. High Frequency Considerations: AD7549 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compen- sation capacitor in parallel with the feedback resistor. Feedthrough: The dynamic performance of the AD7549 depends upon the gain and phase stability of the output amplifier, together with the optimum choice of PC board layout and decoupling components. A suggested printed circuit layout for Figure 2 is shown in Figure 4 which minimizes feedthrough from Vrrra, Vrers to the output in multiplying applications. Vrere Vrera Vop PIN 1 AD7549 Lo Voura PIN 8 ADE44 oo 2 1 x G\ \3 6 Pes Vours COPPER TRACKS ARE ON COMPONENT SIDE DGND OOF PRINTED CIRCUIT BOARD Figure 4. Suggested Layout for AD7549 with AD644 (Dual Op Amp) REV.A AD7549 8085A INTERFACE A typical interface circuit for the AD7549 and the 8085A micro- processor is given in Figure 5. Only the bottom 4 bits of the microprocessor data bus are used. The address decoder provides both the CS and UPD signals for the DAC. Address lines AO, Al, A2 select one of six DAC Input Registers for accepting data. In applications where simultaneous loading of the DACs is required then the UPD pin must be used to strobe both DAC registers. Otherwise, UPD may be tied high and address lines AO-A2, in conjunction with CS and WR signals, will select each DAC register separately (see Pin Function Description). A&-A1S ADDRESS BUS ) | A2-A0 8085A cs ADDRESS ALE}e| LATCH DECODE fy opp 2a ss. AD7549* wR WR FROM SYSTEM ={ CLR RESET LN ADO-AD7 DATA BUS DBO-DB3 LJ *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 5. AD7549-8085A Interface AD7549 Z80 INTERFACE Figure 6 shows the AD7549 connected to the Z80 microprocessor. The interface structure is similar to that for the 8085A. A0-A15 ADDRESS BUS | L A2-A0 z80 _ REG appress =Po] -G DECODE 4) | oo AD7549* WR wR FROM SYSTEM se] CLR RESET Do-D7 DATA BUS DBO-DB3 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 6. AD7549-Z80 InterfaceAD7549 AD7549 8048 INTERFACE The AD7549 can be interfaced to the 8048 single component microcomputer using the circuit of Figure 7. A minimum number of I/O lines are needed. The system is easily expanded by using extra port lines to provide Chip Selects for more AD7549s. The advantage of this interface lies in its simplicity. In either single or multiple DAC applications both the software and chip select decoding are simplified over what would be required if the devices were memory mapped in a conventional manner. The combination of 8048 system and AD7549 is particularly suitable for dedicated control applications. By adding reference and output circuitry a complete control system can be configured with a minimum number of components. AD7549 MC6809 INTERFACE Figure 8 is the interface circuit for the popular MC6809 8-bit microprocessor. CS and UPD signals are decoded from the address for the simultaneous update facility while the WR pulse is provided by inverting the microprocessor clock, E. A0-A15 ADDRESS BUS Mc6809 J L s z AD7549* A2-A0 RW - cs ADDRESS a DECODE pe UPD >o wr UPD JN wer Do-D7 DATA BUS DB0-DB3 cs | FROM SYSTEM ~] CLR RESET *LINEAR CIRCUITRY OMITTED FOR CLARITY *LINEAR CIRCUITRY OMITTED FOR CLARITY - Figure 8. AD7549-MC6809 Interface Figure 7. AD7549-8048 Interface g OUTLINE DIMENSIONS Dimensions shown in inches and (mm), 20-Pin Plastic DIP (N-20) 20-Pin Cerdip (Q-20) ) a 20 1 0.290 + 0.010 PIN4 0.280 (7.11) (7.366 + 0.254) 0240 one 10) 1 ANN Sor oT __ IDENTIFIER 0.325 (8.25) 1.052 + 0.011 0.300 (7.62) |, ___1.060 (26.90) 8300 7 6a) ae __ 0.020 + 0.005 : Se) le + sane 80) 0.080 (1. es 0.300 (7.62) [ aN (26.972 + 0.279) (0.508 10.127) | REF 0.210 0,015 (0.38 0.195 (4.95) 0.175 (4.45) | ae 0.115 (2.93) MAX .150 0.200 (5.05) (3.81) ff 0.015 (0.381) t F 0.150 (3.61) min 0.010 + 0.002 0.125 (3.18) MIN ae (0.254 + 0.051) > \ |e ~~ 0.022 (0.558) 0.100 (2.54) 0.070 (1.77) \ SEATING 0.020 (0.51) 0.100 (2.54) 0.05 (1.27) 0.074 (0.356) BSC 0.045 (1.15) PLANE 0.016 (0.41) TYP TYP 20-Terminal Plastic Leaded Chip Carrier (P-20A) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) | 0.048 (1.21} + rm E-20 LCCC E Package 0.358 (9.09) , 0.342 (8.69) 0.040 (1.02) x45 REF PIN1 18 0 x 3 PLCS 4 IDENTIFIER PIN1 : 0.050 (1.27) IDENTIFIER 0.028 (0.71) 0.042 (1.07) Co r] 0.350 (8.89) BSC 0.022 (0.56) 0.048 (1.21) 0.356 (9.04) qt 7 0.290 (7.37) [< U TOP view 0.985 (9.78) 0.013 (0.33) 9-330 (8.38) BOTTOM VIEW qo 4 0.995 (10.02) ee (0.53) + a.0s0 Os 14 4 0.026 (0.66) [ (727) 0.032 (0.81) a Bsc 13 a CITT Ly W%_0.020 (0.51) > be 0.015 (0.38) x 45 REF 0386 0.386 (9.04) 04) 0.025 (0.63) 0.385 (9.78) 0.025 (0.64 395 0.0 395 (10.02) oavioh 4 ; : 0.100 (2.54) 1.410 (2.79) cy 0.165 (4.19) 1.180 (4.57) -8- REV.A