Preliminary Technical Information IXDR502 / IXDS502 2 Ampere Single Low-Side Ultrafast MOSFET Drivers Features General Description * Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes * Latch-Up Protected up to 2 Amps * High 2A Peak Output Current * Wide Operating Range: 4.5V to 25V * -55C to +125C Extended Operating Temperature * High Capacitive Load Drive Capability: 1000pF in <10ns * Matched Rise And Fall Times * Low Propagation Delay Time * Low Output Impedance * Low Supply Current The IXDR502, and IXDS502 each consist of a single 2A CMOS high speed gate driver for driving the latest IXYS MOSFETs & IGBTs. Each type can source and sink 2 Amps of peak current while producing voltage rise and fall times of less than 15ns. The input of each driver is TTL or CMOS compatible and is virtually immune to latch up. Patented* design innovations eliminate cross conduction and current "shoot-through". Improved speed and drive capabilities are further enhanced by very quick & matched rise and fall times. Applications * * * * * * * * * * Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Class D Switching Amplifiers Power Charge Pumps The IXDR502 is configured as a single inverting gate driver, and the IXDS502 is configured as a single noninverting gate driver. The IXDR502, and IXDS502 are available in the 6-Lead DFN (D1) package, which occupies less than 20% of the board area of a typical 8-Pin SOIC package. *United States Patent 6,917,227 Ordering Information Part Number Description IXDR502D1B IXDR502D1BT/R IXDS502D1B IXDS502D1BT/R 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. Package Type 6-Lead DFN 6-Lead DFN 6-Lead DFN 6-Lead DFN Packing Style 2" x 2" Waffle Pack 7" Tape and Reel 2" x 2" Waffle Pack 7" Tape and Reel Pack Qty 121 2500 121 2500 Configuration Single Inverting Driver Single NonInverting Driver NOTE: All parts are lead-free and RoHS Compliant DS99909(10/07) Copyright (c) 2007 IXYS CORPORATION All rights reserved First Release IXDR502 / IXDS502 Figure 1 - IXDS502 Non-Inverting 2A Gate Driver Functional Block Diagram Vcc P ANTI-CROSS CONDUCTION CIRCUIT * IN OUT N GND GND Figure 2 - IXDR502 Inverting 2A Gate Driver Functional Block Diagram Vcc P IN ANTI-CROSS CONDUCTION CIRCUIT * OUT N GND GND * United States Patent 6,917,227 Copyright (c) 2007 IXYS CORPORATION All rights reserved 2 IXDR502 / IXDS502 Absolute Maximum Ratings (1) Operating Ratings (2) Parameter Supply Voltage All Other Pins Junction Temperature Storage Temperature Lead Temperature (10 Sec) Parameter Value Operating Supply Voltage 4.5V to 25V Operating Temperature Range -55 C to 125 C Package Thermal Resistance * J-A(typ) 125-200 C/W 6-Lead DFN (D1) 6-Lead DFN (D1) J-C(max) 3.3 C/W 6-Lead DFN (D1) J-S(typ) 7.3 C/W Value 35V -0.3 V to VCC + 0.3V 150 C -65 C to 150 C 300 C Electrical Characteristics @ TA = 25 oC (3) Unless otherwise noted, 4.5V VCC 25V . All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. Symbol Parameter Test Conditions Min VIH High input voltage 4.5V VCC 18V 2.5 VIL Low input voltage 4.5V VCC 18V VIN Input voltage range IIN Input current VOH High output voltage VOL tR Low output voltage High state output resistance Low state output resistance Peak output current Continuous output current Rise time tF ROH ROL IPEAK IDC 0V VIN VCC Typ(4) Max Units V 1.0 V -5 VCC + 0.3 V -10 10 A VCC - 0.025 V 0.025 V VCC = 15V 3 4 VCC = 15V 2.2 3 VCC = 15V 2 A 0.5 A CLOAD = 1000pF VCC = 15V 7.5 12 ns Fall time CLOAD = 1000pF VCC = 15V 6.5 10 ns tONDLY ON propagation delay CLOAD = 1000pF VCC = 15V 25 35 ns tOFFDLY OFF propagation delay CLOAD = 1000pF VCC = 15V 20 30 ns VCC Power supply voltage 15 25 V ICC Power supply current 1 0 2 15 15 mA A A 4.5 VIN = 3.5V VIN = 0V VIN = +VCC, (4.5V VCC 18V) IXYS reserves the right to change limits, test conditions, and dimensions. 3 IXDR502 / IXDS502 Electrical Characteristics @ temperatures over -55 oC to 125 oC (3) Unless otherwise noted, 4.5V VCC 22V , Tj < 150oC All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. Symbol Parameter Test Conditions Min VIH High input voltage 4.5V VCC 15V 3.5 VIL Low input voltage 4.5V VCC 15V VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH tR Output resistance @ Output high Output resistance @ Output Low Continuous output current Rise time tF tONDLY 0V VIN VCC Typ Max Units V 0.8 V -5 VCC + 0.3 V -20 20 A VCC - 0.05 V 0.05 V VCC = 15V 6 VCC = 15V 4 0.3 A CL=1000pF Vcc=15V 14 ns Fall time CL=1000pF Vcc=15V 12 ns CL=1000pF Vcc=15V 40 ns CL=1000pF Vcc=15V 35 ns VCC On-time propagation delay Off-time propagation delay Power supply voltage 15 22 V ICC Power supply current 1 0 3 10 10 mA A A ROL IDC tOFFDLY 4.5 VIN = 3.5V VIN = 0V VIN = + VCC, (4.5V VCC 18V) Notes: 1. Operating the device beyond the parameters listed as "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The device is not intended to be operated outside of the Operating Ratings. 3. Electrical Characteristics provided are associated with the stated Test Conditions. 4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function. * The following notes are meant to define the conditions for the J-A, J-C and J-S values: 1) The J-A (typ) is defined as junction to ambient. The J-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the J-A value supposes the DFN package is soldered on a PCB. The J-A (typ) is 200 C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the J-A by adding connected copper pads or traces on the PCB. These can reduce the J-A (typ) to 125 C/W easily, and potentially even lower. The J-A for DFN on PCB without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what they are likely to get if no thermal management is done. 2) J-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The J-C values are generally not published for the PDIP and SOIC packages. The J-C for the DFN packages are important to show the low thermal resistance from junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe. 3) The J-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the DFN package. Copyright (c) 2007 IXYS CORPORATION All rights reserved 4 IXDR502 / IXDS502 Pin Description PIN NUMBER SYMBOL FUNCTION DESCRIPTION 1 IN Signal Input 2 Vcc Supply Voltage 3 OUT Drive Output 4,5,6 GND Ground Input signal-TTL or CMOS compatible. Positive power supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 25V. Driver output. For application purposes, this pin is connected via a resistor to the gate of a MOSFET or IGBT. The drivers ground pins. Internally connected to all circuitry, these pins provide ground reference for the entire device. These pins should be connected to a low noise analog ground plane for optimum performance. CAUTION: Follow proper ESD procedures when handling and assembling this component. Pin Configuration IXDR 6 Lead DFN (D1B) (Bottom View) IXDS 6 Lead DFN (D1B) (Bottom View) GND 6 1 IN GND 6 1 IN GND 5 2 Vcc GND 5 2 Vcc GND 4 3 OUT GND 4 3 OUT NOTE: Solder tabs on bottoms of DFN packages are grounded Figure 3 - Characteristics Test Diagram Vcc 1 2 3 10uF 0.01uF IN Vcc OUT 6 GND 5 GND 4 GND Agilent 1147A Current Probe 1000 pF IXYS reserves the right to change limits, test conditions, and dimensions. 5 IXDR502 / IXDS502 Typical Performance Characteristics Fig. 4 Fig. 5 Fall Time vs. Supply Voltage Rise Time vs. Supply Voltage 80 70 70 60 10000pF Fall Time (ns) Rise Time (ns) 60 50 40 5400pF 30 50 10000pF 40 30 5400pF 20 20 1000pF 560pF 5 10 15 20 25 560pF 0 0 0 1000pF 10 10 30 35 0 40 5 15 20 25 30 35 40 Supply Voltage (V) Supply Voltage (V) Rise / Fall Time vs. Temperature VSUPPLY = 15V CLOAD = 1000pF Fig. 6 10 Fig. 7 Rise Time vs. Capacitive Load 90 12 5V 70 Rise time Rise Time (ns) Rise / Fall Time (ns) 80 10 8 Fall time 6 4 10V 60 15V 20V 50 40 30 20 2 10 0 -50 0 50 100 0 100 150 1000 Temperature (C) Fig. 8 10000 Load Capacitance (pF) Fig. 9 Fall Time vs. Capacitive Load 70 Input Threshold Levels vs. Supply Voltage 2.5 5 50 Threshold Level (V) Fall Time (ns) 60 10V 15V 20V 40 30 20 2 Positive going input 1.5 Negative going input 1 0.5 10 0 100 0 1000 0 10000 10 15 20 25 Supply Voltage (V) Load Capacitance (pF) Copyright (c) 2007 IXYS CORPORATION All rights reserved 5 6 30 35 40 IXDR502 / IXDS502 Fig. 10 Input Threshold Levels vs. Temperature 3 40 Propagation Delay Time (ns) Input Threshold Level (V) Propagation Delay vs. Supply Voltage Rising Input, CLOAD = 1000pF Fig. 11 2.5 2 Positive going input 1.5 Negative going input 1 0.5 35 30 Non-Inverting 25 20 Inverting 15 10 5 0 0 -50 0 50 100 0 150 5 10 15 Temperature (C) 30 35 40 Propagation Delay vs. Temperature VSUPPLY = 15V CLOAD = 1000pF Fig. 13 40 Propagation Delay Time (ns) 45 Propagation Delay Time (ns) 25 Supply Voltage (V) Propagation Delay vs. Supply Voltage Falling Input, CLOAD = 1000pF Fig. 12 20 40 35 30 Inverting 25 20 Non-Inverting 15 10 5 35 Negative going input 30 25 Positve going input 20 15 10 5 0 0 0 5 10 15 20 25 30 35 -50 40 0 50 100 150 Temeprature (C) Supply Voltage (V) Quiescent Current vs. Temperature Fig. 14 Fig. 15 Quiescent Current vs. Supply Voltage Quiescent Current (uA) Quiesent Current (uA) VSUPPLY = 15V 1000000 10000 1000 Inverting/Non-inverting Input = "1" 100 10 Inverting Input = "0" Non-inverting Input = "0" 1 100000 Non-inverting, Input= "1" Inverting, Input= "0" 10000 1000 Inverting, Input= "1" 100 10 Non-inverting, Input= "0" 1 0.1 0.1 0 5 10 15 20 25 30 35 40 -50 Supply Voltage (V) 0 50 Temperature (C) 7 100 150 IXDR502 / IXDS502 Supply Current vs. Capacitive Load VSUPPLY = 5V Fig. 16 100 100 2MHz 80 70 60 50 1MHz 40 30 20 10 80 70 60 5400pF 50 40 30 20 1000pF 10 100kHz 1000 10000pF 90 Supply Current (mA) Supply Current (mA) 90 0 100 Supply Current vs. Frequency VSUPPLY = 5V Fig. 17 560pF 0 100 10000 Load Capacitance (pF) 200 2MHz 180 Supply Current (mA) 140 120 100 10000pF 180 160 Supply Current (mA) Supply Current vs. Frequency VSUPPLY = 10V Fig. 19 200 1MHz 80 60 40 20 160 140 120 5400pF 100 80 60 40 1000pF 20 560pF 100kHz 0 100 1000 0 100 10000 Load Capacitance (pF) 1000 Supply Current vs. Frequency VSUPPLY = 15V Fig. 21 300 300 10000pF 250 Supply Current (mA) Supply Current (mA) 2MHz 200 150 1MHz 100 50 250 200 5400pF 150 100 50 1000pF 560pF 100kHz 0 100 10000 Frequency (kHz) Supply Current vs. Capacitive Load VSUPPLY = 15V Fig. 20 10000 Frequency (kHz) Supply Current vs. Capacitive Load VSUPPLY = 10V Fig. 18 1000 1000 0 100 10000 Load Capacitance (pF) Copyright (c) 2007 IXYS CORPORATION All rights reserved 1000 Frequency (kHz) 8 10000 IXDR502 / IXDS502 Supply Current vs. Capacitive Load VSUPPLY = 20V Fig. 22 Supply Current vs. Frequency VSUPPLY = 20V Fig. 23 400 400 10000pF 2MHz 350 Supply Current (mA) Supply Current (mA) 350 300 250 200 1MHz 150 100 300 250 5400pF 200 150 100 1000pF 50 50 100kHz 0 100 1000 560pF 0 100 10000 1000 Frequency (kHz) Load Capacitance (pF) Output Sink Current vs. Supply Voltage 7 0 6 -1 5 Sink Current (A) Source Current (A) Fig. 25 Output Source Current vs. Supply Voltage Fig. 24 4 3 2 1 -2 -3 -4 -5 -6 0 -7 0 5 10 15 20 25 30 35 40 0 5 10 Supply Voltage (V) 15 20 25 30 35 40 Supply Voltage (V) Output Source Current vs. Temperature VSUPPLY = 15V Fig. 26 Output Sink Current vs. Temperature VSUPPLY = 15V Fig. 27 3.5 0 3 -0.5 Output Sink Current (A) Output Source Current (A) 10000 2.5 2 1.5 1 0.5 -1 -1.5 -2 -2.5 -3 -3.5 0 -50 0 50 100 -50 150 0 50 Temperature (C) Temperature (C) 9 100 150 IXDR502 / IXDS502 Fig. 29 Fig. 28 High State Output Resistance vs. Supply Voltage Output Resistance (ohms) 6 Output Rsistance (ohms) Low State Output Resistance vs. Supply Voltage 4.5 5 4 3 2 1 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0 5 10 15 20 25 30 35 0 40 Supply Voltage (V) 5 10 15 20 25 30 35 40 Supply Voltage (V) Supply Bypassing, Grounding Practices And Output Lead Inductance When designing a circuit to drive a high speed MOSFET utilizing the IXD_502, it is very important to observe certain design criteria in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXD_502 to charge a 1500pF capacitive load from 0 to 25 volts in 25ns. Using the formula: I= V C / t, where V=25V C=1500pF & t=25ns, we can determine that to charge 1500pF to 25 volts in 25ns will take a constant current of 1.5A. (In reality, the charging current won't be constant, and will peak somewhere around 2A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXD_502 must be able to draw this 1.5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected and should have low inductance, low resistance and high-pulse current-service ratings). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXD_502 to an absolute minimum. Copyright (c) 2007 IXYS CORPORATION All rights reserved GROUNDING In order for the design to turn the load off properly, the IXD_502 must be able to drain this 1.5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXD_502 and its load. Path #2 is between the IXD_502 and its power supply. Path #3 is between the IXD_502 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXD_502. OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and its load as short and wide as possible. If the driver must be placed farther than 2" (5mm) from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load. 10 IXDR502 / IXDS502 0.013 [0.32] 0.0350.004 [0.900.10] ] IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com 0.010 [0.26] 0.012 [0.30] 0.020 [0.50] [ S0.002^0.000; o S0.05^0.00;o 0.012 [0.30] 0.008 [0.20] 0.008 [0.20] 0.044 [1.12] 0.054 [1.36] 0.0790.004 [2.000.10] 0.0790.004 [2.000.10] IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de 11