M37730S2AFP,M37730S2BFP M37730S2FP and M37730S2SP M37730S 2ASP ; M37730S2BSP are unified respectively into M37730S2AFP and M37730S2ASP. MITSUBISHI MICROCOMPUTERS 16-BIT CMOS MICROCOMPUTER DESCRIPTION The M37730S2AFP, and M37730S2BFP are 16-bit micro- computers designed with high-performance CMOS silicon gate technology. These are housed in a 64-pin plastic molded QFP. These microcomputers have a large 16M bytes address space, three instruction queue buffers, and two data buffers for high-speed instruction execution. The CPU is a 16-bit parallel processor that can also be switch- ed to perform 8-bit parallel processing. These microcompu- ters are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. M37730S2ASP, and M37730S2BSP are also prepared. These are housed in a 64-pin shrink plastic molded DIP. The differences of these types are the external clock input frequency and package. Therefore, the following descrip- tions will be for the M37730S2AFP unless otherwise noted. - Type name " External clock input frequency Package M37730S2AFP_ SS _16MHz S4PEN | M37730S2BFP 25MHz 64P6N -M37730S2ASP 16MHz 64P4B M37730S2BSP_ so 25MH2si<t**S PWS FEATURES @ Number of basic instructions::--\-- 103 Memory size RAM ccc cee tet teeters 1024 bytes @ Instruction execution time M37730S2AFP, M37730S2ASP (The fastest instruction at 16 MHz frequency)----- 250ns M37730S2BFP, M37730S2BSP (The fastest instruction at 25 MHz frequency) --:--- 160ns e Single power supply ee ee errs 5V4+10% @ Low power dissipation (at 16 MHz frequency) see beeen ene eee ce nenannes 60mW (Typ.) e Interrupts er eee eee eee ee eee eee @ Multiple function 16-bit timer - @ UART (may also be synchronous) 1 1 @ 12-bit watchdog timer @ Programmable input/output (ports P4, P5, P6, P8) ee eee en etek ene eee 25 e Pulse output port Dene eee een cere ener eens censeneneenes 4-bitX 2 The M37730S2AFP and M37730S2ASP satisfy the timing requirements and the switching characteristics of the for- mer M37730S2FP and M37730S2SP. PIN CONFIGURATION (TOP VIEW) 2 WY g [oat Feywd LES PTE eES fze222 Soc See e ge Se oeee RRRRRReSRPRR Pec de Pep pps? t ptrrtittt fe Er] ol Bs] Bal 7 bs PBo/TAdgur/RTP15 = (1) [a] > Ay P5;/TA3y 2] > As P5/TASqur/RTP12 + GB] P5</TA2/ATPI, ++ [] Pog/TAZgur/RTP Ig + P53/TAI /RTPOs + [E| PS2/TAT guy/RTPO, ++ [| P5,/TAOn/RTPO, ++ [2] P5o/TA0 ou r/RTP0, + Le] P4,/DBC* ++ Pc/VPA* + [ii] do djgdzsoc./enw dAVZSOEZZew El] t > o Pas/VDA* [12] Ay, Dis Pa/OCL* +> [3] mAs Co P4g/MX* ++ [1] +ALL 91 +A Dy RDY Aw Cs Ey el 2] frtrtrbb seabed argt oe Saez eh eeyeeagad 0% 2 |8 x 2tHEzRES regyv = cide Vec ++ P8o/CTSy/RTSp P6; + 3} +> P8,/CLK, Pe > => P82/RxDp P65/TBOy + + PB3/TxDo P6,/INT2 + Ao P63/INT, ++ [6] Ay P62/INTg + + Ap P6,/TA4y + [8] A P6/TA4qur/RTP13 + [3] aA, P5,/TASy As P56/TASQut/RTP12 + As P53/TA2y/RTP1, + A, P54/TA2gur/RTPtyg z z +> Ag/Dg P59/TAly/RTPO, s 8 ++ Ac/Do P52/TAtour/RTPO, + a oa + Aio/Dio PS5,/TAG/RTPO, + [el OB & Ayn P5o/TAQgut/RTPO > o + Ay2/Di2 P4;/DBC* ++ [ig] % 2 Ay3/Dig P4g/VPA* ++ > Aya/Dia P4./VDA* + + Ays/Dis P4,/QCL* + + Aje/Do P43/MX* <> = AY7/D, Oye + Ay,/Dz RDY > + Aro/D3 HOLD > + Azo/Da BYTE > + Az,/Ds CNVs5 * ** Azo/Dg RESET Ao3/D7 Xin R/W Xour p]> BHE E+ ALE Vss HLDA Outline 64P4B * - Used in the evaluation chip mode only MITSUBISHI 2-457 ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER td vod Gd vod 9d wod snq Ssoppy snq reg; snq ssolppy siding anduy gndyacyanduit wdyng vnduy, as rer EXIGE) OP) rene Ta 4 aera - LL yyy amo} SSBuPPY C 91:80 /,8/pNu sauB1U ssasppy if il , | i Li j L Lf fr ft i Ut iL _ Ul ft Ui, Ui Ue { (6)0luvn ff (gtjogs aun | [gtove seu | soidg ZO dau, Bopyoyem| | (SL) bWL sow WVvdY (91)2w1 sous i Data Bus(Odd) Data Bus(Even) Address Bus (QIJEWL FOUL (91) PV soul x | ee a ~~) Lal yh |] ij |i Py: [ro | i | || L ; 1 li 4 : LZ ly srr ~ TVS TWA fel : @ | Joo S| la] ]s alla] |< aller Pedy o ete i<clfelfsl fey} ~ STITT ays e]]* SUIS ISHelle 4 i a] | a Syyeyis V2, ]s etPey Pegs 3 SPST) >] [= Tas] fe] | g > 2 2 ro a BS ao = 2 & . a 1 a ' ete Ae B) 12] | 5 Serena) ove} Tete Shap fatenlal zg 2||5 ALE {fal le Stetleif E 21/811] Por St] sy]: i SF Slls x 2 y 3s 2 z > z Sida: . alla ST1a]]6 ES 3 : ell 2 alee et [elle ElLEeE | = Vi oll o sils}]s STIs slietielda a sell si tx] <tP sy ps | | fii alls oPpPap ls f1is|]< Siieliec s STISTISP LoL oles io ii Si] s 2llelie =TTSI 1 file oT ls a STIS TlslL Pol Pole ile] |! ! oyya ay) aypa Sit |s 8 eiyc < TST Tel TEti << : | { ; 1 ETEE & 5 sg & & 4 Li J= iy i | | i ' ti |! rit i i: 1} _] cl | | ; : | il | in} LUTE UU DS ati | imal i i ILA vv Ae WEE | Liss IT q ko L KH Ky P= M4 BU Us? UND Buyesauay y9019 ' L bo bh ke beg bb 4 8 6S SS os f ALAS AQGY ag1OH M/d 3Ha av VYOIH AND PAN O" LAS3Y a nde snoy NI INdW VONDBIIS uy indus inding ajqrua aiqeua weubs (AS AO AS indui yasay inding aiqeug yndino 42012 Indu 49019 unpim sng 1g #9010 Apeay jsanbas pio auspeay Yyby ag ude ssauppy abpaimouyoe PICH WVHSVIC NOO1E dAaVcSOELZEN PR 2458MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP ,M37730S2BSP 16-BIT CMOS MICROCOMPUTER FUNCTIONS OF M37730S2AFP Parameter Functions Number of basic instructions 103 M37730S2AFP, M37730S2ASP 250ns (the fastest instruction at external clock 16MHz frequency} Instruction execution time M37730S2BFP, M37730S2BSP 160ns (the fastest instruction at external clock 25MHz frequency) Memory size _ RAM 1024 bytes | PS. Pb 8 -bitx 2 | Input/Output ports Pa 8 bit 7 BO P8 4-bitX 1 7 | Multi-function timers | TAO, TAN TA2, TAS, TAA __16:bi< 5 oo TBO 16-bitX 1 __| Serial 1/0 (UART or clock synchronous serial 1/O) X | - | Watchdog timer : 12-bitx 1 interrupts 3 external types, 11 internal types (Each interrupt can be set the priority levels to 0 ~ 7.) Clock generating circuit Built-in( externally connected to a ceramic resonator or quartz crystal resonator) | Supply voltage Power dissipation V+410% ; 60mW (at external clock 16MHz frequency? * Input/Output voltage Input/Output characteristic Output current Memory space Operating temperature range 16M bytes ; ~20~85'C Device structure Package M37730S2ASP, M37730S2BSP CMOS high-performance silicon gate process 64-pin plastic molded QFP 64-pin shrink plastic molded DIP APPLICATION Control devices for office equipment such as copiers, prin- ters, typewriters, facsimiles, word processors, personal computers, and HDD Control devices for industrial equipment such as ME, NC, communication and measuring instruments NOTE Refer to Chapter 5 PRECAUTIONS when using this mic- rocomputer. ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin Name Input/Output Functions Voc. Vss Power supply Supply 5 V+10% to Voc and 0 V to Vss. CNVss CNVsz input Input Connect to Voc. RESET Reset input Input To enter the reset state, this pin must be kept at a L" condition which should be maintained for the re- quired time. Xi Clock input Input These are 1/0 pins of internal clock generating circuit. Connect a ceramic of quartz crystal resonator be- tween Xin and Xoyr. When an external clock is used, the clock source should be connected to the Xw pin Xout Clock output Output and the Xour pin shauld be left open. E Enable output Output Data or instruction read and data write are performed when output from this pin is L. BYTE Bus width selection input Input This pin determines whether the external data bus is 8-bit width or 16-bit width. The width is 16 bits when L signal inputs and 8 bits when H signal inputs. 9; Clock output Qutput | This pin outputs the clock , which is divided the clock to Xin pin by 2. ROBY Ready input This is ready input pin. This is an input pin for the RDY signal. Internal clock stops while this signal is L. HOLD Hold request input Input This is an input pin for HOLD request signal. The microcomputer enters into hold state white this signal is . Le, HLDA Hold acknowledge output | Output This is an output pin for HLDA signal, indicates the hold state. R/W Read/Write output Output H" indicates the read status and L indicates the write status. BHE Byte high enable output} Output L" is output when an odd-numbered address is accessed. ALE Address latch enable Output This is used to retrieve only the address data from address data and data multiplex signal. output Ag~Ar Address (low-order) Output | Address (A7~Ao) is output. Output As/De~ Address (middle-order) Vo In case the BYTE pin is L and an external data bus is 16-bit width, high-order data (Dys~ Dg) is input or Ais/Dis output/Data (high-order) output when E output is L and an address (Ais~Ag) is output when E output is H. In case the BYTE pin VO is H" and an external data bus is 8-bit width, only address (Ays~Ag) is output. Ayg/Do~ Address (high-order) vo Low-order data (D7~Dg) is input or output when E output is L, and an address (Azs~ Aig) is output when Aza/D7 output/Data (low-order) E output is H. vO P43~P4, 1/0 port P4 vo Port P4 is a 5-bit 1/O port. This port has an data direction register and each pin can be programmed for in- put or output. This port is in input mode when reset. PSp~P57 1/0 port P5 vo Port P5 is a 8-bit I/O port. This port has an data direction register and each pin can be programmed for in- put or output. This port is in input mode when reset. These pins also function as 1/O pins for timer AQ, timer A1, timer A2 and timer A3. P6y~P67 1/0 port P6 0 In addition to having the same functions as port P5, these pins also function as I/O pins for timer A4, exter- nal interrupt input INTo, INT, and INT2 pins, and input pin for timer BO. P8y~P83 1/0 port P8 0 Port P8 is a 4-bit I/O port. This port has an data direction register and each pin can be programmed for in- put or output. This port is in input mode when reset. These pins also function as RxD, TxD, CLK, CTS/RTS pins for UARTO. >to oe ESMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS The M37730S2AFP contains the following devices on a chip: RAM for storing data, CPU for processing, bus inter- face unit (which controls instruction prefetch and data read/write between CPU and memory), timers, UART, and other peripheral devices such as I/O ports. Each of these devices are described below. MEMORY The memory map is shown in Figure 1. The address space is 16M bytes from addresses 016 to FFFFFF,. The address space is divided into 64K bytes units called banks. The banks are numbered from Oy to FF i 6. Built-in RAM and control registers for built-in peripheral de- vices are assigned to bank 0,.. Addresses FFDC,, to FFFF,, are the RESET and interrupt vector addresses and contain the interrupt vectors. Use ROM for memory of this address. Refer to the section on interrupts for details. The 1024 bytes area from addresses 80, to 47F,,_ contains the built-in RAM. In addition to storing data, the RAM is used as stack during a subroutine call, or interrupts. Assigned to addresses 0,, to 7Fig are peripheral devices such as I/O ports, UART, timer, and interrupt control regis- ters. A 256 bytes direct page area can be allocated anywhere in bank 0O;, using the direct page register DPR. In direct page addressing mode, the memory in the direct page area can be accessed with two words thus reducing program steps. 000000,, ~ ~000000,. -s 000000, oo0na0. Peripheral devices Bank 0, | i \ \ control registers t I SS ( see Fig. 2 for \ OOFFFF i. I ~_e Internal RAM N . further tomato] f 0100005 [7 + 1024 bytes 00007F 3 | | Bank The \ 00047F,, Interrupt vector table OFFFFs Joo 4d \ 1 OOFFOC se TUARTO transmission] | I | / 4 VARTO receive | : ! I \ fot i a 1) a : t 1 | L (1 Timer ad . T T \ T I Timer A4 ' 7 i fof Deo 7 | i \ | / -~ =e _ \ / | Timer Al i ( Fe00004 [TT 7 \ bo [7 Timerad | | \ 1 TO WET TT _) | { | ; iw rere} | I Ne _ | FFO000,., 1 l {/ i Watchdog timer | | | \ 1 ~ ORCL Bank FFi \ 1 OOFFOC:6 -+--_ + i_ BRK instruction | | l 1. _ Zefa divide 1 FEFFFF.g Po a oorFFF., Lo J _ _OOFFFE,,! RESET I Cl] : Internal Los > External Fig. 1 Memory map MITSUBISHI ELECTRIC 2--461MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP ,M37730S2BSP 16-BIT CMOS MICROCOMPUTER Address (Hexadecimal notation) _ Address (Hexadecimal notation) 000000 i 000040 Count start flag 000001 000041 | 900002 000042 One-shot start flag 00003 000043 000004 _ 000044 Up-down flag 000005 _ ee 000045 | __ 000006 000046 . oo0007 ~ : coooa7 | Timer AO 000008 000048 . 00009 _ ooooag | Timer At ee OOCOOA | Port P4 000044 Timer A2 000008 | Port PS 000048 o0000C =| Port P4 data direction register 00004C Timer A3 00000D Port P5 data direction register - : 00004D _ __ i 00000E | Port P6 ; O0004E | + er ad QO000F i 00004F 000010 Port P6 data direction register os 000050 . 000017 _ oooos1 | Timer BO ee 000012 Port P8 000052 | oe __ oo 000013 oe 000053 000014 Port P8 data direction register 000054 000015 aoe _ 000055 000016 coe _. 000056 000017 _ _ 000057. Timer Ai mode register . 000018 | oe 000058 Timer A2 mode register a 000019 _ . 000059 Timer A3 mode register 00001A oe oe 00005A =| Timer A4 mode register . a 00001B , 00005B Timer BO mode register . 00001C _. o000sc | _ oo, 000010 _ . 00005D _ oo oe OO001E _ oo QOO0SE Processor mode register O0001F ; - . _. 00005F _ oe 000020 000060 | Watchdog timer oo 000021 _ 000061 Watchdog timer frequency selection flag 000022 oe . . 000062 Wavetorm output mode register 000023 . 000063 - 000024 | ee oe 000064 Pulse output data register 1 000025 . 000065 | Pulse output data register 0 Gj 000026 000066 000027, | ee 000067 fe . : 000028 _ 000068 ooo09 a OOO06A 00006B oo006C 00006D : OO006E a oo0002F ; Oo0o06F . 000030 | UART 0 transmit/receive mode register 000070 000031 UART 0 bit rate generator 000071 UARTO transmission interrupt control register ooboes UART 0 transmission buffer register oe UARTO receive interrupt control register ! 000034 UART 0 transmit/receive control register 0 000074 _ ; 000035 UART 0 transmit/receive control register 1_ 000075 Timer AO interrupt control register 000036 . . 000076 Timer A1 interrupt control register 000037 UART 0 receive buffer register 000077 Timer A2 interrupt control register | 000038) | oe 000078 Timer A3 interrupt control register ; 000039, _ oe 000079 Timer A4 interrupt control register a 00003A Le 00007A Timer BO interrupt control register 00003B ; 000078 _ oo _ 00003C . 00007C _ ee _ 000030 00007D | INTo interrupt control register OO0cOSE = oe 00007E INT, interrupt control register 00003F oe 00007F | INTz interrupt control register Fig. 2. Location of peripheral devices and interrupt control registers _ MITSUBISHI 2462 ate MISESMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP ,M37730S2BSP 16-BIT CMOS MICROCOMPUTER CENTRAL PROCESSING UNIT (CPU) The CPU has ten registers and is shown in Figure 3. Each of these registers is described below. ACCUMULATOR A (A) Accumulator A is the main register of the microcomputer. It consists of 16 bits and the lower 8 bits can be used separ- ately. The data length flag m determines whether the regis- ter is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is 0 and as an 8-bit reg- ister when flag m is 1. Flag m is a part of the processor status register (PS) which is described tater. Data operations such as calculations, data transfer, input/ output, etc., is executed mainly through the accumulator. ACCUMULATOR B (B) Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A. INDEX REGISTER X (X) Index register X consists of 16 bits and the lower 8 bits can be used separately. The index register length flag x deter- mines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is 0 and as an 8-bit register when flag x is 1. Flag x is a part of the processor status register (PS) which is de- scribed later. In index addressing mode, register X is used as the index register and the contents of this address is added to obtain the real address. Also, when executing a block transfer instruction MVP or MVN, the contents of index register X indicate the low- order 16 bits of the source data address. The third byte of the MVP and MVN is the high-order 8 bits of the source data address. INDEX REGISTER Y (Y) Index register Y consists of 16 bits and the lower 8 bits can be used separately. The index register length flag x deter- mines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is 0 and as an 8-bit register when flag x is 1. Flag x is a part of the processor status register (PS) which is de- scribed later. In index addressing mode, register Y is used as the index register and the contents of this address is added to obtain the real address. Also, when executing a block transfer instruction MVP or MVN, the contents of index register Y indicate the low- order 16 bits of the destination address. The second byte of the MVP and MVN is the high-order 8 bits of the destina- tion data address. 15 7 0 | Ay ml AL | Accumulator A 15 7 0 | By ' B, | Accumulator B 15 7 0 | Xu | XL | index register X 15 7 0 | Yu | Y | Index register Y 19 0 Z o | s | Stack pointer Program bank register PG 7 a 7 0 | PC | Program counter PC Data bank register DT ib 0 | DPR | Direct page register DPR j Q 5 7 {o comme) 10 0 [ea] ule N v m| x} o] ifzic] Processor status register PS TTT TY | } | Carry tlag Zero fla interrupt disable flag Decimal mode flag Index register length flag Data length flag Overtiow tlag Negative flag Processor interrupt priority level IPL | yl lic Fig. 3 Register structure MITSUBISHI ELECTRIC 2463MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER STACK POINTER (S) Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect in- dexed Y addressing mode. PROGRAM COUNTER (PC) Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program mem- ory is accessed through bus interface unit. This is de- scribed later. PROGRAM BANK REGISTER (PG) Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the cotents of the program bank register (PG) is incremented by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) using branch instruction, the contents of the program bank register (PG) is incremented or decremented by 1 so that programs can be written without worrying about bank boundaries. DATA BANK REGISTER (DT) Data bank register (DT) is an 8-bit register. With some addressing modes, a part of the data bank register (DT) is used to specify a memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24- bit address. Addressing modes that use the data bank reg- ister (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y. DIRECT PAGE REGISTER (DPR) Direct page register (DPR) is a 16-bit register. Its contents is used as the base address of a 256-byte direct page area. The direct page area is allocated in bank 0, but when the contents of DPR is FFO1,, or greater, the direct page area spans across bank 0., and bank 1,.. All direct addres- sing modes use the contents of the direct page register (DPR) to generate the data address. If the low-order 8 bits of the direct page register (DPR) is 00,,_, the number of cycles required to generate an address is minimized. Nor- mally the low-order 8 bits of the direct page register (DPR) is set to 00,,. PROCESSOR STATUS REGISTER (PS) Processor status register (PS) is an 11-bit register. It con- sists of a flag to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags C, Z, V, and N. The details of each processor status register bit are de- scribed below. 1. Carry flag (C) The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC and CLC instructions or with the SEP and CLP instructions. 2. Zero flag (Z) This zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions. 3. interrupt disable flag (!) When the interrupt disable flag is set to 1, all interrupts except watchdog timer, DBC, and software interrupt are disabled. This flag is set to 1 automatically when these is an interrupt. It can be set and reset directly with the SEI and CLI instructions or SEP and CLP instructions. 4. Decimal mode flag (D) The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is performed when this flag is O. If it is 1", de- cimal arithmetic is performed with each word treated as two or four digit decimal. Arithmetic operation is performed using four digits when the data length flag m is O and with two digits when it is 1. (Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions. 2464 ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 5. Index register length flag (x) The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit regis- ters when flag x is 0 and as 8-bit registers when it is 1. This flag can be set and reset with the SEP and CLP in- structions. 6. Data length flag (m) The data length flag determines whether the data length is 16-bit or 8-bit. The data length is 16-bit when flag m is 0 and 8-bit when it is 1. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP in- structions. 7. Overflow flag (V) The overflow flag has meaning when addition or subtraction is performed a word as signed binary number. When the data length flag m is 0, the overflow flag is set when the result of addition or subtraction is outside the range be- tween 32768 and + 32767. When the data length flag m is 1, the overflow flag is set when the result of addition or subtraction is outside the range between 128 and +127. It is reset in all other cases. The overflow flag can also be set and reset directly with the SEP, and CLV or CLP in- structions. 8. Negative flag (N) The negative flag is set when the result of arithmetic op- eration or data transfer is negative (If data length flag m is 0, when data bit 15 is 1. If data length flag m is 1, when data bit 7 is 1".) It is reset in all other cases. It can also be set and reset with the SEP and CLP instructions. 16-BIT CMOS MICROCOMPUTER 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7. Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the in- terrupt control register) is higher than the processor inter- rupt priority. When interrupt is enabled, the current proces- sor interrupt priority level is saved in a stack and the pro- cessor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. BUS INTERFACE UNIT The CPU operates on an internal clock frequency which is obtained by dividing the external clock frequency f.x,) by two. This frequency is twice the bus cycle frequency. In order to speed-up processing, a bus interface unit is used to pre-fetch instructions when the data bus is idle. The bus interface unit synchronizes the CPU and the bus and pre- fetches instructions. Figure 4 shows the relationship be- tween the CPU and the bus interface unit. The bus inter- face unit has a program address register, a 3-byte instruc- tion queue buffer, a data address register, and a 2-byte data buffer. The bus interface unit obtains an instruction code from memory and stores it in the instruction queue buffer, obtains data from memory and stores it in the data buffer, or writes the data from the data buffer to the memory. CPU Control signal Bus interface BHE unit Thy Fig. 4 Relationship between the CPU and the bus interface unit ae MRS 2-465MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER The bus interface unit operates using one of the waveforms (1) to (6) shown in Figure 5. The standard waveforms are (1) and (2). The ALE signal is used to iatch only the address signa! from the multiplexed signal containing data and address. The E signal becomes L when the bus interface unit reads an instruction code or data from memory or when it writes data to memory. Whether to perform read or write is controlled by the R/W signal. Read is performed when the R/W signal is H" state and write is performed when it is L state. Waveform (1) in Figure 5 is used to access a single byte or two bytes simultaneously. To read or write two bytes simul- taneously, the first address accessed must be even. Furth- ermore, when accessing an external memory area, set the bus width selection input pin BYTE to L. (external data bus width to 16 bits) The internal memory area is always treated as 16-bit bus width regardless of BYTE. When performing 16-bit data read or write, if the conditions for simultaneously accessing two bytes are not satisfied, waveform (2) is used to access each byte one by one. However, when prefetching the instruction code, if the address of the instruction code is odd, waveform (1) is used, and only one byte is read in the instruction queue buffer. The signals Ay and BHE in Figure 5 are used to control these cases: 1-byte read from even address, 1-byte read from odd address, 2-byte simultaneous read from even and odd addresses, 1-byte write to even address, 1-byte write to odd address, or 2-byte simultaneous write to even and odd addresses. The Aj signal that is the address bit 0 is L when an even number address is accessed. The BHE signal becomes L when an odd number address is accessed. The bit 2 of processor mode register (address 5E,,) is the wait bit. When this bit is set to 0, the L width of E signal is 2 times as long when accessing an external memory area. However, the L width of E signal is not extended when an internal memory area is accessed. When the wait bit is 1, the L width of E signal is not extended for any access. Waveform (3) is an expansion of the L width of E signal in waveform (1). Waveform (4),(5), and (6) are ex- pansion of each L width of E signal in waveform (2), first half of waveform (2), and the last half of waveform (2) re- spectively. inert cook LLL LPL LLL ALE f | Ai/Dj CA XD KAHKD ) ALE Mm ml 3 E L__J ALE j | Ai/Dj CAM _D MK DD) ALE M mM Ai/Dj (AX DAK D) ALE mM mM av0i "XEXD EX > 6 EF ULL ALE ___J L_J LL psa > A: Address O Data Ai/Dj indicates multiplex I/O pin with address data and data. Access sgethod Access 2-byte Access even Access odd Signat \ Simultaneously address 1-byte address 1-byte Ao - ol rp mye BHE ue ou ape - Fig.5 Relationship between access method and signals Ay and BHE 2466 ae SSRMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER Instruction code read, data read, and data write are de- scribed below. Instruction code read will be described first. The CPU obtains instruction codes from the instruction queue buffer and executes them. The CPU notifies the bus interface unit that it is requesting an instruction code during an instruction code request cycle. If the requested instruc- tion code is not yet stored in the instruction queue buffer, the bus interface unit halts the CPU until it can store more instructions than requested in the instruction queue buffer. Even if there is no instruction code request from the CPU, the bus interface unit reads instruction codes from memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruc- tion code is stored and the bus is idle on the next cycle. This is referred to as instruction pre-fetching. Normally, when reading an instruction code from memory, if the accessed address is even the next odd address is read together with the instruction code and stored in the instruc- tion queue buffer. However, if the bus width switching pin BYTE is H, exter- nal data bus width is 8 bits and the address to be read is in external memory area is odd, only one byte is read and stored in the instruction queue buffer. Therefore, waveform (1) of (3) in Figure 5 is used for instruction code read. Data read and write are described below. The CPU notifies the bus interface unit when performing data read or write. At this time, the bus interface unit halts the CPU if the bus interface unit is already using the bus or if there is a request with higher priority. When data read or write is enabled, the bus interface unit uses one of the waveforms from (1) to (6) in Figure 5 to perform the opera- tion. During data read, the CPU waits until the entire data is stored in the data buffer. The bus interface unit sends the address received from the CPU to the address bus. Then it reads the memory when the E signal is L and stores the result in the data buffer. During data write, the CPU writes the data in the data buf- fer and the bus interface unit writes it to memory. There- fore, the CPU can proceed to the next step without waiting for write to complete. The bus interface unit sends the address received from the CPU to the address bus. Then when the E signal is L, the bus interface unit sends the data in the data buffer to the data bus and writes it to memory. MITSUBISHI ELECTRIC 2467MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP ,M37730S2BSP 16-BIT CMOS MICROCOMPUTER INTERRUPTS Table 1 shows the interrupt types and the corresponding interrupt vector addresses. Reset is also treated as a type of interrupt and is. discussed in this section, too. DBC is an interrupt used during debugging. The priority of interrupts when multiple interrupts are caused simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in Figure 7. The hardware priority is fixed the following: reset > DBC > watchdog timer > other interrupts Interrupts other than reset, DBC, watchdog timer, zero di- vide, and BRK instruction all have interrupt control regis- Table 1. Interrupt types and the interrupt vector ters. Table 2 shows the addresses of the interrupt control addresses registers and Figure 6 shows the bit configuration of the in- Interrupts Vector addresses terrupt control register. UARTO transmit QOFFDC:5 OOFFOD:5 Use the SEB and CLB instructions when setting each inter- UARTO receive QOFFDE,;, OOFFDF 15 rupt control register. Timer BO OOFFE4,, OOFFESi The interrupt request bit is automatically cleared by the Timer A4 OOFFEG,, OOFFE7i hardware during reset or when processing an interrupt. Timer A3 QOFFE8;, OOFFE9: Also, interrupt request bits other than DBC and watchdog Timer AZ QOFFEA OOFFEB:. timer can be cleared by software. Timer Aq QOFFEC1g _ OOFFEDe INT, to INTp are external interrupts and whether to cause Timer AO OOFFEE: _OOFFEF se . . INT. external interrupt OOFFFO46 OOFFF 14, an interrupt at the input level (level sense) or at the edge - . INT, external interrupt OOFFF2i OOFFF3,. (edge sense) can be selected with the level sense/edge INT, external interrupt OOFFF4,, OOFFFS;5 sense selection bit. Furthermore, the polarity of the inter- Watchdog timer OOFFF6,, OOFFF7 1, rupt input can be selected with polarity selection bit. DBC (unusable) OOFFF8,, OOFFF9,, Timer and UART interrupts are described in the respective Break instruction OOFFFA,, OOFFFB, section. Zero divide OOFFFC,, OOFFFDi5 fleset OOFFFE 16 OOFFFF 16 i . : 432710 Interrupt priority Interrupt request bit 0 | No interrupt 1. Interrupt Interrupt control register configuration for UARTO, timer A4 to timer AO, and timer BO 765 43219 an ann Interrupt priority Interrupt request bit 0 : No interrupt 1: Interrupt Polarity selection bit 0 : Set interrupt request bit at H" level for level sense and when changing from "H" to "L levei for edge sense. 1 : Set interrupt request bit at "L jevel for level sense and when changing from L to H level for edge sense. Level sense/edge sense selection bit 0 : Edge sense 1 : Level sense Interrupt control register configuration for INT,~INTo. Fig. 6 Interrupt control register configuration 2468 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BiIT CMOS MICROCOMPUTER Table 2. Addresses of interrupt control registers T Interrupt control registers | Addresses | UARTO transmit interrupt control register 00007115 UARTO receive interrupt control register _ To 00007216 Timer AO interrupt control register 00007516 Timer A1 interrupt control register 00007646 Timer A2 interrupt control register . 000077 16 Timer A3 interrupt control register , 0000781, | Timer Ad interrupt control register \ 0000791 Timer BO interrupt control register _ 00007Ai5 | INTo interrupt control register 00007D,_ | INT, interrupt control register _ 00007E 16 INT> interrupt control register 00007F is Interrupts caused by a BRK instruction and when dividing by zero are software interrupts and are not included in this list. Other interrupts previously mentioned are UART, Timer, INT interrupts. The priority of these interrupts can be changed by changing the priority level in the corresponding interrupt control register by software. Figure 8 shows a diagram of the interrupt priority resolution circuit. When an interrupt is caused, the each interrupt de- vice compares its own priority with the priority from above and if its own priority is higher, then it sends the priority be- low and requests the interrupt. If the priorities are the same, the one above has priority. This comparison is repeated to select the interrupt with the highest priority among the interrupts that are being re- quested. Finally the selected interrupt is compared with the processor interrupt priority level (IPL) contained in the pro- cessor status register (PS) and the request is accepted if it is higher than IPL and the interrupt disable flag | is O". The request is not accepted if flag | is "1". The reset, DBC, and watchdog timer interrupts are not affected by the interrupt disable flag I. When an interrupt is accepted, the contents of the proces- sor status register (PS) is saved to the stack and the inter- rupt disable flag | is set to 1. Furthermore, the interrupt request bit of the accepted inter- rupt is cleared to 0 and the processor interrupt priority level (IPL) in the processor status register (PS) is replaced by the priority level of the accepted interrupt. Therefore, multi-level priority interrupts are possible by re- setting the interrupt disable flag | to 0 and enable further interrupts. For reset, DBC, watchdog timer, zero divide, and BRK in- struction interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 3. Priority resolution is performed by latching the interrupt re- guest bit and interrupt priority level so that they do not change. They are sampied at the first half and latched at the last half of the operation code fetch cycle. Because priority resolution takes some time, no sampling puise is generated for a certain interval even if it is the next operation code fetch cycle. Priority is determined by hardware 3 2 q FT ooo toe ee 4 UART. Timer, INT interrupts Priority can be changed with software inside 4 Fig. 7 Interrupt priority Level 0 UARTO transmit UARTO receive interrupt request Fig. 8 Interrupt priority resolution MITSUBISHI ELECTRIC 2469MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER As shown in Figure 9, there are three different interrupt priority resolution time from which one is selected by soft- ware. After the selected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been completed. The time is selected with bits 4 and 5 of the processor mode register (address 5E,,) shown in Figure 10. Table 4 shows the relationship between these bits and the number of cycles. After a reset, the processor mode register is in- itialized to 00,," and therefore, the longest time is selected. However, the shortest time should be selected by software. Table 3. Value set in processor interrupt level (IPL) during an interrupt Interrupt types Setting value Reset Q DBC 7 Watchdog timer 7 Zero divide Not change value of IPL. BRK instruction Not change value of IPL. Table 4. Relationship between priority level resolution time selection bit and number of cycles Priority tevel resolution time selection bit Number of cycles Bit Bit 4 0 Q 7 cycles of 0 1 4 cycles of 1 0 2 cycles of : internal clock internal clock Operation code fetch cycle Sampling pulse Priority resolution time Select from 0 to 2 with bits 4 and 5 of the processor mode register Fig. 9 Interrupt priority resolution time 7.6 65 4 3 2? | x 0 1 Processor mode register(5E1,) L Processor mode bits 0 : Microprocessor mode 1: Evaluation chip mode Must be 1 (It is set to 1 after a reset) Wait bit 0 : Wait 1: No wait Software reset bit The processor is reset when this bit is set to 1. Priority resolution time selection bit 0 0 : Select 0 in Figure 9 01 : Select 1 in Figure 9 1 0 : Setect 2 in Figure 9 Test mode bit Must be 0 Fig. 10 Processor mode register configuration 2-470 oesMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER TIMER There are six 16-bit timers. They are divided by type into timer A(5) and timer B(1). The timer I/O pins are shared with I/O pins for port P5 and P6. To use these pins as timer input pins, the data direction register bit corresponding to the pin must be cleared to 0 to specify input mode. TIMER A Figure 11 shows a block diagram of timer A. Timer A has four modes; timer mode, event counter mode. one-shot pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i=0 to 4). Each of these modes is de- scribed below. (1) Timer mode (00) Figure 12 shows the bit configuration of the timer Ai mode register during timer mode. Bits 0, 1, and 5 of the timer Ai mode register must always be 0 in timer mode. Bit 3 is ignored if bit 4 is 0. Bits 6 and 7 are used to select the timer counter source. The counting of the selected clock starts when the count start flag is 1 and stops when it is 0. Figure 13 shows the bit configuration of the count start flag. The counter is decremented, an interrupt is caused and the: interrupt request bit in the timer Ai interrupt control register is set when the contents becomes 0000,,. At the same time, the contents of the reload register is transferred to the counter and count is continued. fo he {32 i fe12 Data bus (odd) f Data bus (even) J Clock source selection . + Timer * One-shot C S. + Pulse width modulation =< Polarity Event counter ~ selection - External trigger (Lower 8 bits) 3 J Higher 8 bits Reload register(16) _| " | ib Lb Timer gate function; \ }_< 5 BD . ~~ | : TAtiy : Count start flag | Always decremented e044 40.5 Addresses TimerAd 4. 4646 Counter( 16) | | Up/Down / | timeras tr 4Bye lexcept in event count mode! Xu Timera2 43.5 4Asg Down count = o i TimerA3 9.5 Cre | TimerAd $F. 4Ere \ | Up-down flag we) 3 J 44., ee lt : Pulse output | : +<f oe Toggle frp-flop ee TAig ge =O~4 Fig. 11 Block diagram of timer A I 2747} ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER When bit 2 of the timer Ai mode register is 1, the output is generated from TAiguy pin. The output is toggled each time the contents of the counter reaches to 0000,,. When the contents of the count start flag is 0, L is output from TAiour pin. When bit 2 is 0, TAigur can be used as a normal port pin. When bit 4 is 0, TAi,, can be used as a normal port pin. When bit 4 is 1, counting is performed only while the in- put signal from the TAiy pin is H or L" as shown in Fi- gure 14. Therefore, this can be used to measure the pulse width of the TAi,, input signal. Whether to count while the input signal is H or while it is L" is determined by bit 3. If bit 3 is 1, counting is performed while the TAi, pin input signal is H and if bit 3 is O, counting is performed while itis L. Note that the duration of H or L on the TAi, pin must be two or more cycles of the timer count source. When data is written to timer Ai register with timer Ai halted, the same data is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The contents of the counter can be read at any time. When the value set in the timer Ai register is n, the timer frequency dividing ratio is 1/(n +1). 0 0 : Always "00" in timer mode Ox 1 Clock source selection bit 00 Oo: 1 Select fes G Always 0 in timer mode Addresses . Timer AO mode register 5646 Timer At mode register 5716 Timer A2 mode register 586 Timer A3 mode register 5916 : Timer A4 mode register 5Aie | 0 | No pulse output (TAigus is normal port pin) 1 < Pulse output No gate function ( TAiy iS normal port pin 0 ! Count only while TAi,, input is L 1. Count only while TAin input is H" : Select fp : Select f., Select f,., Fig. 12 Timer Ai mode register bit configuration during timer mode 2472 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER 7 6 5 4 3 2 1 0 Count start flag Address S Bd | | ] | (Stop at "0", Start at 1") bo | 4016 (_______ Timer A2 count start flag | i ~~~ Timer A3 count start flag i | ! i / Timer AQ count start flag | } Timer A1 count start flag | i i bo Timer A4 count start flag Timer BO count start flag Fig. 13 Count start flag bit configuration Bit 4 Selected clock source fj UU TAly fo LL Timer mode register Bit3 : I Bit 4 Timer mode register Bit3 1 J) QUUUUU Fig. 14 Count waveform when gate function is availableMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP (2) Event counter mode (01) Figure 15 shows the bit configuration of the timer Ai mode register during event counter mode. in event counter mode, the bit 0 of the timer Ai mode register must be 1 and bit 1 and 5 must be 0. The input signal from the TAiy pin is counted when the count start flag shown in Figure 13 is 1 and counting is stopped when it is 0. Count is performed at the fall of the input signal when bit 3 is O and at the rise of the signal when it is 1. In event counter mode, whether to increment or decrement the count can be selected with the up-down flag or the in- put signal from the TAigur pin. When bit 4 of the timer Ai mode register is O", the up- down flag is used to determine whether to increment or de- crement the count (decrement when the flag is O and in- crement when it is 1). Figure 16 shows the bit configura- tion of the up-down flag. When bit 4 of the timer Ai mode register is 1, the input signal from the TAigur pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be 0 if bit 4 is 1" because if bit 2 is 1", TAigur pin becomes an output pin with pulse output. The count is decremented when the input signal from the TAiour pin is L and incremented when it is H. Deter- mine the level of the input signal from the TAigyr pin be- fore valid edge is input to the TAi,y pin. An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set when the counter reaches 0000,, (decrement count) or FFFF,, (increment count). At the same time, the contents of the reload register is transferred to the counter and the count is continued. : When bit 2 is 1 and the counter reaches 0000,, (decrement count) or FFFF,, (increment count), the wave- form reversing polarity is output from TAigur pin. If bit 2 is O, TAiguy pin can be used as a normai port pin. However, if bit 4 is 1 and the TAigyy pin is used as an output pin, the output from the pin changes the count direc- tion. Therefore, bit 4 should be 0 unless the output from the TAiour pin is to be used to select the count direction. 16-BIT CMOS MICROCOMPUTER Addresses Timer AO mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Timer A3 mode register 5916 76543210 [>xPx[o on Loy L____ 0: No pulse output : Pulse output Timer A4 mode register 5Ai6 : Always 01 in event counter mode : Count at the falling edge of input signal : Count at the rising edge of input signai _~ oO 0 : increment or decrement according to up/down flag 1 = Increment or decrement according to TAiguy pin-input signal level 0 : Always 0 in event counter mode *X : Not used in event counter mode Fig. 15 Timer Al mode register bit configuration during event counter mode Address 446 76543210 Up-down flag Timer AO up-down fiag Timer A1 up-down flag Timer A2 up-down flag Timer A3 up-down flag Timer A4 up-down flag Timer A2 two-phase pulse signal processing selection bit 0 | Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signat processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Fig. 16 Up-down flag bit configuration 2-474 oeMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER Data write and data read are performed in the same way as for timer mode. That is, when data is written to timer Ai halted, it is also written to the reload register and the coun- ter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The counter can be read at any time. In event counter mode, whether to increment or decrement the counter can also be determined by supplying two- phase pulse input with phase shifted by 90 to timer A2, AS, or A4. There are two types of two-phase puise processing operations. One uses timers A2 and A3, and the other uses timer A4. In either processing operation, two-phase pulse is input in the same way, that is, pulses out of phase by 90 are input at the TAjour (j=2 to 4) pin and TAjiy pin. When timers A2 and A3 are used, as shown in Figure 17, the count is incremented when a rising edge is input to the TAkiy pin after the level of TAkour (k= 2, 3) pin changes from L" to H, and when the falling edge is inserted, the count is decremented. For timer A4, as shown in Figure 18, when a phase related pulse with a rising edge input to the TA4,n pin is input after the level of TA4oy7 pin changes from L to H, the count is incremented at the respective rising edge and falling edge of the TA4our pin and TA4iy pin. When a phase related pulse with a falling edge input to the TA4our pin is input after the level of TA4iy pin changes from H to L, the count is decremented at the respective rising edge and falling edge of the TA4,, pin and TA4gur pin. When performing this two-phase pulse signal proces- sing, timer Aj mode register bit 0 and bit 4 must be set to 1 and bits 1, 2, 3, and 5 must be 0. Bits 6 and 7 are ignored. Note that bits 5, 6, and 7 of the up-down flag reg- ister (44,5) are the two-phase pulse signal processing selection bit for timer A2, A3, and A4 respectively. Each timer operates in normal event counter mode when the cor- responding bit is 0 and performs two-phase pulse signal processing when it is 1. Count is started by setting the count start flag to 1". Data write and read are performed in the same way as for nor- mal event counter mode. Note that the direction register of the input port must be set to input mode because two- phase pulse signal is input. Also, there can be no pulse output in this mode. Addresses Timer A2 mode register 5816 Timer A3 mode register 5916 76543210 Timer A4 mode register 5Ai | i | [| 0 1 : Always 01 in event counter mode | -- 0 100 : Always "0100" when processing | two-phase pulse signal ee XX | Not used in event counter moce Fig. 19 Timer Aj mode register bit configuration when performing two-phase pulse signal processing in event counter mode wo FPL | LL TAkin J LPL LL Increment- Decrement- Decrement- Decrement- coum count count count (k=2, 3) Increment- Increment- count count Fig. 17 Two-phase pulse processing operation of timer A2 and timer A3 me FLEE LPL Increment-count at each edge Decrement-count at each edge oceans ee ._ Increment-count at each edge Decrement-count at each edge TA4in Fig. 18 Two-phase pulse processing operation of timer A4 ae MESH 2475MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER (3) One-shot pulse mode (10) Figure 20 shows the bit configuration of the timer Ai mode register during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1. The trigger is enabled when the count start flag is "1". The trigger can be generated by software or it can be input from the TAi, pin. Software trigger is selected when bit 4 is OQ and the input signal from the TAiy pin is used as the trigger when it is 1. Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. The trigger is at the fall of the trigger signal when bit 3 is O and at the rise of the trigger signal when it is 1. Software trigger is generated by setting the bit in the one- shot start flag corresponding to each timer. Figure 21 shows the bit configuration of the one-shot start flag. As shown in Figure 22, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7. If the contents of the counter is not 0000;., the TAioguy pin goes H when a trigger signal is received. The count direction is decrement. When the counter reaches 000116, The TAigur pin goes L and count is stopped. The contents of the reload register is transferred to the counter. At the same time, an interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set. This is repe- ated each time a trigger signal is received. The output pulse width is 1 pulse frequency of the selected clock X (counter's value at the time of trigger). If the count start flag is 0, TAigyr goes L. Therefore, the value corresponding to the desired pulse width must be written to timer Ai before setting the timer Ai count start flag. As shown in Figure 23, a trigger signal can be received be- fore the operation for the previous trigger signal is com- pleted. In this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. Except when retriggering while operating, the contents of the reload register is not transferred to the counter by trig- gering. When retriggering, there must be at least one timer count source cycle before a new trigger can be issued. Data write is performed to the same way as for timer mode. When data is written in timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. Undefined data is read when timer Ai is read. Addresses Timer AO mode register 56i6 Timer A1 mode register 5716 Timer A2 mode register S86 Timer A3 mode register 5916 Timer A4 mode register 5Ais PPL | | 10 : Always 10" in one-shot pulse mode | : Always 1 in one-shot pulse mode f Ll og: Software trigger 1 0 : Trigger at the falling edge of TAiny | input 1h: Trigger at the rising edge of Ai ij input \ _- 0 : Always 0 in one-shot pulse mode Clock source selection 00 : Select f, 01 Select tig 10 : Select fea 11 Select f5,2 Fig. 20 Timer Al mode register bit configuration during one-shot pulse mode Address 76543210 4246 One-shot start flag | L_ Timer AO one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Fig. 21 One-shot start flag bit configuration 2476 ae MEMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER Selected clock source fj TAin (in case of the rising edge) TAiour Example when the contents of the reload register is 0003, Fig. 22 Pulse output example when external rising edge is selected Selected clock source fj POLAT TAins (in case of the rising edge} TAigut Example when the contents of the reload register is 0004,, Fig. 23. Example when trigger is re-issued during pulse output MITSUBISHI 2-477 ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER (4) Pulse width modulation mode (11) Figure 24 shows the bit configuration of the timer Ai mode register during pulse width modulation mode. In pulse width modulation mode, bits 0, 1, and 2 must be set to 1. Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modula- tor. 16-bit length pulse width modulator is performed when bit 5 is O and 8-bit length pulse width modulator is per- formed when it is 1. The 16-bit length pulse width mod- ulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAin pin (external trigger). The software trigger mode is selected when bit 4 is 0. Pulse width modulator is started and pulse is output from TAiour when the timer Ai start flag is set to 1. The external trigger mode is selected when bit 4 is 1. Pulse width modulator starts when a trigger signal is input from the TAij, pin when the timer Ai start flag is 1. Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is O" and at the rise when it is 1. When data is written to timer Ai with the pulse width mod- ulator halted, it is written to the reload register and the counter. Then when the time Ai start flag is set to 1 and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 25 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration H" of pulse is i selected clock frequency ~ and the output pulse period is 1 selected clock frequency An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set at each falt of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when the timer Ai mode register bit 5 is 1". The reload register and the counter are both divided into 8- bit halves. The low order 8 bits function as a prescaler and the high X(2'4), order 8 bits function as the 8-bit length pulse width modula- tor. The prescaler counts the clock selected by bits 6 and 7. A pulse is generated when the counter reaches 0000,. as shown in Figure 26. At the same time, the contents of the reload register is transferred to the counter and count is continued. Addresses Timer AO mode register 56.: Timer A1 mode register 575 Timer A2 mode register 5816 76543210 Timer A3 mode register 59: | tee Py) Timer A4 mode register 5Aie Ty | co i 1 1: Always "11" in pulse width modulation | i mode i ! 1: Always "1" in pulse width moduiation fo mode | 1 0 X : Software trigger t 10 : Trigger at the falling of TAi,y input 11: Trigger at the rising of TAi, input : 0 : 16 bit pulse width modulator | | 1: 8 bit pulse width modulator Pe Clock source selection bit 0 0 : Select f, O01 : Select fy, 10 : Select fea 11 : Select fs;> Fig. 24 Timer Al mode register bit configuration during pulse width modulation mode 2478 ae MasMITSUBISHI MICROCOMPUTERS M37730S2AFP ,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER Therefore, if the low order 8-bit of the reload register is n, the period of the generated pulse is 1 selected clock frequency x(n+1). The high order 8-bit function as an 8-bit length pulse width modulator using this pulse as input. The operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. If the high order 8-bit of the reload reg- ister is m, the duration H of pulse is 1 selected clock frequency (P+ 1)*m And the output pulse period is 1 an 8B selected clock frequency X(n $1) x (221). a W/E (278 1 Selected clock eq r-4 bod aod io it source f, a4 te | ! t TAln | | vin case of the > i This trigger 1s not accepted | rising edge: | | VAX Om uC Xin) | TAigur | Example when the contents of the reload register 1s 0003, Fig. 25 16-bit length puise width modulator output pulse example Seiected clock scurce f, TAtia ! I in case of the falling edge : ha Prescaler output when n =2 8-bit length pulse width modulator output when m = W/E (n1) X (28~1) ' Fig. 26 8-bit length pulse width modulator output pulse example ae eS 2-479MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP ,M37730S2BSP 16-BIT CMOS MICROCOMPUTER TIMER B Figure 27 shows a block diagram of timer B. Timer B has three modes; timer mode, event counter made, and pulse period measurement/pulse width measurement mode. The mode is selected with bits 0 and 1 of the timer BO mode register. Each of these modes is described below. (1) Timer mode (00) Figure 28 shows the bit configuration of the timer BO mode register during timer mode. Bits 0, and 1 of the timer BO mode register must always be 0 in timer mode. Bits 6 and 7 are used to select the clock source. The counting of the selected clock starts when the count start flag is 1 and stops when 0. As shown in Figure 13, the timer BO count start flag is at the same address as the timer Ai count start flag. The count is decremented, an interrupt occurs, and the interrupt request bit in the timer BO interrupt control register is set when the contents becomes 0000,,. At the same time, the contents of the reload register is stored in the counter and count is continued. Timer BO does not have a pulse output function or a gate function like timer A. When data is written to timer BO halted, it is written to the reload register and the counter. When data is written to timer BO which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The contents of the counter can be read at any time. Polarity selection Event counter { Data bus(odd) 4 f Data bus(even) 4 Clock source selection | (Lower 8 bits) (Higher 8 bits) * Timer <7 o Pulse period measurement/pulse | Reload register(16) | he 0 \ width measurement fi fea O | | T SZ Addresses {5:2 O Counter(16) | Timer BO Ste 5016 TBO ( }-4 and edge pulse o generator Count start flag 40;6) Counter reset circuit Fig. 27 Timer B block diagram _ MITSUBISHI 2480 ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP ,M37730S2BSP 16-BIT CMOS MICROCOMPUTER (2) Event counter mode (01) Figure 29 shows the bit configuration of the timer BO mode register during event counter mode. In event counter mode, the bit 0 in the timer BO mode register must be 1 and bit 1 must be 0. The input signal from the TBO, pin is counted when the count start flag is "1" and counting is stopped when it is 0. Count is performed at the fall of the input signal when bits 2, and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is 1. When bit 3 is 1" and bit 2 is 0, count is performed at the rise and fall of the input signal. Data write, data read and timer interrupt are performed in the same way as for timer mode. (3) Pulse period measurement/pulse width measurement mode (10) Figure 30 shows the bit configuration of the timer BO mode register during pulse period measurement/pulse width measurement mode. In pulse period measurement/pulse width measurement made, bit 0 must be 0 and bit 1 must be 1. Bits 6 and 7 are used to select the clock source. The selected clock is counted when the count start flag is 1 and counting stops when it is 0. The pulse period measurement mode is selected when bit 3 is 0. In pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the TBO, pin to the next fall or at the rise of the input signal to the next rise and the result is stored in the reload register. In this case, the reload register acts as a buffer register. When bit 2 is 0, the clock is counted from the fall of the input signal to the next fail. When bit 2 is 1, the clock is counted from the rise of the input signal to the next rise. In the case of counting from the fall of the input signal to the next fall, counting is performed as follows. As shown in Figure 31, when the fail of the input signal from TBO. pin is detected, the contents of the counter is transferred to the reload register. Next the counter is cleared and count is started from the next clock. When the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and the count is started. The period from the fall of the in- put signal to the next fail is measured in this way. 76543210 Addresses Timer BO mode register 5By< +-1 0 0 : Always 00 in timer mode Li... XX | Not used in timer mode and may be any _ ~ X | Not used in timer mode Clock source selection bit 00 : Select f, 01 : Select tf, 10 : Select fea 11: Select fe,> Fig. 28 Timer BO mode register bit configuration dur- ing timer mode 7654321 0 Lxxyxpe | Loy Addresses Timer BO mode register 5Bi 0 1 : Always 01 in event counter | mode - 0 0 : Count at the falling edge cf input signal 0 1 : Count at the rising edge ct | input signal | ! 1 0 : Count at the both falling edge and rising edge of input signal i : xX X : Not used in event counter mode Fig. 29 Timer BO mode register bit configuration dur- ing event counter mode 76543210 Addresses Timer BO mode register 5By.5 1 0 : Always 10 in pulse period Lo measurement/pulse width \ measurement mode | 0 0 : Count from the falling edge of | input signal to the next falling one f ! 0 1 : Count from the rising edge ot input signal to the next rising one 1 0 : Count from the falling edge of i input signal to the next rising one an and from the rising edge to he next falling one | | ho Timer BO overtiow flag Clock source selection bit 0 0 : Select f. QO 1 : Select fig 10 Select tea 11 : Select fs4> Fig. 30 Timer BO mode register bit configuration dur- ing pulse period measurement/pulse width measurement mode oe eS 2-481MITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER After the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer BO interrupt control regis- ter is set. However, no interrupt request signal is generated when the contents of the counter is transferred first time to the reload register after the count start flag is set to 1. When bit 3 is 1, the pulse width measurement mode is selected. Pulse width measurement mode is similar to pulse period measurement mode except that the clock is counted from the fall of the TBO. pin input signal to the next rise or from the rise of the input signal to the next fall as shown in Figure 32. When timer BO is read, the contents of the reload register is read. Note that in this mode, the interval between the fall of the TBO. pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer BO overflow flag which is bit 5 of timer BO mode reg- ister is set to 1 when the timer BO counter reaches 0000,,. This flag is cleared by writing to corresponding tim- er BO mode register. This bit is set to 1 at reset. Reload register counter Counter+-0 seve" UU source fj Count start flag | interrupt request signal Fig. 31 next falling one) Pulse period measurement mode operation (example of measuring the Interval between the falling edge to Reload register Counter [| Counter=-0 [] ec OU UU UU UU source f, I td i TBOn I fi 1! f i Count stan flag | Interrupt request signal Fig. 32 Pulse width measurement mode operation 2482 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP 16-BIT CMOS MICROCOMPUTER Pulse output port mode Figure 33 shows a block diagram for pulse output port mode. In the pulse output port mode, two pairs of four-bit pulse output ports are used. Whether using pulse output port or not can be selected by waveform output selection bit (bit 0, bit 1) of waveform output mode register (624. address) shown in Figure 34. When bit 0 of waveform out- put selection bit is set to 1, ports P69, P5g, P5s and P5, are used as pulse output ports (RTP1 selected), and when bit 1 of waveform output selection bit is set to 1, ports P53, P52, P5,, and P59 are used as pulse output ports (RTPO selected). When bits 1 and 0 of waveform output selection bit are set to 1, ports P6>, P5g, PSs, and P,, and ports P53, P52, P5, and P59 are used as pulse output ports (RTP1 and RTPO selected). The ports not used as pulse output ports can be used as normal parallel ports or timer input/output. In the pulse output port mode, set timers A2 and AO to tim- er mode as timers A2 and AO are used. Figure 35 shows the bit configuration of timer AO, A2 mode registers in pulse output port mode. Data can be set in each bit of the pulse output data regis- ter corresponding to four ports selected as pulse output ports. Figure 36 shows the bit configuration of the pulse output data register. The contents of the pulse output data register 1 (low-order four bits of 641. address) correspond- ing to ports P6>, P5s, P5; and P5, is output to the ports each time the counter of timer A2 becomes 0000... The contents of the pulse output data register 0 (low-order four bits of 65, address) corresponding to ports P53, P5,, P5,, and P5, is output to the ports each time the counter of tim- er AQ becomes 0000,.. When 0 is written to a specified bit of the pulse output data register, L level is output to the corresponding pulse output port when the counter of corresponding time: be- comes 0000,., and when 1 is written, H level is output to the pulse output port. Pulse width modulation can be applied to each pulse out- put port. Since pulse width modulation involves the use of timers A3 and A1, activate these timers in pulse width mod- ulation mode. When a certain bit of the pulse output regis- ter is 1", pulse width modulation is output from the pulse output port when the counter of the corresponding timer becomes 0000,.. Pulse width modulation selection bit (Bit 4, 5 of 62,, address} Puise width modulation output by timer A3 o- Pulse output data Pulse width modulation output by timer At : Waveform output control bit (Bit 7 of 62,5 address) register 1 (64, address) (~ Ds 0 ' Q PG) (RTP13) D, D 0 P5, (RTP1,) D, D Q P5, (RTP1,) 5 Ds D Q P54 (RTP1o) > a 8 __J a a 8 8 Dy, D Q P5, (RTPO3) MJ Dio D Q PS, (RTPO,) | V] d, D Q P, (RTPO,) L ) ~ 72 Pee armel Puise output data register 0 (651. address) . Polarity selection bit Timer AO (Bit 3 of 62,_ address) Fig. 33 Block diagram for pulse output port modeMITSUBISHI MICROCOMPUTERS M37730S2AFP,M37730S2BFP M37730S2ASP,M37730S2BSP Ports P69, P5.s, P5; and P5, are applied pulse width mod- ulation by timer A3 by setting the pulse width modulation selection bit by timer A3 (bit 5) of the waveform output mode register to 1. Ports P53, P5o, P5,; and P5, are applied pulse width mod- ulation by timer Ai by setting the pulse width modulation selection bit by timer Ai (bit 4) of the waveform output mode register to 1. The contents of the pulse output data register 0 can be re- versed and output to pulse output ports P53, P52, P5, and P5o by the polarity selection bit (bit 3) of the waveform out- put mode register. When the polarity selection bit is 0, the contents of the pulse output data register 0 is output unchangeably, and when 1, the contents of the pulse out- put data register 0 is reversed and output. When pulse width modulation is applied, likewise the polarity reverse to pulse width modulation can be selected by the polarity selection bit. Figure 37 shows example of waveforms in pulse output port mode. Ports selecting the pulse output port mode can control out- put by the waveform output control bit (bit 7) of the wave- form output mode register (62,, address). When the waveform output control bit is set to 1, a wave- form is output from the port. When this bit is set to O". waveform output from the port is stopped and the port is placed in floating state. This bit can be set to 0 by instructions, by inputting a fall- ing edge to the INT, pin, or reset. Address CDI LE DIT J ein output mode register 62,, Wavetorm output selection bit 0 0 : Parallel port 01 : RTP1 selected 1 0 ! RTPO selected 1 1 . RTP1 and RTPO selected Polarity selection bit 0 : Positive polarity i: 1! Negative polarity ~~ Pulse width modulation selection bit by timer Al : i 0 : Not modulated : 1. Modulated _ Pulse width modulation selection bit by timer A3 0 - Not modulated 1: Modulated Waveform output control bit Q Waveform output inhibited 1} Waveform output enabled Fig. 34 Waveform output mode register bit configura- tion 16-BIT CMOS MICROCOMPUTER Address 765432 10 Timer AQ mode register *) oF oO} x] t] 0] 0 Lies ae mode register 5816 Always 100 in pulse output port mode i; Not used in pulse output port mode | iL Always 00 in pulse output port mode Clock source selection bit 00 Select f. 01 : Select fy, 1 0 : Select fe, 11: Select feo Fig. 35 Timer AO, A2 mode register bit configuration in pulse output port mode Address Pulse output data register 1 6445 Pulse output data bit of port P5, Pulse output data bit of port P5; Pulse output data bit of port P56 Pulse output data bit of port P6> pes soe Address PI , | y | Pulse output data registerO 6545 Lo Pulse output data bit of port PS; Pulse output data bit of port P5. Pulse output data bit of port P5; '______ Pulse output data bit of port P5; Fig. 36 Pulse output data register bit configuration 2484 oe es