CY62136CV30LL-55BVXI - Cypress Semiconductor Corp.

2-Mbit (128K x 16) Static RAM

CY62136CV30 MoBL®

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05199 Rev. *E Revised July 19, 2006

Features

• Very high speed

—55 ns

• Voltage range

— 2.7V – 3.3V

• Pin-compatible with the CY62136V

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— T ypical active current: 7 mA @ f = fMax (55 ns speed)

• Low standby power

• Easy memory expansion with CE and OE featur es

• Automatic power-down when deselected

• CMOS for optimum speed/po we r

• Available in Pb-free and non Pb-free 48-ball VFBGA

package

Functional Description[1]

The CY62136CV30 is high-performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular te lephones. Th e device

also has an automatic power-down feature that significantly

reduces power consumption by 80% when addresses are not

toggling. The device can also be put into standby mode

reducing power consumption by more than 99% when

deselected (CE HIGH). The input/output pins (I/O0 through

I/O15) are placed in a high-impedance state when: deselected

(CE HIGH), outputs are disabled (OE HIGH), both Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

or during a write operation (CE LOW, and WE LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is

written into the location specified on the address pins (A0

through A16). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8 through I/O15) is written into the location

specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified b y the address

pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) i s

LOW , then data from memory will appear on I/O8 to I/O15. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Note:

1. For best practice recommendation s, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

128K x 16

RAM Array I/O0–I/O7

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

I/O8–I/O15

BLE

BHE

A16

ROW DECODER

A10

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CY62136CV30 MoBL®

Document #: 38-05199 Rev. *E Page 2 of 12

Pin Configuration[3, 4]

Product Portfolio

Product

VCC Range (V) Speed

(ns)

Power Dissipation

Operating, ICC (mA)

Standby, ISB2 (µA)f = 1 MHz f = fMax

VCC(min.) VCC(typ.)[2] VCC(max.) Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.

CY62136CV30LL 2.7 3.0 3.3 55 1.5 3 7 15 2 10

70 1.5 3 5.5 12

A11

A10

A3CE

I/O10

I/O8

I/O9

I/O11

I/O13

I/O12

I/O14

I/O15

VSS

I/O0

BHE

BLE

VCC

I/O2

I/O1

I/O3

I/O4

I/O5I/O6

I/O7

A15

A14

A13

A12

NC NC

48-ball VFBGA

A16

DNU

VCC

Notes:

2. Typical values are included for reference only and are not guaranteed or tested . Typical values are measured at VCC = VCC(typ.), TA = 25°C.

3. NC pins are not connected to the die.

4. E3 (DNU) pin have to be left floating or tied to VSS to ensure proper operation.

Top View

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Document #: 38-05199 Rev. *E Page 3 of 12

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential–0.5V to VCC(max) + 0.5V

DC Voltage Applied to Outputs

in High-Z S tate[5]....................................–0.5V to VCC + 0.3V

DC Input Voltage[5] .................... ............–0.5V to VCC + 0.3V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current............... ... ... .............. ... ... ... ........ > 200 mA

Operating Range

Device Range Ambient

Temperature VCC

CY62136CV30 Industrial –40°C to +85°C 2.7V to 3.3V

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY62136CV30-55 CY62136CV30-70

UnitMin. Typ.[2] Max. Min. Typ.[2] Max.

VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.3V 2.2 VCC +

0.3V V

VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V

IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA

IOZ Output Leakage

Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA

ICC VCC Operating Supply

Current f = fMax = 1/tRC VCC = 3.3V

IOUT = 0 mA

CMOS Levels

715 5.5 12 mA

f = 1 MHz 1.5 31.5 3

ISB1 Automatic CE

Power-down Current —

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = fMax (Address and Data Only),

f = 0 (OE, WE, BHE, and BLE)

210 210 µA

ISB2 Automatic CE

Power-down Current —

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = 3.3V

210 210 µA

Capacitance[7]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = VCC(typ.) 6pF

COUT Output Capacitance 8pF

Thermal Resistance[7]

Parameter Description Test Conditions VFBGA Unit

ΘJA Thermal Resistance

(Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch,

2-layer printed circuit board 55 °C/W

ΘJC Thermal Resistance

(Junction to Case) 16 °C/W

Notes:

5. VIL(min.) = –2.0V for pulse duratio ns less than 20 ns.

6. Tested initially and after any design or process changes that may affect these parameters.

7. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.

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Document #: 38-05199 Rev. *E Page 4 of 12

AC Test Loads and Waveforms

Parameters 3.0V Unit

R1 1105 Ω

R2 1550 Ω

RTH 645 Ω

VTH 1.75 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Typ.[2] Max. Unit

VDR VCC for Data Retention 1.5 Vcc(max) V

ICCDR Data Retention Current VCC= 1.5V, CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V 1 6 µA

tCDR[7] Chip Deselect to Data

Retention T ime 0ns

tR[7] Operation Recovery Time tRC ns

Data Retention Waveform

VCC Typ

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

OUTPUT VTH

Equivalent to: THE VENINEQUIVALENT

ALL INPUT PULSES

RTH

Rise TIme: 1 V/ns Fall Time: 1 V/ns

VCC(min)

tCDR

VDR >1.5 V

DATA RETENTION MODE

VCC

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Document #: 38-05199 Rev. *E Page 5 of 12

Switching Characteristics Over the Operating Range[8]

Parameter Description

55 ns 70 ns

UnitMin. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 55 70 ns

tAA Address to Data Valid 55 70 ns

tOHA Data Hold from Address Change 10 10 ns

tACE CE LOW to Data Valid 55 70 ns

tDOE OE LOW to Data Valid 25 35 ns

tLZOE OE LOW to Low-Z[9] 5 5 ns

tHZOE OE HIGH to High-Z[9, 10] 20 25 ns

tLZCE CE LOW to Low-Z[9] 10 10 ns

tHZCE CE HIGH to High-Z[9, 10] 20 25 ns

tPU CE LOW to Power-up 0 0 ns

tPD CE HIGH to Power-down 55 70 ns

tDBE BHE/BLE LOW to Data Valid 25 35 ns

tLZBE BHE/BLE LOW to Low-Z[9] 5 5 ns

tHZBE BHE/BLE HIGH to High-Z[9, 10] 20 25 ns

Write Cycle[11]

tWC Write Cycle Time 55 70 ns

tSCE CE LOW to Write End 45 60 ns

tAW Address Set-up to Write End 45 60 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-up to Write Start 0 0 ns

tPWE WE Pulse Width 40 45 ns

tBW BHE/BLE Pulse Width 50 60 ns

tSD Data Set-up to Write End 25 30 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High-Z[9, 10] 20 25 ns

tLZWE WE HIGH to Low-Z[9] 10 10 ns

Notes:

8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the

specifi e d IOL/IOH and 30 pF loa d c apacitance.

9. At any given temperature and vol t age co nditi on, t HZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any

given device.

10.ItHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.

11.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any

of these signals can terminate a write by goin g INAC TIVE. The data input set-up and hold timing should be r efe renced to the edge o f the sig nal t hat te rminates

the write.

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Document #: 38-05199 Rev. *E Page 6 of 12

Switching Waveforms

Read Cycle No. 1(Address Transition Controlled)[12, 13]

Read Cycle No. 2 (OE Controlled)[13, 14]

Notes:

12.Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.

13.WE is HIGH for read cycle.

14.Address valid prior to or coincident with CE, BHE, BLE transition LOW.

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

50%

DATA VALID

ACE

LZBE

LZCE

HIGH IMPEDANCE

HZOE

HZCE

HZBE

LZOE

DOE

LZOE

tDBE

IMPEDANCE

HIGH

DATA OUT

SUPPLY

CURRENT

BHE/BLE

ADDRESS

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Document #: 38-05199 Rev. *E Page 7 of 12

Write Cycle No. 1 (WE Controlled)[11, 15, 16]

Write Cycle No. 2 (CE Controlled)[11, 15, 16]

Notes:

15.Dat a I/O is high-impedance if OE = VIH

16.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

17.During this period, the I/Os are in output stat e and input signals should not be applied.

Switching Waveforms

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

tHZOE

DATAIN VALID

NOTE17

tBW

DATA I/O

ADDRESS

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

DATAIN VALID

NOTE 17

tBW

tSA

tHZOE

ADDRESS

DATA I/O

BHE/BLE

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Document #: 38-05199 Rev. *E Page 8 of 12

Write Cycle No. 3 (WE Controlled, OE LOW)[16]

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[16]

Switching Waveforms

tHDSD

tHA

DATAIN VALID

tLZWE

tSA

tAW

tHZWE

NOTE 17

tBW

tWC

ADDRESS

DATA I/O

BHE/BLE

tPWE

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATAIN VALID

tBW

NOTE 17

ADDRESS

DATA I/O

BHE/BLE

tPWE

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Document #: 38-05199 Rev. *E Page 9 of 12

Typical DC and AC Parameters

12.0

10.0

6.0

4.0

2.7

8.0

SUPPLY VOLTAGE (V)

3.6

2.0

3.3

12.0

10.0

6.0

4.0

3.0

8.0

ISB (µA)

Standby Current vs. Supply Voltage

SUPPLY VOLTAGE (V)

MoBL

2.0

2.7 3.3

SUPPLY VOLTAGE (V)

Access Time vs. Supply Voltage

TAA (ns)

3.0

2.7 3.3

MoBL

Operating Current vs. Supply Voltage

MoBL

(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)

2.7 3.6

SUPPLY VOLTAGE (V)

TAA (ns)

3.3

MoBL

ISB (µA)

12.0

10.0

6.0

4.0

2.0

2.7 3.6

0.0

8.0

ICC (mA)

SUPPLY VOLTAGE (V)

14.0

3.3

MoBL

(f = 1 MHz)

(f = fMax,

70 ns)

(f = fMax,

55 ns)

12.0

10.0

6.0

4.0

2.0

2.7 3.3

0.0

8.0

ICC (mA)

SUPPLY VOLTAGE (V)

MoBL

(f = 1 MHz)

14.0

3.0

(f = fMax,

70 ns)

(f = fMax,

55 ns)

3.0

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Document #: 38-05199 Rev. *E Page 10 of 12

Truth Table

CE WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X High-Z Deselect/Power-down Standby (ISB)

L X X H H High-Z Output Disabled Active (ICC)

L H L L L Data Out (I/O0–I/O15)Read Active (ICC)

L H L H L High Z (I/O8–I/O15);

Data Out (I/O0–I/O7)Read Active (ICC)

L H L L H Data Out (I/O8–I/O15);

High Z (I/O0–I/O7)Read Active (ICC)

L L X L L Data In (I/O0–I/O15)Write Active (ICC)

L L X H L High Z (I/O8–I/O15);

Data In (I/O0–I/O7)Write Active (ICC)

L L X L H Data in (I/O8–I/O15);

High Z (I/O0–I/O7)Write Active (ICC)

L H H L L High-Z Output Disabled Active (ICC)

L H H H L High-Z Output Disabled Active (ICC)

L H H L H High-Z Output Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

55 CY62136CV30LL-55BVI 51-85150 48-ball Fine Pitch BGA (6 x 8 x 1 mm) Industrial

70 CY62136CV30LL-70BVXI 48-ball Fine Pitch BGA (6 x 8 x 1 mm) Pb-free

Please contact your local Cypress sales representative for availability of these parts

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Document #: 38-05199 Rev. *E Page 11 of 12

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wit hout notice. Cypr ess S em icon duct or Corpo ration assu mes no resp onsib ility for th e u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furthermore , Cypress does no t authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and

company names mentioned in this document may be the trademarks of their respective holders.

Package Diagram

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

48-ball VFBGA (6 x 8 x 1 mm) (51-85150)

51-85150-*D

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Document #: 38-05199 Rev. *E Page 12 of 12

Document History Page

Document Title: CY62136CV30 2-Mbit (128K x 16) Static RAM

Document Number: 38-05199

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 112 379 02/19/02 GAV New Data Sheet (advance information)

*A 114023 04/25/02 JUI Added BV package diagram

Changed Advance Information to Preliminary

*B 117 063 07/12/02 MGN Changed Preliminary to Final

*C 118121 08/26/02 MGN Added new part numbers: CY62136CV with wider voltage (2.7V – 3.6V);

CY62136CV33 narrower voltage range (3.0V – 3.6V)

For TAA = 55 ns, improved tPWE Min from 45 ns to 40 ns

For TAA = 70 ns, improved tPWE Min from 50 ns to 45 ns

For TAA = 70 ns, improved tLZWE Min from 5 ns to 10 ns

*D 118622 10/3/02 MGN Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns)

Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns)

For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns

Changed upper spec. for Supply V oltage to Ground Potential to VCC(max) + 0.5V

Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC

Input Voltage to VCC + 0.3V

*E 486789 SEE ECN VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Removed Part numbers: CY62136CV and CY62136CV33

Updated Ordering Information table

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