Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Li+ Charger Protection IC with Integrated P-MOSFET
• Input Over-Voltage Protection
• Current-Limit Protection
• Battery Over-Voltage Protection
• High Immunity of False Triggering
• High Accuracy Protection Threshold
• A Built-In P-MOSFET
• Available with 3 Versions of Charging Current:
450mA, 550mA, 650mA
• Thermal Shutdown Protection
• Available in TDFN2x2-8 and TSOT-23-6A Packages
• “Lithium-Safe” Criteria
• Lead Free and Green Devices Available
(RoHS Compliant)
Features
Applications
• Cell Phones for Infineon
General Description
Simplified Application Circuit
The APL3208A/B/C provides complete Li+ charger pro-
tection against Input over-voltage, battery over-voltage,
and the charge current limit. When the input OVP or the
battery OVP is over the threshold, the IC removes the
power from the charging system by turning off an internal
switch. When the current via the internal switch surpasses
the current limit threshold, the current will be clamped in
a constant level to provide a constant current for battery
charging usage. All protections also have deglitch time
against false triggering due to voltage spikes or current
transients.
The APL3208A/B/C integrates a P-MOSFET with the body
diode reverse protection to replace the external power
bipolar transistor and Schottky diode for charger function
of the Infineon ULC2 mobile phones. When the CHG_DET
voltage drops below VBAT+20mV, the internal power se-
lect circuit will reverse the body diode’s terminal to pre-
vent a reverse current flowing from the battery back to the
CHG_DET pin.
The APL3208A/B/C provides complete Li+ charger pro-
tections and save the external MOSFET and Schottky di-
ode for the Infineon ULC2 mobile phones. The above
features and small package make the APL3208A/B/C an
ideal part for cell phones applications.
Pin Configuration
R
= Exposed Pad
(Connected to the ground plane for better heat
dissipation)
EP
TDFN2x2-8
(Top View)
EP
ACIN 1
GND 3
ACIN 2
VBAT 4
8 OUT
7 OUT
5 CHG_SW
6 CHG_DET
ACIN CHG_DET
VBAT
GND
APL3208A/B/C
Li+
Battery
CHG_SW
OUT
5V Adapter
or USB VCHG_DET
CHG_SW
4 VBAT
6 ACIN
CHG_DET 25 GND
CHG_SW 3
OUT 1
TSOT-23-6A
(Top View)
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw2
Ordering and Marking Information
Absolute Maximum Ratings (Note 1)
Symbol Parameter Rating Unit
VACIN ACIN Input Voltage (ACIN to GND) -0.3 ~ 30 V
VCHG_DET CHG_DET to GND Voltage -0.3 ~ 7 V
VCHG_SW CHG_SW to GND Voltage -0.3 ~ VCHG_DET V
VBAT VBAT to GND Voltage -0.3 ~ 7 V
VOUT OUT to GND Voltage -0.3 ~ 7 V
IOUT OUT Output Current 1.5 A
TJ Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2) TDFN2x2-8
TSOT-23-6A
80
235
oC/W
Thermal Characteristics
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN2x2-8 is soldered directly on the PCB.
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
APL3208A
APL3208B
APL3208C Handling Code
Temperature Range
Package Code
X - Date Code
Assembly Material
APL3208A QB: L08A
X
X - Date CodeAPL3208B QB: L08B
X
X - Date CodeAPL3208C QB: L08C
X
Package Code
QB : TDFN2x2-8 CT : TSOT-23-6A
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
X - Date CodeAPL3208A CT: L8AX
X - Date CodeAPL3208B CT: L8BX
X - Date CodeAPL3208C CT: L8CX
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw3
Symbol
Parameter Range Unit
VACIN ACIN Input Voltage 4.5 ~ 5.5 V
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
APL3208A/B/C
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
ACIN INPUT CURRENT AND POWER-ON-RESET (POR)
IACIN ACIN Supply Current IOUT=0A, ICHG_DET=0A - 250 350 µA
VACIN ACIN POR Threshold VACIN rising 2.4 - 2.8 V
ACIN POR Hysteresis 200 250 300 mV
TB(ACIN) ACIN Power-On Blanking Time - 8 - ms
INTERNAL SWITCH ON RESISTANCE
CHG_DET Discharge On
Resistance - 500 - Ω
INPUT OVER-VOLTAGE PROTECTION (OVP)
VOVP Input OVP Threshold VACIN rising 6 6.17
6.35
V
Input OVP Hysteresis 200 300 400 mV
Input OVP Propagation Delay - - 1 µs
TON(OVP) Input OVP Recovery Time - 8 - ms
CURRENT-LIMIT PROTECTION
APL3208A, TA=25°C 400 450 500
APL3208B, TA=25°C 500 550 600
ILIM Current Limit Threshold
APL3208C, TA=25°C 600 650 700
mA
BATTERY OVER-VOLTAGE PROTECTION
VBOVP Battery OVP Threshold VBAT rising 4.32
4.35
4.38
V
Battery OVP Hysteresis 220 270 320 mV
IVBAT VBAT Pin Leakage Current VBAT = 4.4V - - 20 nA
TB(BOVP) Battery OVP Blanking Time - 176 - µs
INTERNAL P-MOSFET (CHG_DET, OUT AND CHG_SW PINS)
VCHG_DET from low to high, P-MOSFET is
controlled by CHG_SW - 120 -
VCHG_DET-VBAT Lockout Threshold VCHG_DET from high to low, P-MOSFET is off
- 20 - mV
OUT Input Current VCHG_DET=0V, VOUT=4.2V, CHG_SW =GND - - 1 µA
CHG_SW Leakage Current VACIN=VCHG_DET= VOUT=5V, VCHG_SW=0V - 7.5 13 µA
OUT Leakage Current VACIN=VCHG_DET= VCHG_SW =5V, VOUT=0V - - 1 µA
Electrical Characteristics
Recommended Operating Conditions (Note 3)
Note 3: Refer to the typical application circuit
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw4
APL3208A/B/C
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
INTERNAL P-MOSFET (CHG_DET, OUT AND CHG_SW PINS) (CONT.)
P-MOSFET Input Capacitance - 200
- pF
CHG_SW Input Resistance - 15 - Ω
OVER-TEMPERATURE PROTECTION (OTP)
TOTP Over-Temperature Threshold TJ rising - 160
- °C
Over-Temperature Hysteresis - 40 - °C
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at
TA=25oC.
Electrical Characteristics (Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw5
Operating Waveforms
The test condition is VACIN=5V, VBAT=3.8V, TA= 25oC unless otherwise specified.
Normal Power OnOVP at Power On
1
2,3
4
VACIN
VOUT
IOUT
VCHG_DET
CH1: VACIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
TIME: 2ms/Div
CACIN =1µF, COUT =1µF, VCHG_SW = VCHG_DET
CH4: IOUT, 0.2A/Div, DC
CH3: VCHG_DET, 2V/Div, DC
CH1: VACIN, 10V/Div, DC
CH2: VCHG_DET, 1V/Div, DC
CH3: VOUT, 2V/Div, DC
TIME: 2ms/Div
CACIN =1µF, COUT =1µF
1
2
3
VOUT
VACIN
VCHG_DET
Input Over-Voltage Protection Recovery from Input OVP
VCHG_DET
VACIN
1
2
VOUT
3
CH1: VACIN, 5V/Div, AC
CH2: VCHG_DET, 2V/Div, DC
TIME:20µs/Div
CACIN =1µF, COUT =1µF
VACIN =5V to 12V, VCHG_SW = 0V, No Load
VACIN
1VCHG_DET
2
CH1: VACIN, 5V/Div, AC
CH2: VCHG_DET, 2V/Div, DC
TIME: 2ms/Div
CACIN =1µF, COUT =1µF
CH3: VOUT, 2V/Div, DC
VACIN= 12V to 5V, VCHG_SW = VCHG_DET
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw6
Operating Waveforms (Cont.)
The test condition is VACIN=5V, VBAT=3.8V, TA= 25oC unless otherwise specified.
Battery Over-Voltage Protection Battery Over-Voltage Protection
VCHG_DET
VBAT
1
2
1
2
VBAT
VCHG_DET
CH1: VBAT, 2V/Div, DC
CH2: VCHG_DET, 2V/Div, DC
TIME: 200µs/Div
VBAT = 3.6V to 4.4V
CACIN=1µF, COUT =1µF
CH1: VBAT, 2V/Div, DC
CH2: VCHG_DET, 2V/Div, DC
TIME: 50ms/Div
CACIN =1µF, COUT =1µF
VBAT = 3.6V to 4.4V to 3.6V
Pin Description
PIN
NO.
TDFN2x2-8
TSOT-23-6A
NAME FUNCTION
1, 2 6 ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF
(minimum) ceramic capacitor.
3 5 GND Ground Terminal.
4 4 VBAT Battery Voltage Sense Input. Connect this pin to pack positive terminal through a
resistor.
5 3 CHG_SW
Internal P-MOSFET Gate Input.
6 2 CHG_DET
Output Pin. This pin provides supply voltage to the Infineon ULC2 input. Bypass to GND
with a 1µF (minimum) ceramic capacitor.
7, 8 1 OUT Output Pins. These pins provide supply source current in series with a resistor to battery.
Exposed
Pad - EP Exposed Thermal Pad. Must be electrically connected to the GND pin.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw7
Typical Application Circuit
Designation
Description
CACIN 1µF, 50V, X7R, 0805
Murata GRM21BR71H105K
C1 1µF, 10V, X7R, 0805
Murata GRM21BR71A105K
Murata website: www.murata.com
Block Diagram
Gate Driver and
Control Logic
POR
ACIN
VBAT
OUT
Charge
Pump
0.5V
ACIN
OVP
CHG_DET
CHG_SW
GND
Thermal
Shutdown
1V
VBAT
OVP
ACIN CHG_DET
VBAT
GND
APL3208A/B/C
Li+
Battery
CHG_SW
OUT
5V Adapter or USB
C1
1µF
CACIN
1µF
RBAT
200kΩ
Infineon
ULC2
CHG_SW
VBAT
CHG_DET
R1
2.2kΩ
R2
20~100kΩ
C2
33nF
1, 2
3
6
5
7, 8
4
(Optional)
Figure 1. Infineon ULC2 Application Circuit
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw8
Typical Application Circuit (Cont.)
ACIN CHG_DET
VBAT
GND
APL3208
Li+
Battery
CHG_SW
OUT
1, 2
34
5
6
7, 8
CACIN
1µFCOUT
1µF
RBAT
200kΩ
PMIC
VBAT
CHG_SW
CHG_DET
(Optional)
Designation
Description
CACIN 1µF, 50V, X7R, 0805
Murata GRM21BR71H105K
COUT 1µF, 10V, X7R, 0805
Murata GRM21BR71A105K
Murata website: www.murata.com
Figure 2. General Application Circuit
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw9
Function Description
ACIN Power-On-Reset (POR)
The APL3208A/B/C has a built-in power-on-reset circuit
to keep the output shutting off until internal circuitry is
operating properly. The POR circuit has hysteresis and a
de-glitch feature so that it will typically ignore undershoot
transients on the input. When the input voltage exceeds
the POR threshold and after 8ms blanking time, the out-
put voltage starts a soft-start to reduce the inrush current.
ACIN Over-Voltage Protection (OVP)
The input voltage is monitored by the internal OVP circuit.
When the input voltage rises above the input OVP
threshold, the internal FET will be turned off within 1ms to
protect the connected system on OUT pin. When the in-
put voltage returns below the input OVP threshold minus
the hysteresis, the FET is turned on again after 8ms re-
covery time. The input OVP circuit has a 200mV hyster-
esis and a recovery time of TON(OVP) to provide noise im-
munity against transient conditions.
Battery Over-Voltage Protection
The APL3208A/B/C monitors the VBAT pin voltage for bat-
tery over-voltage protection. The battery OVP threshold is
internally set to 4.35V. When the VBAT pin voltage ex-
ceeds the battery OVP threshold for a blanking time of TB
(BOVP), the internal power FET is turned off. When the VBAT
voltage returns below the battery OVP threshold minus
the hysteresis, the FET is turned on again. The APL3208A/
B/C has a built-in counter. When the total count of battery
OVP fault reaches 16, the FET is turned off permanently,
requiring a VACIN POR again to restart.
Over-Temperature Protection
When the junction temperature exceeds 160oC, the inter-
nal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
tion temperature cools by 40oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal pro-
tection is designed to protect the IC in the event of over
temperature conditions. For normal operation, the junc-
tion temperature cannot exceed TJ=+125oC.
Internal P-MOSFET
The APL3208A/B/C integrates a P-channel MOSFET with
the body diode reverse protection to replace the external
power bipolar transistor and Schottky diode for the Infineon
ULC2 mobile. The body diode reverse protection pre-
vents a reverse current flowing from the battery back to
the CHG_DET pin. During power-on, when CHG_DET
voltage rises above the VBAT voltage by more than
120mV, the body diode of the P-channel MOSFET is for-
ward biased from OUT to CHG_DET, and P-MOSFET is
controlled by the external CHG_SW voltage. When the
CHG_DET voltage drops below VBAT+20mV, the body di-
ode of the P-channel MOSFET is forward biased from
CHG_DET to OUT and P-channel MOSFET is turned off.
When any of input OVP, battery OVP, is detected,the inter-
nal P-channel MOSFET is also turned off.
Current-Limit Protection
The APL3208A/B/C provides a current-limit protection
function. When the current via the internal switch sur-
passes the current limit threshold, the current will be
clamped to a constant level to provide external battery
charging current.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw10
Function Description (Cont.)
Figure 4. Battery OVP Timing Diagram
VCHG_DET
Count 13
times
VBAT
TB(BOVP)
Total count 16
times, IC is
latched off
P-MOS Gate
Control
VBOVP
TB(BOVP)
VBOVP
VCHG_DET -VOUT = 120mV
TB(BOVP)
Turn Off Internal
P-MOSFET
Controlled
by CHG_SW Controlled by
CHG_SW Turn Off Internal
P-MOSFET
Controlled by
CHG_SW Turn Off
Internal
P-OSFET
Figure 3. OVP Timing Diagram
VPOR
VOVP
VACIN
ACIN OVP TON(OVP)
VCHG_DET
VCHG_DET -VBAT = 120mV
TB(ACIN)
P-MOS Gate
Control
VOUT
Turn Off Internal
P-MOSFET Controlled
by CHG_SW Controlled by
CHG_SW
VCHG_DET -VBAT = 120mV
Turn Off Internal P-MOSFET
CHG_SW is pulled low
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw11
Application Information
RBAT Selection
Connect the VBAT pin to the positive terminal of battery
through a resistor RBAT for battery OVP function. The RBAT
limits the current flowing from VBAT to battery in case of
VBAT pin is shortened to ACIN pin under a failure mode.
The recommended value of RBAT is 200kΩ. In the worse
case of an IC failure, the current flowing from the VBAT
pin to the battery is:
(30V-3V)/ 200kΩ =135µA
where the 30V is the maximum ACIN voltage and the 3V
is the minimum battery voltage. The current is so small
and can be absorbed by the charger system.
Capacitor Selection
The input capacitor is for decoupling and prevents the
input voltage from overshooting to dangerous levels. In
the AC adapter hot plug-in applications or load current
step-down transient, the input voltage has a transient
spike due to the parasitic inductance of the input cable. A
50V, X7R, dielectric ceramic capacitor with a value be-
tween 1µF and 4.7µF placed close to the ACIN pin is
recommended.
The output capacitor of CHG_DET is for CHG_DET volt-
age decoupling. And also can be as the input capacitor of
the charging circuit. At least, a 1µF, 10V, X7R capacitor is
recommended.
Layout Consideration
In some failure modes, a high voltage may be applied to
the device. Make sure the clearance constraint of the PCB
layout must satisfy the design rule for high voltage. The
exposed pad of the TDFN2x2-8 performs the function of
channeling heat away. It is recommended that connect
the exposed pad to a large copper ground plane on the
backside of the circuit board through several thermal vias
to improve heat dissipation. The input and output capaci-
tors should be placed close to the IC. The high current
traces like input trace and output trace must be wide and
short.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw12
Package Information
TDFN2x2-8
Note : 1. Follow from JEDEC MO-229 WCCD-3.
MIN. MAX.
0.80
0.00
0.18 0.30
1.00 1.60
0.05
0.60
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TDFN2x2-8
0.30 0.45
1.00
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.039 0.063
0.024
0.012 0.018
0.70
0.039
0.028
0.002
0.50 BSC 0.020 BSC
S
Y
M
B
O
L
1.90 2.10 0.075 0.083
1.90 2.10 0.075 0.083
D
E
A
b
A1
A3
D2
E2
L
e
Pin 1 Corner
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw13
Package Information
TSOT-23-6A
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
De
e1
b
E1
E
c
SEE VIEW A
A2A1
A
VIEW A
L
0.25
SEATING PLANE
GAUGE PLANE
0.020
0.008
0.004
0.024
0.035
0.039
MAX.
0.30L
00°
E
e
e1
E1
D
c
b
0.08
0.30
0.012
0.60
8° 0° 8°
0.95 BSC
1.90 BSC
0.50
0.20
0.075 BSC
0.037 BSC
0.012
0.003
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.01
0.70
TSOT-23-6A
MAX.
0.90
0.10
1.00
MIN.
0.000
0.028
INCHES
2.70 3.10 0.106 0.122
2.60 3.00 0.102 0.118
1.40 1.80 0.055 0.071
0.70 0.028
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw14
Carrier Tape & Reel Dimensions
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN2x2-8
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.4 3.35 MIN
3.35 MIN
1.30±0.20
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TSOT-23-6A
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
H
T1
A
d
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
Devices Per Unit
Package Type Unit Quantity
TDFN2x2-8 Tape & Reel 3000
TSOT-23-6A Tape & Reel 3000
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw15
Taping Direction Information
USER DIRECTION OF FEED
TDFN2x2-8
TSOT-23-6A
AAAX AAAX AAAX AAAX AAAX AAAX AAAX
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw16
Classification Profile
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
APL3208A/B/C
www.anpec.com.tw17
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Reliability Test Program
Classification Reflow Profiles (Cont.)
