UTS54ACS169/UTS54ACTS 169 Radiation-Hardened 4-Bit Up-Down Binary Counters FEATURES Fully synchronous operation for counting and programming * Internal look-ahead for fast counting Carry output for n-bit cascading Fully independent clock circuit 1.2u radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UTS4ACS 169 and the UTS4ACTS 169 are synchronous 4- bit binary counters that feature an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simulta- neously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. Synchronous operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters, The clock input triggers the four flip-flops on the rising (positive-going) edge of the clock. The counters are fully programmable (i.c., the outputs may each be preset high or low). The load input circuitry allows loading with the carry-enable output of cascaded counters. Loading is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascaded counters for n-bit synchronous application without additional gating. In- strumental in accomplishing this function are two count-enable inputs and acarry output. Assert both count enable inputs (ENP and ENT) to count. The direction of the count is determined by the level of the U/D input. When U/D is high, the counter counts up; when low, it counts down. Input ENT is fed forward to enable the carry output. The ripple carry output RCOenables a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. The low- level overflow carry pulse can be used to enable successive cas- caded stages. PINOUTS 16-Pin DIP Top View wD (1 16 |] Yoo ceux (CJ2 45[_] RCO aCls 14[_] aC js 13[C_] Qa cls 121] Qc oe 11] Qn ENP (~]7 10{_] ENT Vss[_]8 9[_] LOAD 16-Lead Flatpack Top View ud 1 Vpp CLK 2 RCO A 3 % B 4 Qa c 5 Q D 6 Qp ENP 7 ENT Vss 8 TOAD Transitions at ENP or ENT are allowed regardless of the level of the clock input. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, U/D) that modify the op- erating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The devices are characterized over full military temperature range of -55C to +125C. Hi Rad-Hard MSI LogicUTS4ACS 169/UTS4ACTS 169 LOGIC SYMBOL FUNCTION TABLE (9) CTRDIV 16 OUTPUT TOAD M1 (LOAD) M2 (COUNT) Count Up ud Os M3 (UP) Count Down M44 (DOWN) (18) Ent CONS, 35CT=15 RCO enp NIgg 4,5CT=0 cuk 2}, 235,607 SS 2,3,5,6- _1 Cc A a 1,70 (1) an & 8 (2) p Og Cc (5) (12) (6) 4) an db_ (8) Qp Note: 1. This symbols is in acoordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM CLK up 4 Loan ) ENT Rad-Hard MSI Logic 112UT54ACS 169/UTS54ACTS 169 RADIATION HARDNESS SPECIFICATIONS ! PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU & SEL Threshold ? 80 MeV-cm?/mg Neutron Fluence 1.0E14 n/em2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage -0.3 to 7.0 v Vio Voltage any pin -.3 t0 Vpp +-3 Vv Tstc Storage Temperature range 65 to +150 c Ty Maximum junction temperature +175 C TLs Lead temperature (soldering 5 seconds) +300 c Ojc Thermal resistance junction to case 20 C/W |, DC input current +10 mA Pp Maximum power dissipation 1 WwW Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage 4.5 to 5.5 Vv VIN Input voltage any pin 0 to Vpp Vv Te Temperature range -55 to + 125 C 113 Rad-Hard MSI LogicDC ELECTRICAL CHARACTERISTICS (Vpp = 5.0V 10%; Vsg = OV , -55C < Te < +125C) UTS4ACS 169/UTS4ACTS 169 SYMBOL PARAMETER CONDITION MIN MAX UNIT Vin Low-level input voltage ! ow ee input voltage 08 y ACS 3Vpp Vin High-level input voltage ! ACTS SVpp v ACS 7Vpp lin Input leakage current ACTS/ACS Vin = Vpp or Vsg -1 1 HA VoL Low-level output voltage ? ACTS 8 lo_ = 8.0mA 0.40 v ACS Igy, = 100A 0.25 Von High-level output voltage 3 ACTS lou = -8.0mA TVpp Vv ACS Ioy = -100pA Vpp- 0.25 Tos Short-circuit output current 24 ACTS/ACS Vo = Vpp and Vss -200 200 mA Protal Power dissipation 8? C_ = SOpF 2.3 mW/MHz Ippo Quiescent Supply Current Vpp = 5.5V 10 HA Cin Input capacitance > f = 1MHz @ 0V 15 pF Cour Output capacitance 5 f= IMHz @ 0V 15 pF Notes: 1.Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: Vij = Vyyq(min) + 20%, - 0%; Vy = Vy_(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to Vy,,(min) and Vj, (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-M-38510, for current density < 5.0E5 amps/cm?, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second, 5. Capacitance measured for initial qualification and when design changes may affect the value. Cap at frequency of IMHz and a signal amplitude of S0mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose < 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. the desi inal and Vsg Rad-Hard MSI Logic 114UT54ACS 169/UTS4ACTS 169 AC ELECTRICAL CHARACTERISTICS ? (Vpp = 5.0V 10%; Vgg = OV |, -55C < Te < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tpLH CLK to RCO 1 23 ns tpyL CLK to RCO 1 28 ns tpLy CLK to any Q 1 24 ns tpaL CLK to any Q 1 24 ns tpLH ENT to RCO 1 15 ns tpHL ENT tw RCO 1 16 ns tpt U/D to RCO 1 16 ns tpHL U/D to RCO 1 16 ns fax Maximum clock frequency 71 MHz tsu Setup time before CLK T 9 ns A, B,C,D LOAD ENP, ENT up ti Data hold time after CLK T 2 ns All synchronous inputs tw Minimum pulse width 7 ns CLK high CLK low Notes: 1, Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose < 1E6 rads(Si). 115 Rad-Hard MSI Logic