74HC/HCT164 MSI 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER FEATURES TYPICAL Gated serial data inputs SYMBOL PARAMETER CONDITIONS UNIT Asynchronous master reset HC | HCT @ Output capability: standard . Propagation delay @ lec category: MSI tPHL/ CP ie Q, 12 14 ns 'PLH MR to O,, CL = 15 pF 11 | 16 | ns GENERAL DESCRIPTION Veco =5V The 74HC/HCT164 are high-speed fmax maximum clock frequency 78 61 MHz Si-gate CMOS devices and are pin . : compatible with low power Schottky C1 input capacitance 3.5 3.5 pF TTL (LSTTL). They are specified in wo . q power dissipation compliance with JEDEC standard no. 7A. Cpp capacitance per package notes 1 and 2 40 40 pF The 74HC/HCT 164 are 8-bit edge- triggered shift registers with serial data GND = 0 V; Tamb = 25 C; ty = ty = 6 ns entry and an output from each of the Notes eight stages. 1 : : : Fecinati Pr in uW): Data is entered serially through one of . Cpp is used to determine the dynamic power dissipation (Pp in hW) two inputs (Dg or Dg); either input PD =Cpp x Vcc? x fit = (CL * Vc? x fo) where: can be used as an active HIGH enable for fj = input frequency in MHz CL = output load capacitance in pF data entry through the other input. fo = output frequency in MHz Vec = supply voltage in V Both inputs must be connected together Zz (Cy x Voc? x fo) = sum of outputs or an unused input must be tied HIGH. 2. For HC the condition is Vj] = GND to Vcc Data shifts one place to the right on For HCT the condition is Vj = GND to Voc 1.5 V each LOW-to-HIGH transition of the clock (CP) input and enters into Qo, which is the logical AND of the two data PACKAGE OUTLINES inputs (Dga, Dg) that existed one set-up 14-lead DIL; plastic (SOT27) time prior to the rising clock edge. 14-1ead mini pack: plastic ($014; SOT108A) A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1,2 Dga, Dsp data inputs Ton oy 13 Qo to Q7 outputs 7 GND ground (0 V} 8 cP clock input (LOW-to-HIGH, edge-triggered} 9 MR master reset input {active LOW) 14 Vec positive supply voltage Pa v pal vec a 3 Qo ES [12] Og ; a, - : a,fe] 164 [alas Og Fs : a,/~10 o, [5] [10] O4 8 cp agh11 8 Q3 [5] [9 | ian ag 12 1 ono [7] ray ce 9olma =o Fs . 7293344 7293342 13 7293343 Fig. 1 Pin configuration. Fig. 2. Logic symbol. Fig. 3 |EC logic symbol. December 1990 351 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.74HC/HCT 164 MSI APPLICATIONS Serial data transfer 1 [Osa [~ ZY Deb B-BIT SERIAL-IN #PARALLEL- OUT 8 cP SHIFT REGISTER 9 [MR Og |G, faz Jag {oy jog lag Ja, 7293344 3 |4 [5 fa |i [tt [a2 413 Fig. 4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES -lelp.lp Oy a | H= HIGH voltage level sa sb | Qo 1 7 h = HIGH voltage level one set-up time prior to the LOW-to-HIGH ret len u [xP Pe Te ee] igre | = LOW voltage level one set-up time prior to the LOW-to-HIGH nm ' , t 90 _ a6 clock transition shift H t h | L 40 _ 96 q = lower case letters indicate the state of the referenced input nm t h h H 40 _ q6 one set-up time prior to the LOW-to-HIGH clock transition 90 96] + = LOW-to-HIGH clock transition Dsa o a D Qa oO Q BO a D a D Q o06G B Qa Dep cP cp cP cP cp POlce royce race FFI FF2 FFS FRA FFS FFG FFT FFB Ro Ro Ap Ro Rp Rp Fo Ro cP fe bd 4 g + + g MR -f>o o o 2 3 os os 6 72933468 Fig. 5 Logic diagram. 352 January 1986 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.8-bit serial-in/parallel-out shift register 74HC/HCT 164 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: MSI AC CHARACTERISTICS FOR 74HC GND =OV;t, =t =6ns;C, = 50 pF Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40to+85 | 40to +125 Vv min. | typ. | max. | min. | max, | min. ; max. . 41 | 170 215 255 2.0 tpHL/ propagation deiay 15 | 34 43 51 as 45 Fig. 6 tPLH CP to On 12 | 29 37 43 6.0 . 39 | 140 175 210 2.0 PHL propagation delay 14 | 28 35 42 | ns 4.5 | Fig.7 ME to Qn 11 | 24 30 36 6.0 tral / 19 | 75 95 110 2.0 ab output transition time 7 15 19 22 ns 4.5 Fig. 6 TLH 6 | 13 16 19 6.0 . 80 14 100 120 2.0 clock pulse width . w= |migercow FB 8) | Rm Lge | Ree 60 17 75 90 2.0 master reset pulse . wo | am tom a . 60 vi 75 90 2.0 removal time . tom | te cr mle fy f ite | dm | as | Fer set-up time 60 | 8 75 90 2.0 : 12 13 15 18 ns 45 | Fig 8 su Dear Deb to CP 10 | 2 13 15 6.0 . 4 -6 4 4 2.0 hold time . t 4 2 4 4 ns 4.5 Fig. 8 h Dg: Dsp to CP 4 _2 4 4 6.0 . k pul 6 23 5 4 2.0 f maximum clock pulse 30 | 71 24 20 MHz | 4.5 | Fig 6 max frequency 35 | 85 28 24 6.0 March 1988 35374HC/HCT 164 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: MSI Note to HCT types The value of additional quiescent supply current {Alec) for a unit load of 1 is given in the family specifications. To determine Alec per input, multiply this value by the unit load coefficient shown in the table betow. UNIT LOAD INPUT COEFFICIENT Dsa Dep | 0.25 cP 0.60 MR 0.90 AC CHARACTERISTICS FOR 74HCT GND =O V;t,- = tg =6ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Vee | WAVEFORMS +25 ~40t0 +85 | 40 to +125 Vv min. | typ. | max.| min. | max. | min. | max. tpH/ propagation delay : tPLH CP to Q, 7 36 45 54 ns 4.5 Fig. 6 tPHL propagation delay . MR to Q, 19 | 38 48 57 ns 4.5 Fig. 7 tTHL/ output transition time 7 15 19 22 ns 45 Fig. 6 'TLH clock pulse width Ei tw HIGH or LOW 18 7 23 27 ns 4.5 ig. 6 master reset pulse . tw width: LOW 18 | 10 23 27 ns 4.5 | Fig. 7 removal time 7 . trem MR to CP 16 20 24 ns 4.5 Fig. 7 set-up time Fi tsy Dsa, Deb to CP 12 6 15 18 ns 4.5 ig. 8 hold time _ Fi th Dea, Dsp to CP 4 2 4 4 ns 45 ig. 8 maximum clock pulse Fi fmax frequency 27 55 22 18 MHz | 4.5 ig. 6 354 March 1988 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.8-bit serial-in/parallel-out shift register AC WAVEFORMS 74HC/HCT 164 MSI CP INPUT Q,, OUTPUT 7Z87478.1 Fig. 6 Waveforms showing the clock (CP) to output (Q,,) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. MR INPUT CP INPUT a,, OUTPUT 7ZB7478 Fig. 7 Waveforms showing the master reset {MR} pulse width, the master reset to output (Q,) propagation delays and the master reset to clock (CP) removal time. CP INPUT D, INPUTS Q,, OUTPUT Vig (1) Fig. 8 Waveforms showing the data set-up 7293345 and hold times for Dp inputs. Note to AC waveforms (1) HC: Vxq = 50%; V) = GND to Vec. HCT: VM = 1.3V; V] = GND to 3 V. Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. - (snvar 1986 355