Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 AMC1100 Fully-Differential Isolation Amplifier 1 Features 3 Description * The AMC1100 is a precision isolation amplifier with an output separated from the input circuitry by a silicon dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier is certified to provide galvanic isolation of up to 4250 VPEAK, according to UL1577 and IEC60747-5-2. Used in conjunction with isolated power supplies, this device prevents noise currents on a high common-mode voltage line from entering the local ground and interfering with or damaging sensitive circuitry. 1 * * * * * * * * * * * 250-mV Input Voltage Range Optimized for Shunt Resistors Very Low Nonlinearity: 0.075% max at 5 V Low Offset Error: 1.5 mV max Low Noise: 3.1 mVRMS typ Low High-Side Supply Current: 8 mA max at 5 V Input Bandwidth: 60 kHz min Fixed Gain: 8 (0.5% Accuracy) High Common-Mode Rejection Ratio: 108 dB Low-Side Operation: 3.3 V Certified Galvanic Isolation: - UL1577 and IEC60747-5-2 Approved - Isolation Voltage: 4250 VPEAK - Working Voltage: 1200 VPEAK - Transient Immunity: 2.5 kV/s min Typical 10-Year Life Span at Rated Working Voltage (see Application Report SLLA197) Fully Specified Over the Extended Industrial Temperature Range The AMC1100 input is optimized for direct connection to shunt resistors or other low voltage level signal sources. The excellent performance of the device enables accurate current and voltage measurement in energy-metering applications. The output signal common-mode voltage is automatically adjusted to either the 3-V or 5-V low-side supply. The AMC1100 is fully specified over the extended industrial temperature range of -40C to +105C and is available in the SMD-type, wide-body SOIC-8 (DWV) and gullwing-8 (DUB) packages. Device Information(1) PART NUMBER 2 Applications * AMC1100 Shunt Resistor Based Current Sensing in: - Energy Meters - Green Energy - Power Measurement Applications PACKAGE BODY SIZE (NOM) SOP (8) 9.50 mm x 6.57 mm SOIC (8) 5.85 mm x 7.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Floating Power Supply HV+ AMC1100 Gate Driver 5.0 V VDD1 VDD2 GND1 GND2 3.3 V, or 5.0 V RSHUNT To Load VINP VOUTP VINN VOUTN ADS7263 Gate Driver HV- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 3 3 4 4 4 4 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Regulatory Information.............................................. IEC 60747-5-2 Insulation Characteristics ................. IEC Safety Limiting Values ....................................... IEC 61000-4-5 Ratings ............................................. IEC 60664-1 Ratings................................................. Package Characteristics ........................................ Electrical Characteristics......................................... Typical Characteristics ............................................ Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 13 14 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Applications ................................................ 15 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 23 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History Changes from Original (April 2012) to Revision A Page * Changed format to meet latest data sheet standards ............................................................................................................ 1 * Added ESD Rating table and Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections..................................................................................................................... 1 * Added DWV package to document ........................................................................................................................................ 1 * Deleted Package and Ordering Information section............................................................................................................... 3 2 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 5 Pin Configuration and Functions DUB and DWV Packages SOP-8 and SOIC-8 (Top View) VDD1 1 8 VDD2 VINP 2 7 VOUTP VINN 3 6 VOUTN GND1 4 5 GND2 Pin Descriptions PIN FUNCTION NAME NO. GND1 4 Power High-side analog ground DESCRIPTION GND2 5 Power Low-side analog ground VDD1 1 Power High-side power supply VDD2 8 Power Low-side power supply VINN 3 Analog input Inverting analog input Noninverting analog input VINP 2 Analog input VOUTN 6 Analog output Inverting analog output VOUTP 7 Analog output Noninverting analog output 6 Specifications 6.1 Absolute Maximum Ratings over the operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT -0.5 6 V GND1 - 0.5 VDD1 + 0.5 V Input current to any pin except supply pins 10 mA Maximum junction temperature, TJ Max 150 C 150 C Supply voltage, VDD1 to GND1 or VDD2 to GND2 Analog input voltage at VINP, VINN Storage temperature range, Tstg (1) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2500 Charged device model (CDM), per JEDEC specification JESD22C101 (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 3 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Operating ambient temperature range -40 105 C VDD1 High-side power supply 4.5 5.0 5.5 V VDD2 Low-side power supply 2.7 5.0 5.5 V 6.4 Thermal Information AMC1100 THERMAL METRIC (1) DUB (SOP) DWV (SOIC) 8 PINS 8 PINS RJA Junction-to-ambient thermal resistance 75.1 102.8 RJC(top) Junction-to-case (top) thermal resistance 61.6 49.8 RJB Junction-to-board thermal resistance 39.8 56.6 JT Junction-to-top characterization parameter 27.2 16.0 JB Junction-to-board characterization parameter 39.4 55.2 RJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A (1) UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Regulatory Information VDE AND IEC UL CSA Certified according to IEC 60747-5-2 Recognized under 1577 component recognition program Recognized under CSA component acceptance NO 5 program File number: 40016131 File number: E181974 File number: pending 6.6 IEC 60747-5-2 Insulation Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VIORM VPR VIOTM Input-to-output test voltage Transient overvoltage VISO Insulation voltage per UL RS Insulation resistance PD Pollution degree 4 TEST CONDITIONS VALUE UNIT 1200 VPEAK Qualification test: after input/output safety test subgroup 2/3 VPR = VIORM x 1.2, t = 10 s, partial discharge < 5 pC 1140 VPEAK Qualification test: method A, after environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, partial discharge < 5 pC 1920 VPEAK 100% production test: method B1, VPR = VIORM x 1.875, t = 1 s, partial discharge < 5 pC 2250 VPEAK Qualification test: t = 60 s 4250 VPEAK Qualification test: VTEST = VISO, t = 60 s 4250 VPEAK 100% production test: VTEST = 1.2 x VISO, t = 1 s 5100 VPEAK VIO = 500 V > 109 2 Maximum working insulation voltage Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 6.7 IEC Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. I/O circuitry failure can allow low resistance to either ground or supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, thus potentially leading to secondary system failures. The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. PARAMETER IS Safety input, output, or supply current TC Maximum-case temperature TEST CONDITIONS MIN TYP MAX JA = 246C/W, VIN = 5.5 V, TJ = +150C, TA = +25C UNIT 10 mA +150 C 6.8 IEC 61000-4-5 Ratings PARAMETER VIOSM Surge immunity TEST CONDITIONS VALUE UNIT 6000 V 1.2-s or 50-s voltage surge and 8-s or 20-s current surge 6.9 IEC 60664-1 Ratings PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group II Rated mains voltage 150 VRMS I-IV Rated mains voltage 300 VRMS I-IV Rated mains voltage 400 VRMS I-III Rated mains voltage < 600 VRMS I-III 6.10 Package Characteristics (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 7 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across package surface 7 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112 and VDE 0303 part 1 > 400 V Minimum internal gap (internal clearance) Distance through insulation 0.014 mm RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together to create a two-terminal device, TA < +85C > 1012 Input to output, VIO = 500 V, +85C TA < TA max > 1011 CIO Barrier capacitance input to output VI = 0.5 VPP at 1 MHz 1.2 pF CI Input capacitance to ground VI = 0.5 VPP at 1 MHz 3 pF (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary section. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 5 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com 6.11 Electrical Characteristics All minimum and maximum specifications are at TA = -40C to +105C and are within the specified voltage range, unless otherwise noted. Typical values are at TA = +25C, VDD1 = 5 V, and VDD2 = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Maximum input voltage before clipping VINP - VINN Differential input voltage VINP - VINN 320 mV -250 250 -0.16 VDD1 mV VCM Common-mode operating range VOS Input offset voltage -1.5 0.2 1.5 mV TCVOS Input offset thermal drift -10 1.5 10 V/K CMRR Common-mode rejection ratio CIN Input capacitance to GND1 CIND Differential input capacitance RIN Differential input resistance VIN from 0 V to 5 V at 0 Hz VIN from 0 V to 5 V at 50 kHz VINP or VINN Small-signal bandwidth 60 V 108 dB 95 dB 3 pF 3.6 pF 28 k 100 kHz OUTPUT Nominal gain GERR Gain error TCGERR Gain error thermal drift Nonlinearity 8 Initial, at TA = +25C -0.5% 0.05% 0.5% -1% 0.05% 1% 56 4.5 V VDD2 5.5 V -0.075% 0.015% 0.075% 2.7 V VDD2 3.6 V -0.1% 0.023% 0.1% Nonlinearity thermal drift Output noise PSRR Power-supply rejection ratio Rise-and-fall time VIN to VOUT signal delay CMTI Common-mode transient immunity Output common-mode voltage ROUT ppm/K 2.4 ppm/K VINP = VINN = 0 V 3.1 mVRMS vs VDD1, 10-kHz ripple 80 dB vs VDD2, 10-kHz ripple 61 0.5-V step, 10% to 90% 3.66 6.6 s 0.5-V step, 50% to 10%, unfiltered output 1.6 3.3 s 0.5-V step, 50% to 50%, unfiltered output 3.15 5.6 s 0.5-V step, 50% to 90%, unfiltered output 5.26 9.9 s VCM = 1 kV dB 2.5 3.75 kV/s 2.7 V VDD2 3.6 V 1.15 1.29 1.45 V 4.5 V VDD2 5.5 V 2.4 2.55 2.7 V Short-circuit current 20 mA Output resistance 2.5 POWER SUPPLY VDD1 High-side supply voltage 4.5 5.0 5.5 VDD2 Low-side supply voltage 2.7 5.0 5.5 IDD1 High-side supply current 5.4 8 mA IDD2 Low-side supply current 2.7 V < VDD2 < 3.6 V 3.8 6 mA 4.5 V < VDD2 < 5.5 V 4.4 7 mA PDD1 High-side power dissipation 27.0 44.0 mW PDD2 Low-side power dissipation 2.7 V < VDD2 < 3.6 V 11.4 21.6 mW 4.5 V < VDD2 < 5.5 V 22.0 38.5 mW 6 Submit Documentation Feedback V V Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 6.12 Typical Characteristics At VDD1 = VDD2 = 5 V, VINP = -250 mV to +250 mV, and VINN = 0 V, unless otherwise noted. 2 2 1.5 1.5 1 1 Input Offset (mV) Input Offset (mV) VDD2 = 2.7 V to 3.6 V 0.5 0 -0.5 0.5 0 -0.5 -1 -1 -1.5 -1.5 -2 4.5 4.75 5 VDD1 (V) 5.25 -2 2.7 5.5 3 3.3 3.6 VDD2 (V) Figure 1. Input Offset vs High-Side Supply Voltage Figure 2. Input Offset vs Low-Side Supply Voltage 2 2 1.5 1 1 Input Offset (mV) Input Offset (mV) VDD2 = 4.5 V to 5.5 V 1.5 0.5 0 -0.5 0.5 0 -0.5 -1 -1 -1.5 -1.5 -2 4.5 4.75 5 VDD2 (V) 5.25 -2 -40 -25 -10 5.5 130 40 120 30 110 20 100 90 80 110 125 -10 60 -30 100 95 0 -20 1 10 Input Frequency (kHz) 80 10 70 50 0.1 20 35 50 65 Temperature (C) Figure 4. Input Offset vs Temperature Input Current (A) CMRR (dB) Figure 3. Input Offset vs Low-Side Supply Voltage 5 -40 -400 Figure 5. Common-Mode Rejection Ratio vs Input Frequency -300 -200 -100 0 100 Input Voltage (mV) 200 300 Figure 6. Input Current vs Input Voltage Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 400 7 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) At VDD1 = VDD2 = 5 V, VINP = -250 mV to +250 mV, and VINN = 0 V, unless otherwise noted. 120 1 0.8 0.6 0.4 100 Gain Error (%) Input Bandwidth (kHz) 110 90 80 0.2 0 -0.2 -0.4 -0.6 70 -0.8 60 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 -1 4.5 110 125 Figure 7. Input Bandwidth vs Temperature 5.5 0.6 0.6 0.4 0.4 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 3 3.3 VDD2 = 4.5 V to 5.5 V 0.8 Gain Error (%) Gain Error (%) 5.25 1 VDD2 = 2.7 V to 3.6 V -1 2.7 -1 4.5 3.6 VDD2 (V) Figure 9. Gain Error vs Low-Side Supply Voltage 0.8 0 0.6 -10 Normalized Gain (dB) 10 0.2 0 -0.2 -0.4 -50 -70 80 95 Figure 11. Gain Error vs Temperature 110 125 5.5 -40 -0.8 20 35 50 65 Temperature (C) 5.25 -30 -60 5 5 VDD2 (V) -20 -0.6 -1 -40 -25 -10 4.75 Figure 10. Gain Error vs Low-Side Supply Voltage 1 0.4 Gain Error (%) 5 VDD1 (V) Figure 8. Gain Error vs High-Side Supply Voltage 1 0.8 8 4.75 -80 1 10 100 Input Frequency (kHz) 500 Figure 12. Normalized Gain vs Input Frequency Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 Typical Characteristics (continued) At VDD1 = VDD2 = 5 V, VINP = -250 mV to +250 mV, and VINN = 0 V, unless otherwise noted. 0 5 -30 4.5 -60 VOUTP VOUTN 4 Output Voltage (V) Output Phase () -90 -120 -150 -180 -210 -240 3.5 3 2.5 2 1.5 -270 1 -300 0.5 -330 -360 1 10 100 Input Frequency (kHz) 0 -400 1000 Figure 13. Output Phase vs Input Frequency -200 -100 0 100 Input Voltage (mV) 200 300 400 Figure 14. Output Voltage vs Input Voltage 3.6 3.3 -300 0.1 VDD2 = 2.7 V to 3.6 V VOUTP VOUTN 3 0.08 0.06 2.4 Nonlinearity (%) Output Voltage (V) 2.7 2.1 1.8 1.5 1.2 0.04 0.02 0 -0.02 -0.04 0.9 -0.06 0.6 -0.08 0.3 0 -400 -300 -200 -100 0 100 Input Voltage (mV) 200 300 -0.1 4.5 400 Figure 15. Output Voltage vs Input Voltage 5.25 5.5 0.1 VDD2 = 2.7 V to 3.6 V 0.08 0.06 0.06 0.04 0.04 0.02 0 -0.02 -0.04 0.02 0 -0.02 -0.04 -0.06 -0.06 -0.08 -0.08 3 3.3 3.6 -0.1 4.5 VDD2 (V) Figure 17. Nonlinearity vs Low-Side Supply Voltage VDD2 = 4.5 V to 5.5 V 0.08 Nonlinearity (%) Nonlinearity (%) 5 VDD1 (V) Figure 16. Nonlinearity vs High-Side Supply Voltage 0.1 -0.1 2.7 4.75 4.75 5 VDD2 (V) 5.25 5.5 Figure 18. Nonlinearity vs Low-Side Supply Voltage Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 9 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) At VDD1 = VDD2 = 5 V, VINP = -250 mV to +250 mV, and VINN = 0 V, unless otherwise noted. 0.1 0.1 VDD2 = 3 V VDD2 = 5 V 0.08 0.06 0.06 0.04 0.04 Nonlinearity (%) Nonlinearity (%) 0.08 0.02 0 -0.02 -0.04 0.02 0 -0.02 -0.04 -0.06 -0.06 -0.08 -0.08 -0.1 -250 -200 -150 -100 -50 0 50 100 Input Voltage (mV) 150 200 -0.1 -40 -25 -10 250 2600 100 2400 90 2200 80 2000 70 1800 1600 1400 110 125 20 800 10 100 VDD1 VDD2 40 30 10 95 50 1000 1 80 60 1200 600 0.1 20 35 50 65 Temperature (C) Figure 20. Nonlinearity vs Temperature PSRR (dB) Noise (nV/sqrt(Hz)) Figure 19. Nonlinearity vs Input Voltage 5 0 1 10 Ripple Frequency (kHz) Frequency (kHz) Figure 21. Output Noise Density vs Frequency 100 Figure 22. Power-Supply Rejection Ratio vs Ripple Frequency 10 Output Rise/Fall Time (s) 9 8 7 500 mV/div 6 5 4 3 200 mV/div 2 1 0 -40 -25 -10 500 mV/div 5 20 35 50 65 Temperature (C) 80 95 110 125 Time (2 ms/div) Figure 23. Output Rise and Fall Time vs Temperature 10 Submit Documentation Feedback Figure 24. Full-Scale Step Response Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 Typical Characteristics (continued) At VDD1 = VDD2 = 5 V, VINP = -250 mV to +250 mV, and VINN = 0 V, unless otherwise noted. 10 5 8 Signal Delay (s) 7 6 5 4 3 2 1 0 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 VDD2 rising VDD2 falling Output Common-Mode Voltage (V) 50% to 10% 50% to 50% 50% to 90% 9 4 3 2 1 0 3.5 110 125 Figure 25. Output Signal Delay Time vs Temperature 3.7 3.8 3.9 4 4.1 VDD2 (V) 4.2 4.3 4.4 4.5 Figure 26. Output Common-Mode Voltage vs Low-Side Supply Voltage 5 8 VDD2 = 2.7 V to 3.6 V VDD2 = 4.5 V to 5.5 V Output Common-Mode Voltage (V) 3.6 IDD1 IDD2 7 Supply Current (mA) 4 3 2 6 5 4 3 2 1 1 0 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 0 4.5 110 125 Figure 27. Output Common-Mode Voltage vs Temperature 4.75 5 Supply Voltage (V) 5.25 5.5 Figure 28. Supply Current vs Supply Voltage 8 8 7 6 6 Supply Current (mA) IDD2 (mA) VDD2 = 2.7 V to 3.6 V 7 5 4 3 2 1 0 2.7 5 4 3 2 1 3 3.3 3.6 IDD1 IDD2 0 -40 -25 -10 VDD2 (V) Figure 29. Low-Side Supply Current vs Low-Side Supply Voltage 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 30. Supply Current vs Temperature Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 11 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The AMC1100 consists of a delta-sigma modulator input stage including an internal reference and clock generator. The output of the modulator and clock signal are differentially transmitted over the integrated capacitive isolation barrier that separates the high- and low-voltage domains. The received bitstream and clock signals are synchronized and processed by a third-order analog filter with a nominal gain of 8 on the low-side and presented as a differential output of the device, as shown in the Functional Block Diagram section. The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity, as described in application report SLLA181, ISO72x Digital Isolator Magnetic-Field Immunity (available for download at www.ti.com). 7.2 Functional Block Diagram VDD1 VDD2 Isolation Barrier 2.5-V Reference 2.56-V Reference DATA TX RX VINP Retiming and 3rd order active low-pass filter u-Modulator VINN TX VOUTP VOUTN RX CLK RC oscillator GND1 12 GND2 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 7.3 Feature Description The differential analog input of the AMC1100 is a switched-capacitor circuit based on a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The device compares the differential input signal (VIN = VINP - VINN) against the internal reference of 2.5 V using internal capacitors that are continuously charged and discharged with a typical frequency of 10 MHz. With the S1 switches closed, CIND charges to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then both S2 switches close. CIND discharges to approximately GND1 + 0.8 V during this phase. Figure 31 shows the simplified equivalent input circuitry. VDD1 GND1 GND1 CINP = 3 pF 3 pF Equivalent Curcuit 400 : S1 S2 GND1 + 0.8 V CIND = 3.6 pF RIN = 28 k: 400 : S1 S2 GND1 + 0.8 V 3 pF CINN = 3 pF R IN GND1 GND1 1 f CLK * C IND GND1 (fCLK = 10 MHz) Figure 31. Equivalent Input Circuit The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. However, there are two restrictions on the analog input signals, VINP and VINN. If the input voltage exceeds the range GND1 - 0.5 V to VDD1 + 0.5 V, the input current must be limited to 10 mA to protect the implemented input protection diodes from damage. In addition, the device linearity and noise performance are ensured only when the differential analog input voltage remains within 250 mV. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 13 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com 7.4 Device Functional Modes The AMC1100 is powered on when the supplies are connected. The device is operated off a 5-V nominal supply on the high-side. The potential of the ground reference GND1 can be floating, which is usually the case in shuntbased current-measurement applications. TI recommends tying one side of the shunt to the GND1 pin of the AMC1100 to maintain the operating common-mode range requirements of the device. The low-side of the AMC1100 can be powered from a supply source with a nominal voltage of 3.0 V, 3.3 V, or 5.0 V. When operated at 5 V, the common-mode voltage of the output stage is set to 2.55 V nominal; in both other cases, the common-mode voltage is automatically set to 1.29 V. Although usually applied in shunt-based current-sensing circuits, the AMC1100 can also be used for isolated voltage measurement applications, as shown in a simplified way in Figure 32. In such applications, usually a resistor divider (R1 and R2 in Figure 32) is used to match the relatively small input voltage range of the AMC1100. R2 and the AMC1100 input resistance (RIN) also create a resistance divider that results in additional gain error. With the assumption that R1 and RIN have a considerably higher value than R2, the resulting total gain error can be estimated using Equation 1: R GERRTOT = GERR + 2 RIN where: * GERR = device gain error. (1) L1 R1 R2 RIN L2 Figure 32. Voltage Measurement Application 14 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The AMC1100 offers unique linearity, high input common-mode rejection, and low dc errors and drift. These features make the AMC1100 a robust, high-performance isolation amplifier for industrial applications where users and subsystems must be protected from high voltage potentials. 8.2 Typical Applications 8.2.1 The AMC1100 in Frequency Inverters A typical operation for the AMC1100 is isolated current and voltage measurement in frequency inverter applications (such as industrial motor drives, photovoltaic inverters, or uninterruptible power supplies), as conceptually shown in Figure 33. Depending on the end application, only two or three phase currents are being sensed. DC Link Gate Driver Gate Driver Gate Driver RSHUNT RSHUNT RSHUNT AMC1100 Gate Driver Gate Driver Gate Driver AMC1100 VDD1 AMC1100 AMC1100 VDD1 GND1 GND1 VDD1 VDD2 GND1 GND2 VINP VOUTP ADC1P VINN VOUTN ADC1N VDD2 GND2 VDD1 VDD2 VINP VOUTP GND1 GND2 VINN VOUTN ADC2P ADC2N VDD2 VINP VOUTP ADC3P GND2 VINN VOUTN ADC3N VINP VOUTP ADC4P VINN VOUTN ADC4N Figure 33. Isolated Current and Voltage Sensing in Frequency Inverters 8.2.1.1 Design Requirements Current measurement through the phase of a motor power line is done via the shunt resistor RSHUNT (in a twoterminal shunt); see Figure 34. For better performance, the differential signal is filtered using RC filters (components R2, R3, and C2). Optionally, C3 and C4 can be used to reduce charge dumping from the inputs. In this case, care must be taken when choosing the quality of these capacitors; mismatch in values of these capacitors leads to a common-mode error at the modulator input. Using NP0 capacitors is recommended, if necessary. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 15 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com Typical Applications (continued) Isolation Barrier Phase TMC320 C/F28xxx R1 Device 1 C1(1) 0.1 mF R2 12 W RSHUNT R3 12 W 2 VDD1 VINP VDD2 VOUTP 14 13 C5(1) 0.1 mF R (1) C2 330 pF C 3 C3 10 pF (optional) C4 10 pF (optional) 4 VINN VOUTN GND1 GND2 11 ADC R 9 Figure 34. Shunt-Based Current Sensing with the AMC1100 The isolated voltage measurement can be performed as described in the Device Functional Modes section. 8.2.1.2 Detailed Design Procedure The floating ground reference (GND1) is derived from the end of the shunt resistor, which is connected to the negative input of the AMC1100 (VINN). If a four-terminal shunt is used, the inputs of the AMC1100 are connected to the inner leads and GND1 is connected to one of the outer shunt leads. The differential input of the AMC1100 ensures accurate operation even in noisy environments. The differential output of the AMC1100 can either directly drive an analog-to-digital converter (ADC) input or can be further filtered before being processed by the ADC. 8.2.1.3 Application Curve In frequency inverter applications the power switches must be protected in case of an overcurrent condition. To allow fast powering off of the system, low delay caused by the isolation amplifier is required. Figure 35 shows the typical full-scale step response of the AMC1100. 500 mV/div 200 mV/div 500 mV/div Time (2 ms/div) Figure 35. Typical Step Response of the AMC1100 16 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 Typical Applications (continued) 8.2.2 The AMC1100 in Energy Metering Resulting from its immunity to magnetic fields, the AMC1100 can be used for shunt-based current sensing in smart electricity meter (e-meter) designs, as shown in Figure 36. Three AMC1100 devices are used for isolated current sensing. For voltage sensing, resistive dividers are usually used to reduce the common-mode voltage to levels that allow non-isolated measurement. L1 L2 L3 VDD2 = DVDD VDD1A AMC1100 4G-Modulator VDD1B AMC1100 ADC 3x dig. filter for currents DVDD MSP430F47167 Metrology MCU VDD1C AMC1100 ADC Sync ADC SysCLK ADC 3x dig. filter for voltage Data Application MCU ADC ADC Digital Core N Figure 36. The AMC1100 in an E-Meter Application 8.2.2.1 Design Requirements For best performance, an RC low-pass filter can be used in front of the AMC1100. Further improvement can be achieved by filtering the output signal of the device. In both cases, the values of the resistors and the capacitors must be tailored to the bandwidth requirements of the system. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 17 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com Typical Applications (continued) The analog output of the device is converted to the digital domain using the on-chip analog-to-digital converters (ADCs) of a suitable metrology microcontroller. The architecture of the MSP430F471x7 family of ultra-low power microcontrollers is tailored for this kind of applications. The MSP430F471x7 offers up to seven ADCs for simultaneous sampling: six of which are used for the three phase currents and voltages whereas the seventh channel can be used for additional voltage sensing of the neutral line for applications that require anti-tampering measures. 8.2.2.2 Detailed Design Procedure The high-side supply for the AMC1100 can be derived from the phase voltage using a capacitive-drop power supply (cap-drop), as shown in Figure 37 and described in the application report SLAA552, AMC1100: Replacement of Input Main Sensing Transformer in Inverters with Isolate Amplifier. Phase 5.1 V 470 n / 400 V 220 1N4007 5.6V 470 / 10 V Neutral GND Figure 37. Cap-Drop High-Side Power Supply for the AMC1100 Alternatively, the high-side power supply for each AMC1100 can also be derived from the low-side supply using the SN6501 to drive a transformer, as proven by the TI reference design TIPD121, Isolated Current Sensing Reference Design Solution, 5A, 2kV. 8.2.2.3 Application Curve One of the key parameters of an e-meter is its noise performance, which is mainly influenced by the performance of the ADC and the current sensor. When using a shunt-based approach, the sensor front-end consists of the actual shunt resistor and the isolated amplifier. Figure 38 shows the typical output noise density of the AMC1100 as a basis for overall performance estimations. 2600 2400 Noise (nV/sqrt(Hz)) 2200 2000 1800 1600 1400 1200 1000 800 600 0.1 1 10 100 Frequency (kHz) Figure 38. Output Noise Density of the AMC1100 18 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 9 Power Supply Recommendations In a typical frequency inverter application, the high-side power supply for the AMC1100 (VDD1) is derived from the system supply, as shown in Figure 39. For lowest cost, a Zener diode can be used to limit the voltage to 5 V 10%. A 0.1-F decoupling capacitor is recommended for filtering this power-supply path. Place this capacitor (C1) as close as possible to the VDD1 pin for best performance. If better filtering is required, an additional 1-F to 10-F capacitor can be used. HV+ Floating Power Supply 20 V R1 800 Gate Driver AMC1100 5.1 V VDD1 VDD2 Z1 1N751A 3.3 V, or 5.0 V C4 0.1F C1 0.1F GND1 GND2 RSHUNT VINP to load R2 12 ADS7263 VINN Gate Driver VOUTP C3 330pF VOUTN R3 12 HV- Figure 39. Zener Diode Based High-Side Supply For higher power efficiency and better performance, a buck converter can be used; an example of such an approach is based on the LM5017. A reference design including performance test results and layout documentation can be downloaded at PMP9480, Isolated Bias Supplies + Isolated Amplifier Combo for Line Voltage or Current Measurement. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 19 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com 10 Layout 10.1 Layout Guidelines A layout recommendation showing the critical placement of the decoupling capacitors that be placed as close as possible to the AMC1100 while maintaining a differential routing of the input signals is shown in Figure 40. To maintain the isolation barrier and the common-mode transient immunity (CMTI) of the device, keep the distance between the high-side ground (GND1) and the low-side ground (GND2) at a maximum; that is, the entire area underneath the device must be kept free of any conducting materials. 10.2 Layout Example Top View 12 W SMD 0603 To Shunt 12 W SMD 0603 330 pF SMD 0603 VDD1 VDD2 VINP VOUTP 0.1mF VINN VOUTN 1206 SMD 1206 GND1 GND2 0.1 mF SMD 1206 LEGEND Top layer; copper pour and traces 0.1 mF SMD Device To Filter or ADC Clearance area. Keep free of any conductive materials. High-side area Controller-side area Via Figure 40. Example Layout 20 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature 11.1.1.1 Isolation Glossary Creepage Distance: The shortest path between two conductive input-to-output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance: The shortest distance between two conductive input-to-output leads measured through air (line of sight). Input-to-Output Barrier Capacitance: The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to-Output Barrier Resistance: The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit: An internal circuit directly connected to an external supply mains or other equivalent source that supplies the primary circuit electric power. Secondary Circuit: A circuit with no direct connection to primary power that derives its power from a separate isolated source. Comparative Tracking Index (CTI): CTI is an index used for electrical insulating materials. It is defined as the numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface. The higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive insulation surface degradation by small localized sparks. Such sparks result from a surface film of a conducting contaminant breaking on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. 11.1.1.1.1 Insulation: Operational insulation--Insulation needed for correct equipment operation. Basic insulation--Insulation to provide basic protection against electric shock. Supplementary insulation--Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 21 AMC1100 SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 www.ti.com Device Support (continued) Double insulation--Insulation comprising both basic and supplementary insulation. Reinforced insulation--A single insulation system that provides a degree of protection against electric shock equivalent to double insulation. 11.1.1.1.2 Pollution Degree: Pollution Degree 1--No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence on device performance. Pollution Degree 2--Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation is to be expected. Pollution Degree 3--Conductive pollution, or dry nonconductive pollution that becomes conductive because of condensation, occurs. Condensation is to be expected. Pollution Degree 4--Continuous conductivity occurs as a result of conductive dust, rain, or other wet conditions. 11.1.1.1.3 Installation Category: Overvoltage Category--This section is directed at insulation coordination by identifying the transient overvoltages that may occur, and by assigning four different levels as indicated in IEC 60664. 1. Signal Level: Special equipment or parts of equipment. 2. Local Level: Portable equipment and so forth 3. Distribution Level: Fixed installation. 4. Primary Supply Level: Overhead lines, cable systems. Each category should be subject to smaller transients than the previous category. 22 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 AMC1100 www.ti.com SBAS562A - APRIL 2012 - REVISED DECEMBER 2014 11.2 Documentation Support 11.2.1 Related Documentation High-Voltage Lifetime of the ISO72x Family of Digital Isolators, SLLA197 ISO72x Digital Isolator Magnetic-Field Immunity, SLLA181 AMC1100: Replacement of Input Main Sensing Transformer in Inverters with Isolate Amplifier, SLAA552 Isolated Current Sensing Reference Design Solution, 5A, 2kV, TIPD121 Isolated Bias Supplies + Isolated Amplifier Combo for Line Voltage or Current Measurement, PMP9480 TPS62120 Data Sheet, SLVSAD5 MSP430F471xx Data Sheet, SLAS626 SN6501 Data Sheet, SLLSEA0 LM5017 Data Sheet, SNVS783 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: AMC1100 23 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) AMC1100DUB ACTIVE SOP DUB 8 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 AMC1100 AMC1100DUBR ACTIVE SOP DUB 8 350 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 AMC1100 AMC1100DWV ACTIVE SOIC DWV 8 64 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 105 AMC1100 AMC1100DWVR ACTIVE SOIC DWV 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 105 AMC1100 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AMC1100DUBR SOP DUB 8 350 330.0 24.4 10.9 10.01 5.85 16.0 24.0 Q1 AMC1100DWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AMC1100DUBR SOP DUB 8 350 346.0 346.0 29.0 AMC1100DWVR SOIC DWV 8 1000 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE DUB0008A SOP - 4.85 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE 10.7 TYP 10.1 C SEATING PLANE ALTERNATE PIN 1 ID A 0.1 C PIN 1 ID 8 1 6X 2.54 9.55 9.02 NOTE 3 2X 7.62 4X (1.524) 4 5 4X (0.99) B 6.67 6.57 8X 0.555 0.355 0.1 C A B 6.62 6.52 TOP MOLD 0.355 TYP 0.204 SEE DETAIL A 4.85 MAX 0.635 GAGE PLANE 0 -4 1.45 1.15 0.38 MIN DETAIL A TYPICAL 4222355/D 08/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.254 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DUB0008A SOP - 4.85 mm max height SMALL OUTLINE PACKAGE 8X (2.35) SYMM (R0.05) TYP 1 8 8X (0.65) SYMM 6X (2.54) 5 4 (9.1) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:5X SOLDER MASK OPENING 0.07 MAX ALL AROUND METAL UNDER SOLDER MASK METAL EXPOSED METAL SOLDER MASK OPENING EXPOSED METAL 0.07 MIN ALL AROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222355/D 08/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DUB0008A SOP - 4.85 mm max height SMALL OUTLINE PACKAGE 8X (2.35) SYMM (R0.05) TYP 1 8 8X (0.65) SYMM 6X (2.54) 5 4 (9.1) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:5X 4222355/D 08/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DWV0008A SOIC - 2.8 mm max height SCALE 2.000 SOIC C SEATING PLANE 11.5 0.25 TYP PIN 1 ID AREA 0.1 C 6X 1.27 8 1 2X 3.81 5.95 5.75 NOTE 3 4 5 0.51 0.31 0.25 C A 8X A 7.6 7.4 NOTE 4 B B 2.8 MAX 0.33 TYP 0.13 SEE DETAIL A (2.286) 0.25 GAGE PLANE 0 -8 0.46 0.36 1.0 0.5 (2) DETAIL A TYPICAL 4218796/A 09/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. www.ti.com EXAMPLE BOARD LAYOUT DWV0008A SOIC - 2.8 mm max height SOIC 8X (1.8) SEE DETAILS SYMM 8X (0.6) SYMM 6X (1.27) (10.9) LAND PATTERN EXAMPLE 9.1 mm NOMINAL CLEARANCE/CREEPAGE SCALE:6X METAL SOLDER MASK OPENING SOLDER MASK OPENING 0.07 MAX ALL AROUND METAL 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4218796/A 09/2013 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DWV0008A SOIC - 2.8 mm max height SOIC 8X (1.8) SYMM 8X (0.6) SYMM 6X (1.27) (10.9) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4218796/A 09/2013 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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