Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE MAY 1996
1996 Integrated Device Technology, Inc. 3569/-
CMOS STATIC RAM
1 MEG (256K x 4-BIT)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT71028S70
FEATURES:
• 256K x 4 CMOS static RAM
• Equal access and cycle times
— Commercial: 70ns
• One Chip Select plus one Output Enable pin
• Bidirectional data Inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Available in 400 mil Plastic SOJ package
DESCRIPTION:
The IDT71028 is a 1,024,576-bit medium-speed static
RAM organized as 256K x 4. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
The IDT71028 has an output enable pin which operates as
fast as 30ns, with address access times as fast as 70ns. All
bidirectional inputs and outputs of the IDT71028 are TTL-
compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ
package.
FUNCTIONAL BLOCK DIAGRAM
1
A17
A0
I/O CONTROL
I/O0 – I/O3
CONTROL
LOGIC
WE
OE
CS
3569 drw 01
4 4
ADDRESS
DECODER 1,048,576-BIT
MEMORY
ARRAY
2
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Com’l. Unit
VTERM(2) Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TAOperating Temperature 0 to +70 °C
TBIAS Temperature Under –55 to +125 °C
Bias
TSTG Storage Temperature –55 to +125 °C
PTPower Dissipation 1.25 W
IOUT DC Output Current 50 mA
NOTES: 3569 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
PIN CONFIGURATION
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — VCC+0.5 V
VIL Input Low Voltage –0.5(1) — 0.8 V
NOTE: 3569 tbl 04
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
(3)
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10% IDT71028
Symbol Parameter Test Condition Min. Max. Unit
|ILI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA
|ILO| Output Leakage Current VCC = Max.,
CS
= VIH, VOUT = GND to VCC — 5 µA
VOL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 V
VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — V
3569 tbl 05
SOJ
TOP VIEW
TRUTH TABLE(1,2)
CS
CS OE
OE WE
WE
I/O Function
L L H DATAOUT Read Data
L X L DATAIN Write Data
L H H High-Z Output Disabled
H X X High-Z Deselected - Standby (ISB)
VHC X X High-Z Deselected - Standby (ISB1)
NOTES: 3569 tbl 01
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥VHC or ≤VLC.
5
6
7
8
9
12
13
14
GND
A0
A1
A2
1
2
3
4
28
27
26
25
24
23
22
21
20
17
16
15
SO28-6
A3
A4
A5
A7
A17
A16
A15
A14
NC
A13
OE WE
I/O0
3569 drw 02
A810 19
A12
A911 18
A11
A10
VCC
A6
CS
I/O1
I/O2
I/O3
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 3dV 8 pF
CI/O I/O Capacitance VOUT = 3dV 8 pF
NOTE: 3569 tbl 03
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
3
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE
*Including jig and scope capacitance.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
3569 tbl 07
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V) 71028S70
Symbol Parameter Com'l. Mil. Unit
ICC Dynamic Operating Current, CS2 ≥ VIH and 140 — mA
CS2 ≥ VIH and
CS1
≤ VIL, Outputs Open,
VCC = Max., f = fMAX(2)
ISB Standby Power Supply Current (TTL Level) 35 — mA
CS1
≥ VIH or CS2 ≤ VIL, Outputs Open,
VCC = Max., f = fMAX(2)
ISB1 Full Standby Power Supply Current 10 — mA
(CMOS Level)
CS1
≥ VHC,
or CS2 ≤ VLC Outputs Open,
VCC = Max., f = 0(2), VIN ≤ VLC or VIN ≥ VHC
NOTES: 3569 tbl 06
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
3569 drw 03
480Ω
255Ω
30pF
DATAOUT
5V
3569 drw 04
480
Ω
255
Ω
5pF*
DATA
OUT
5V
4
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Commercial Temperature Range)
71028S70
Symbol Parameter Min. Max. Unit
Read Cycle
tRC Read Cycle Time 70 — ns
tAA Address Access Time —70 ns
tACS Chip Select Access Time —70 ns
tCLZ(2) Chip Select to Output in Low-Z 3 — ns
tCHZ(2) Chip Deselect to Output in High-Z 0 30 ns
tOE Output Enable to Output Valid — 30 ns
tOLZ(2) Output Enable to Output in Low-Z 0 — ns
tOHZ(2) Output Disable to Output in High-Z 0 30 ns
tOH Output Hold from Address Change 4 — ns
tPU(2) Chip Select to Power-Up Time 0 — ns
tPD(2) Chip Deselect to Power-Down Time — 70 ns
Write Cycle
tWC Write Cycle Time 70 — ns
tAW Address Valid to End-of-Write 60 — ns
tCW Chip Select to End-of-Write 60 — ns
tAS Address Set-up Time 0— ns
tWP Write Pulse Width 45 — ns
tWR Write Recovery Time 0— ns
tDW Data Valid to End-of-Write 30 — ns
tDH Data Hold Time 0— ns
tOW(2) Output Active from End-of-Write 5 — ns
tWHZ(2) Write Enable to Output in High-Z 0 30 ns
NOTES: 3569 tbl 08
1. 0°C to +70°C temperature range only.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
5
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise tAA is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
ADDRESS
3569 drw 05
OE
CS
DATAOUT
(5) (5) (5)
(5)
DATAOUT VALID
HIGH IMPEDANCE
tAA
tRC
tOE
tACS
tOLZ
tCHZ
tCLZ
(3)
tOHZ
VCC SUPPLY
CURRENT
tPU tPD
ICC
ISB
DATA
OUT
ADDRESS
3569 drw 6
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALIDPREVIOUS DATA
OUT
VALID
6
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
WE
WE
CONTROLLED TIMING)(1,2,3,5)
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CS
CS
CONTROLLED TIMING)(1,2,5)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
ADDRESS
CS
WE
DATAOUT
DATAIN
3569 drw 07
(6)
(4) (4)
(3)
(6) (6)
DATAIN VALID
HIGH IMPEDANCE
tWC
tAS
tWHZ
tWP
tCHZ
tOW
tDW tDH
tWR
tAW
CS
ADDRESS
WE
3569 drw 08
DATAIN VALID
tAW
tWC
tCW
tAS tWR
tDW tDH
DATAIN
7
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
S
Power
XX
Speed
XX
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
Y
70
71028
Device
Type
IDT
Speed in nanoseconds
3569 drw 09
400-mil Small Outline J-Bend (SO28-6)
