 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DOutput Swing Includes Both Supply Rails
DLow Noise . . . 12 nV/Hz Typ at f = 1 kHz
DLow Input Bias Current ...1 pA Typ
DFully Specified for Both Single-Supply and
Split-Supply Operation
DLow Power . . . 500 µA Max
DCommon-Mode Input Voltage Range
Includes Negative Rail
DLow Input Offset Voltage
950 µV Max at TA = 25°C (TLV226xA)
DWide Supply Voltage Range
2.7 V to 8 V
DMacromodel Included
DAvailable in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
The TLV2262 and TLV2264 are dual and quad low
voltage operational amplifiers from Texas Instru-
ments. Both devices exhibit rail-to-rail output
performance for increased dynamic range in
single or split supply applications. The TLV226x
family offers a compromise between the micro-
power TLV225x and the ac performance of the
TLC227x. It has low supply current for battery-
powered applications, while still having adequate
ac performance for applications that demand it.
This family is fully characterized a t 3 V and 5 V and
is optimized for low-voltage applications. The
noise performance has been dramatically im-
proved over previous generations of CMOS
amplifiers. Figure 1 depicts the low level of noise
voltage for this CMOS amplifier, which has only
200 µA (typ) of supply current per amplifier.
The TLV226x, exhibiting high input impedance
and low noise, are excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the micro-
power dissipation levels combined with 3-V
operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the
rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with
analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available and has a
maximum input offset voltage of 950 µV.
The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output
dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to
be used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption make them ideal for high density, battery-powered equipment.
Copyright 1997−2006, Texas Instruments Incorporated
  !"# $ %!!# $  &%'(# #)
!%#$ !" # $&#$ &! #* #!"$  $ $#!%"#$
$#! +!!#,) !%# &!$$- $ # $$!(, (%
#$#-  (( &!"#!$)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOH
| IOH | − High-Level Output Current − µA
Figure 1
2
1
0.5
00 500 1000
3
3.5
4
1500 200
0
2.5
1.5
TA = −55°C
VDD = 3 V
TA = 85°C
TA = −40°C
TA = 125°C
TA = 25°C
 &!%#$ "&(# # ./0.0 (( &!"#!$ ! #$#
%($$ #*!+$ #)  (( #*! &!%#$ &!%#
&!$$- $ # $$!(, (% #$#-  (( &!"#!$)
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262 AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CERAMIC
FLATPACK
(U)
0°C to 70°C2.5 mV TLV2262CD TLV2262CP TLV2262CPWLE
−40°C to 125°C
950 µV
TLV2262AID
TLV2262AIP
TLV2262AIPWLE
−40°C to 125°C
950 µV
2.5 mV
TLV2262AID
TLV2262ID
TLV2262AIP
TLV2262IP
TLV2262AIPWLE
−40°C to 125°C
950 µV
TLV2262AQD
−40°C to 125°C
950 µV
2.5 mV
TLV2262AQD
TLV2262QD
−55°C to 125°C950 µV
2.5 mV
TLV2262AMFK
TLV2262MFK TLV2262AMJG
TLV2262MJG
TLV2262AMU
TLV2262MU
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262CDR).
The PW package is available only left-end taped and reeled.
§Chips are tested at 25°C.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
TLV2264 AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)
CERAMIC
FLATPACK
(W)
−40
°
C to
950 µV
TLV2264AID
TLV2264AIN
TLV2264AIPWLE
−40 C to
125°C
950 µV
2.5 mV
TLV2264AID
TLV2264ID
TLV2264AIN
TLV2264IN
TLV2264AIPWLE
−40
°
C to
950 µV
TLV2264AQD
−40 C to
125°C
950 µV
2.5 mV
TLV2264AQD
TLV2264QD
−55°C to
125°C950 µV
2.5 mV
TLV2264AMFK
TLV2264MFK TLV2264AMJ
TLV2264MJ
TLV2264AMW
TLV2264MW
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262IDR).
The PW package is available only left-end taped and reeled.
§Chips are tested at 25°C.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262C, TLV2262AC
TLV2262I, TLV2262AI
TLV2262Q, TLV2262AQ
D, P, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN
1IN+
VDD/GND
VDD+
2OUT
2IN
2IN+
NC
VCC +
2OUT
2IN
2IN +
NC
1OUT
1IN
1IN +
VCC/GND
1
2
3
4
5
10
9
8
7
6
1
2
3
4
8
7
6
5
1OUT
1IN
1IN+
VDD/GND
VDD+
2OUT
2IN
2IN+
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN
NC
NC
1IN
NC
1IN+
NC
NC
1OUT
NC
2IN+
NC NC
NC
NC VDD+
VDD−
TLV2262M, TLV2262AM
FK PACKAGE
(TOP VIEW)
/GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN
1IN+
VDD+
2IN+
2IN
2OUT
4OUT
4IN
4IN+
VDD/GND
3IN+
3IN
3OUT
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC/GND
NC
3IN+
1IN+
NC
VCC+
NC
2IN+
1IN −
1OUT
NC
3OUT
3IN − 4OUT
4IN −
2IN −
2OUT
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN
1IN+
VDD+
2IN+
2IN
2OUT
4OUT
4IN
4IN+
VDD/GND
3IN+
3IN
3OUT
TLV2264I, TLV2264AI
TLV2264Q, TLV2264AQ
D, N, OR PW PACKAGE
(TOP VIEW)
TLV2264M, TLV2264AM
J OR W PACKAGE
(TOP VIEW)
TLV2264M, TLV2264AM
FK PACKAGE
(TOP VIEW)
TLV2662M, TLV2262AM
U PACKAGE
(TOP VIEW)
TLV2262M, TLV2262AM
JG PACKAGE
(TOP VIEW)
Template Release Date: 7−11−94
1
1
SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
1
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
equivalent schematic (each amplifier)
Q3 Q6 Q9 Q12 Q14 Q16
Q2 Q5 Q7 Q8 Q10 Q11
D1
Q17Q15Q13
Q4Q1
R5
C1
VDD+
IN+
IN
R3 R4 R1 R2
OUT
VDD/GND
R6
ACTUAL DEVICE COMPONENT COUNT
COMPONENT TLV2252 TLV2254
Transistors 38 76
Resistors 28 54
Diodes 9 18
Capacitors 3 6
Includes both amplifiers and all ESD, bias, and trim circuitry
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input, see Note 1) VDD0.3 V to VDD+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of VDD ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current (at or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: I suffix 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q suffix 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to VDD .
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below VDD − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
TA
25
°
C
DERATING FACTOR
TA = 85
°
C
TA = 125
°
C
TA 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
D−8 725 mW 5.8 mW/°C377 mW 145 mW
D−14 950 mW 7.6 mW/°C 494 mW 190 mW
FK 1375 mW 11.0 mW/°C 715 mW 275 mW
J1375 mW 11.0 mW/°C 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 210 mW
N1150 mW 9.2 mW/°C 598 mW
P1000 mW 8.0 mW/°C 520 mW 200 mW
PW−8 525 mW 4.2 mW/°C 273 mW 105 mW
PW−14 700 mW 5.6 mW/°C 364 mW
U700 mW 5.5 mW/°C 150 mW
W700 mW 5.5 mW/°C370 mW 150 mW
recommended operating conditions
I SUFFIX Q SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD±   2.7 8 2.7 8 2.7 8 V
Input voltage range, VIVDD VDD+1.3 VDD VDD+1.3 VDD VDD+1.3 V
Common-mode input voltage, VIC VDD VDD+1.3 VDD VDD+1.3 VDD VDD+1.3 V
Operating free-air temperature, TA−40 125 −40 125 −55 125 °C
NOTE 1: All voltage values, except differential voltages, are with respect to VDD .
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA
TLV2262I TLV2262AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO Temperature coefficient
of input offset voltage 25°C
to 85°C2 2 µV/°C
Input offset voltage
long-term drift
(see Note 4) VDD± = ±1.5 V, VIC = 0,
V = 0, R = 50
25°C 0.003 0.003 µV/mo
DD IC
VO = 0, RS = 50 25°C 0.5 60 0.5 60
I
IO
Input offset current
OS
85°C 150 150 pA
IIO
Input offset current
Full range 800 800
pA
25°C 1 60 1 60
I
IB
Input bias current 85°C 150 150 pA
IIB
Input bias current
Full range 800 800
pA
VICR
Common-mode input
voltage range
RS = 50
|VIO |≤5 mV
25°C0
to
2
0.3
to
2.2
0
to
2
0.3
to
2.2
V
V
ICR
Common-mode input
voltage range
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
Full range 0
to
1.7
0
to
1.7
V
IOH = −20 µA 25°C 2.99 2.99
High-level output
IOH = −100 µA
25°C 2.85 2.85
V
OH
High-level output
voltage
I
OH
= −100
µ
A
Full range 2.825 2.825 V
VOH
voltage
IOH = −400 µA
25°C 2.7 2.7
V
I
OH
= −400
µ
A
Full range 2.65 2.65
VIC = 1.5 V, IOL = 50 µA 25°C 10 10
Low-level output
VIC = 1.5 V,
IOL = 500 µA
25°C 100 100
V
OL
Low-level output
voltage
V
IC
= 1.5 V,
I
OL
= 500
µ
A
Full range 150 150 mV
VOL
voltage
VIC = 1.5 V,
IOL = 1 A
25°C 200 200
mV
V
IC
= 1.5 V,
I
OL
= 1
A
Full range 300 300
Large-signal differential
VIC = 1.5 V,
RL = 50 k
25°C 60 100 60 100
A
VD
Large-signal differential
voltage amplification
VIC = 1.5 V,
VO = 1 V to 2 V
R
L
= 50 k
Full range 30 30 V/mV
AVD
voltage amplification
VO = 1 V to 2 V
RL = 1 M25°C 100 100
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, P package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 270 270
CMRR
Common-mode
rejection ratio
V
IC
= 0 to 1.7 V,
V = 1.5 V, R = 50
25°C 65 75 65 77
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
VO = 1.5 V, RS = 50 Full range 60 60
dB
kSVR
Supply voltage rejection
VDD = 2.7 V to 8 V,
25°C 80 95 80 100
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)
VDD = 2.7 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
Full range is − 40°C to 125°C.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2262I TLV2262AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 1.5 V,
No load
25°C 400 500 400 500
µA
I
DD
Supply current
V
O
= 1.5 V,
No load
Full range 500 500 µ
A
Full range is − 40°C to 125°C.
TLV2262I operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2262I TLV2262AI
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VO = 1.1 V to 1.9 V,
RL = 50 k,
25°C0.35 0.55 0.35 0.55
SR Slew rate at unity gain VO = 1.1 V to 1.9 V,
CL = 100 pF
RL = 50 k
,
Full
0.3
0.3
V/µs
SR
Slew rate at unity gain
CL = 100 pF
Full
range 0.3 0.3
V/µs
Vn
Equivalent input noise
f = 10 Hz 25°C 43 43
nV/Hz
Vn
Equivalent input noise
voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.6 0.6
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1 1 µV
InEquivalent input noise
current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.03% 0.03%
THD + N
Total harmonic
distortion plus noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.05% 0.05%
Gain-bandwidth
f = 1 kHz,
RL = 50 k
,
25°C
0.67
0.67
MHz
Gain-bandwidth
product
f = 1 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.67 0.67 MHz
BOM
Maximum
output-swing
VO(PP) = 1 V,
AV = 1,
25°C
395
395
kHz
BOM
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 k,
AV = 1,
CL = 100 pF25°C395 395 kHz
AV = −1,
To 0.1%
5.6
5.6
ts
Settling time
AV = −1,
Step = 1 V to 2 V,
To 0.1%
25°C
5.6 5.6
s
tsSettling time
Step = 1 V to 2 V,
R
L
= 50 k,
C = 100 pF
To 0.01%
25°C
12.5
12.5
µs
RL = 50 k,
CL = 100 pFTo 0.01% 12.5 12.5
φmPhase margin at
unity gain R
L
= 50 k, C
L
= 100 pF25°C 55°55°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is − 40°C to 125°C.
Referenced to 1.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA
TLV2262I TLV2262AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
25 C
to 85°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4) VDD± = ±2.5 V, VIC = 0,
V = 0, R = 50
25°C 0.003 0.003 µV/mo
DD IC
VO = 0, RS = 50 25°C 0.5 60 0.5 60
I
IO
Input offset current
OS
85°C 150 150 pA
IIO
Input offset current
Full range 800 800
pA
25°C 1 60 1 60
I
IB
Input bias current 85°C 150 150 pA
IIB
Input bias current
Full range 800 800
pA
0
0.3
0
0.3
25
°
C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
|VIO |≤5 mV,
RS = 50
25 C
to
4
to
4.2
to
4
to
4.2
V
V
ICR
Common-mode input
voltage range |
V
IO
| ≤
5 mV,
R
S
= 50
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
3.5
to
3.5
IOH = −20 µA 25°C 4.99 4.99
IOH = −100 µA
25°C 4.85 4.94 4.85 4.94
V
OH
High-level output voltage
I
OH
= −100
µ
A
Full range 4.82 4.82 V
VOH
High-level output voltage
IOH = −400 µA
25°C 4.7 4.85 4.7 4.85
V
I
OH
= −400
µ
A
Full range 4.6 4.6
VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01
VIC = 2.5 V,
IOL = 500 µA
25°C 0.09 0.15 0.09 0.15
V
OL
Low-level output voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
Low-level output voltage
VIC = 2.5 V,
IOL = 1 A
25°C 0.2 0.3 0.2 0.3
V
V
IC
= 2.5 V,
I
OL
= 1
A
Full range 0.3 0.3
Large-signal differential
VIC = 2.5 V,
RL = 50 k
25°C 80 170 80 170
A
VD
Large-signal differential
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 50 k
Full range 55 55 V/mV
AVD
voltage amplification
V
O
= 1 V to 4 V
RL = 1 M25°C 550 550
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, P package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 240 240
CMRR
Common-mode rejection
VIC = 0 to 2.7 V,
25°C 70 83 70 83
dB
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V,
VO = 2.5 V, RS = 50 Full range 70 70
dB
kSVR
Supply voltage rejection
VDD = 4.4 V to 8 V,
25°C 80 95 80 95
dB
kSVR
Supply voltage rejection
ratio (VDD/VIO)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80 dB
Full range is − 40°C to 125°C.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2262I TLV2262AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 2.5 V,
No load
25°C 400 500 400 500
A
IDD Supply current VO = 2.5 V, No load Full range 500 500 µA
Full range is − 40°C to 125°C.
TLV2262I operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2262I TLV2262AI
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at unity
VO = 1.5 V to 3.5 V,
RL = 50 k,
25°C0.35 0.55 0.35 0.55
SR Slew rate at unity
gain
VO = 1.5 V to 3.5 V,
CL = 100 pF
RL = 50 k
,
Full
0.3
0.3
V/µs
SR
gain
CL = 100 pF
Full
range 0.3 0.3
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 40 40
nV/Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.7 0.7
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.3 1.3 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.017% 0.017%
THD + N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.03% 0.03%
Gain-bandwidth
f = 50 kHz,
RL = 50 k
,
25°C
0.71
0.71
MHz
Gain-bandwidth
product
f = 50 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.71 0.71 MHz
BOM
Maximum output-
VO(PP) = 2 V,
AV = 1,
25°C
185
185
kHz
BOM
Maximum output-
swing bandwidth
VO(PP) = 2 V,
R
L
= 50 k,
AV = 1,
C
L
= 100 pF25°C185 185 kHz
AV = −1,
To 0.1%
6.4
6.4
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
To 0.1%
25°C
6.4 6.4
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 50 k,
To 0.01%
25°C
14.1
14.1
µs
RL = 50 k,
CL = 100 pFTo 0.01% 14.1 14.1
φmPhase margin at
unity gain
RL = 50 k
,
CL = 100 pF
25°C 56°56°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is − 40°C to 125°C.
Referenced to 2.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA
TLV2264I TLV2264AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
25 C
to 85°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4) VDD± = ±1.5 V,
VIC = 0,
V = 0,
25°C 0.003 0.003 µV/mo
VIC = 0,
VO = 0,
RS= 50
25°C 0.5 60 0.5 60
I
IO
Input offset current
O
R
S
= 50
85°C 150 150 pA
IIO
Input offset current
Full range 800 800
pA
25°C 1 60 1 60
I
IB
Input bias current 85°C 150 150 pA
IIB
Input bias current
Full range 800 800
pA
0
0.3
0
0.3
25
°
C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
RS = 50
|VIO |≤5 mV
25 C
to
2
to
2.2
to
2
to
2.2
V
V
ICR
Common-mode input
voltage range
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
1.7
to
1.7
IOH = −20 µA 25°C 2.99 2.99
High-level output
IOH = −100 µA
25°C 2.85 2.85
V
OH
High-level output
voltage
I
OH
= −100
µ
A
Full range 2.825 2.825 V
VOH
voltage
IOH = −400 µA
25°C 2.7 2.7
V
I
OH
= −400
µ
A
Full range 2.65 2.65
VIC = 1.5 V, IOL = 50 µA 25°C 10 10
VIC = 1.5 V,
IOL = 500 µA
25°C 100 100
V
OL
Low-level output voltage
V
IC
= 1.5 V,
I
OL
= 500
µ
A
Full range 150 150 mV
VOL
Low-level output voltage
VIC = 1.5 V,
IOL = 1 A
25°C 200 200
mV
V
IC
= 1.5 V,
I
OL
= 1
A
Full range 300 300
Large-signal differential
V = 1.5 V,
RL = 50 k
25°C 60 100 60 100
A
VD
Large-signal differential
voltage amplification
VIC = 1.5 V,
VO = 1 to 2 V
R
L
= 50 k
Full range 30 30 V/mV
AVD
voltage amplification
IC
V
O
= 1 to 2 V
RL = 1 M25°C 100 100
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, N package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 270 270
CMRR
Common-mode
VIC = 0 to 1.7 V, 25°C 65 75 65 77
dB
CMRR
Common-mode
rejection ratio VO = 1.5 V, RS = 50 Full range 60 60
dB
kSVR
Supply voltage rejection
ratio ( V/V)
VDD = 2.7 V to 8 V, 25°C 80 95 80 100
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)VIC = VDD/2, No load Full range 80 80
dB
Full range is − 40°C to 125°C.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2264I TLV2264AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
(four amplifiers)
VO = 1.5 V,
No load
25°C 0.8 1 0.8 1
mA
I
DD
Supply current
(four amplifiers)
V
O
= 1.5 V,
No load
Full range 1 1
mA
Full range is − 40°C to 125°C.
TLV2264I operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2264I TLV2264AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
25°C
0.35
0.55
0.35
0.55
Slew rate at unity
VO = 0.7 V to 1.7 V,
RL = 50 k,
25°C 0.35 0.55 0.35 0.55
SR Slew rate at unity
gain
VO = 0.7 V to 1.7 V
,
CL = 100 pF
RL = 50 k
,
Full
0.3
0.3
V/µs
SR
gain
CL = 100 pF
Full
range 0.3 0.3
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 43 43
nV/Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.6 0.6
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1 1 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V
,
f = 20 kHz,
AV = 1
25°C
0.03% 0.03%
THD + N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.05% 0.05%
Gain-bandwidth
f = 1 kHz,
RL = 50 k
,
25°C
0.67
0.67
MHz
Gain-bandwidth
product
f = 1 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.67 0.67 MHz
BOM
Maximum
output-swing
VO(PP) = 1 V,
‡,
AV = 1,
25°C
395
395
kHz
BOM
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 k‡,
AV = 1,
CL = 100 pF25°C395 395 kHz
AV = −1,
To 0.1%
5.6
5.6
ts
Settling time
AV = −1,
Step = 1 V to 2 V,
‡,
To 0.1%
25°C
5.6 5.6
s
tsSettling time
Step = 1 V to 2 V,
R
L
= 50 k‡,
C = 100 pF
To 0.01%
25°C
12.5
12.5
µs
RL = 50 k‡,
CL = 100 pFTo 0.01% 12.5 12.5
φmPhase margin at
unity gain R
L
= 50 k, C
L
= 100 pF25°C 55°55°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is − 40°C to 125°C.
Referenced to 1.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA
TLV2264I TLV2264AI
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
25 C
to 85°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4) VDD± = ±2.5 V,
VIC = 0,
VO = 0,
25°C 0.003 0.003 µV/mo
VIC = 0,
VO = 0,
RS = 50
25°C 0.5 60 0.5 60
I
IO
Input offset current
R
S
= 50
85°C 150 150 pA
IIO
Input offset current
Full range 800 800
pA
25°C 1 60 1 60
I
IB
Input bias current 85°C 150 150 pA
IIB
Input bias current
Full range 800 800
pA
0
0.3
0
0.3
25°C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
|VIO |≤5 mV,
RS = 50
25 C
to
4
to
4.2
to
4
to
4.2
V
V
ICR
Common-mode input
voltage range |
V
IO
| ≤
5 mV,
R
S
= 50
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
3.5
to
3.5
IOH = −20 µA 25°C 4.99 4.99
High-level output
IOH = −100 µA
25°C 4.85 4.94 4.85 4.94
V
OH
High-level output
voltage
I
OH
= −100
µ
A
Full range 4.82 4.82 V
VOH
voltage
IOH = −400 µA
25°C 4.7 4.85 4.7 4.85
V
I
OH
= −400
µ
A
Full range 4.6 4.6
VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01
Low-level output
VIC = 2.5 V,
IOL = 500 µA
25°C 0.09 0.15 0.09 0.15
V
OL
Low-level output
voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
voltage
VIC = 2.5 V,
IOL = 1 A
25°C 0.2 0.3 0.2 0.3
V
V
IC
= 2.5 V,
I
OL
= 1
A
Full range 0.3 0.3
Large-signal differential
VIC = 2.5 V,
RL = 50 k
25°C 80 170 80 170
A
VD
Large-signal differential
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 50 k
Full range 55 55 V/mV
AVD
voltage amplification
V
O
= 1 V to 4 V
RL = 1 M25°C 550 550
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, N package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 240 240
CMRR
Common-mode rejection
VIC = 0 to 2.7 V, VO = 2.5 V,
25°C 70 83 70 83
dB
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V, VO = 2.5 V,
R
S
= 50 Full range 70 70
dB
kSVR
Supply voltage rejection V
DD
= 4.4 V to 8 V, 25°C 80 95 80 95
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
Full range is − 40°C to 125°C.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2264I TLV2264AI
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 2.5 V,
No load
25°C 0.8 1 0.8 1
mA
I
DD
Supply current
(four amplifiers)
V
O
= 2.5 V,
No load
Full range 1 1
mA
Full range is − 40°C to 125°C.
TLV2264I operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2264I TLV2264AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
MIN TYP MAX MIN TYP MAX
UNIT
25°C
0.35
0.55
0.35
0.55
Slew rate at unity
VO = 1.4 V to 2.6 V,
RL = 50 k,
25°C 0.35 0.55 0.35 0.55
SR Slew rate at unity
gain
VO = 1.4 V to 2.6 V,
CL = 100 pF
RL = 50 k
,
Full
0.3
0.3
V/µs
SR
gain
CL = 100 pF
Full
range 0.3 0.3
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 40 40
nV/Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.7 0.7
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.3 1.3 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.017% 0.017%
THD + N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.03% 0.03%
Gain-bandwidth
f = 50 kHz,
RL = 50 k
,
25°C
0.71
0.71
MHz
Gain-bandwidth
product
f = 50 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.71 0.71 MHz
BOM
Maximum output-
VO(PP) = 2 V,
AV = 1,
25°C
185
185
kHz
BOM
Maximum output-
swing bandwidth
VO(PP) = 2 V,
R
L
= 50 k,
AV = 1,
C
L
= 100 pF25°C185 185 kHz
AV = −1,
To 0.1%
6.4
6.4
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
To 0.1%
25°C
6.4 6.4
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 50 k,
To 0.01%
25°C
14.1
14.1
µs
RL = 50 k,
CL = 100 pFTo 0.01% 14.1 14.1
φmPhase margin at
unity gain
RL = 50 k
,
CL = 100 pF
25°C 56°56°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is − 40°C to 125°C.
Referenced to 2.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TLV2262Q,
TLV2262M TLV2262AQ,
TLV2262AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4)
VDD± = ±1.5 V, VIC = 0,
VO = 0, RS = 50 25°C 0.003 0.003 µV/mo
IIO
Input offset current
OS
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
125°C 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
125°C 800 800
pA
0
0.3
0
0.3
25°C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
voltage range
RS = 50
|VIO |≤5 mV
25 C
to
2
to
2.2
to
2
to
2.2
V
V
ICR
Common-mode input
voltage range
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
1.7
to
1.7
IOH = −20 µA 25°C 2.99 2.99
High-level output
IOH = −100 µA
25°C 2.85 2.85
V
OH
High-level output
voltage
I
OH
= −100
µ
A
Full range 2.82 2.82 V
VOH
voltage
IOH = −400 µA
25°C 2.7 2.7
V
I
OH
= −400
µ
A
Full range 2.55 2.55
VIC = 1.5 V, IOL = 50 µA 25°C 10 10
Low-level output
VIC = 1.5 V,
IOL = 500 µA
25°C 100 150 100 150
V
OL
Low-level output
voltage
V
IC
= 1.5 V,
I
OL
= 500
µ
A
Full range 165 165 mV
VOL
voltage
VIC = 1.5 V,
IOL = 1 A
25°C 200 300 200 300
mV
V
IC
= 1.5 V,
I
OL
= 1
A
Full range 300 300
Large-signal differential
VIC = 1.5 V,
RL = 50 k
25°C 60 100 60 100
A
VD
Large-signal differential
voltage amplification
VIC = 1.5 V,
VO = 1 V to 2 V
R
L
= 50 k
Full range 25 25 V/mV
AVD
voltage amplification
VO = 1 V to 2 V
RL = 1 M25°C 100 100
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, P package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 270 270
CMRR
Common-mode
rejection ratio
V
IC
= 0 to 1.7 V,
V = 1.5 V, R = 50
25°C 65 75 65 77
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
VO = 1.5 V, RS = 50 Full range 60 60
dB
kSVR
Supply voltage rejection
ratio ( V/V)
V
DD
= 2.7 V to 8 V,
V = V /2, No load
25°C 80 95 80 100
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)
VDD = 2.7 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2262Q,
TLV2262M TLV2262AQ,
TLV2262AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 1.5 V,
No load
25°C 400 500 400 500
µA
I
DD
Supply current
V
O
= 1.5 V,
No load
Full range 500 500 µ
A
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2262Q and TLV2262M operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2262Q,
TLV2262M TLV2262AQ,
TLV2262AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VO = 0.5 V to 1.7 V,
RL = 50 k,
25°C0.35 0.55 0.35 0.55
SR Slew rate at unity gain VO = 0.5 V to 1.7 V,
CL = 100 pF
R
L
= 50 k
,
Full
0.25
0.25
V/µs
SR
Slew rate at unity gain
CL = 100 pF
Full
range 0.25 0.25
V/µs
Vn
Equivalent input noise
f = 10 Hz 25°C 43 43
nV/Hz
Vn
Equivalent input noise
voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input noise
f = 0.1 Hz to 1 Hz 25°C 0.6 0.6
V
VN(PP)
equivalent input noise
voltage f = 0.1 Hz to 10 Hz 25°C 1 1 µV
InEquivalent input noise
current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.03% 0.03%
THD + N
Total harmonic
distortion plus noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.05% 0.05%
Gain-bandwidth
f = 1 kHz,
RL = 50 k
,
25°C
0.67
0.67
MHz
Gain-bandwidth
product
f = 1 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.67 0.67 MHz
BOM
Maximum
output-swing
VO(PP) = 1 V,
AV = 1,
25°C
395
395
kHz
BOM
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 k,
AV = 1,
CL = 100 pF25°C395 395 kHz
AV = −1,
To 0.1%
5.6
5.6
ts
Settling time
AV = −1,
Step = 1 V to 2 V,
To 0.1%
25°C
5.6 5.6
s
tsSettling time
Step = 1 V to 2 V,
R
L
= 50 k,
To 0.01%
25°C
12.5
12.5
µs
RL = 50 k,
CL = 100 pFTo 0.01% 12.5 12.5
φmPhase margin at unity
gain
RL = 50 k
,
CL = 100 pF
25°C 55°55°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TLV2262Q,
TLV2262M TLV2262AQ,
TLV2262AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient of
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient of
input offset voltage
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift (see Note 4) VDD± = ±2.5 V, VIC = 0,
VO = 0, RS = 50
25°C 0.003 0.003 µV/mo
IIO
Input offset current
VO = 0, RS = 50
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
125°C 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
125°C 800 800
pA
0
0.3
0
0.3
25°C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
|VIO |≤5 mV,
RS = 50
25 C
to
4
to
4.2
to
4
to
4.2
V
V
ICR
Common-mode input
voltage range |
V
IO
| ≤
5 mV,
R
S
= 50
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
3.5
to
3.5
IOH = −20 µA 25°C 4.99 4.99
IOH = −100 µA
25°C 4.85 4.94 4.85 4.94
V
OH
High-level output voltage
I
OH
= −100
µ
A
Full range 4.82 4.82 V
VOH
High-level output voltage
IOH = −400 µA
25°C 4.7 4.85 4.7 4.85
V
I
OH
= −400
µ
A
Full range 4.5 4.5
VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01
VIC = 2.5 V,
IOL = 500 µA
25°C 0.09 0.15 0.09 0.15
V
OL
Low-level output voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
Low-level output voltage
VIC = 2.5 V,
IOL = 1 A
25°C 0.2 0.3 0.2 0.3
V
V
IC
= 2.5 V,
I
OL
= 1
A
Full range 0.3 0.3
Large-signal differential
VIC = 2.5 V,
RL = 50 k
25°C 80 170 80 170
A
VD
Large-signal differential
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 50 k
Full range 50 50 V/mV
AVD
voltage amplification
VO = 1 V to 4 V
RL = 1 M25°C 550 550
V/mV
ri(d) Differential input resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, P package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 240 240
CMRR
Common-mode rejection
VIC = 0 to 2.7 V,
25°C 70 83 70 83
dB
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V,
VO = 2.5 V, RS = 50 Full range 70 70
dB
kSVR
Supply voltage rejection
VDD = 4.4 V to 8 V,
25°C 80 95 80 95
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2262Q,
TLV2262M TLV2262AQ,
TLV2262AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 2.5 V,
No load
25°C 400 500 400 500
µA
I
DD
Supply current
V
O
= 2.5 V,
No load
Full range 500 500 µ
A
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2262Q and TLV2262M operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2262Q,
TLV2262M TLV2262AQ,
TLV2262AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at unity
VO = 0.5 V to 3.5 V,
RL = 50 k
25°C0.35 0.55 0.35 0.55
SR Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF
RL = 50 k
Full
0.25
0.25
V/µs
SR
gain
CL = 100 pF
Full
range 0.25 0.25
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 40 40
nV/Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.7 0.7
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.3 1.3 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.017% 0.017%
THD + N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.03% 0.03%
Gain-bandwidth
f = 50 kHz,
RL = 50 k
,
25°C
0.71
0.71
MHz
Gain-bandwidth
product
f = 50 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.71 0.71 MHz
BOM
Maximum
output-swing
VO(PP) = 2 V,
AV = 1,
25°C
185
185
kHz
BOM
output-swing
bandwidth
VO(PP) = 2 V,
RL = 50 k,
AV = 1,
CL = 100 pF25°C185 185 kHz
AV = −1,
To 0.1%
6.4
6.4
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
To 0.1%
25°C
6.4 6.4
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 50 k,
To 0.01%
25°C
14.1
14.1
µs
RL = 50 k,
CL = 100 pFTo 0.01% 14.1 14.1
φmPhase margin at
unity gain
RL = 50 k
,
CL = 100 pF
25°C 56°56°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TLV2264Q,
TLV2264M TLV2264AQ,
TLV2264AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
V = 1.5 V,
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4)
VDD± = ±1.5 V,
VIC = 0,
VO = 0,
RS = 50
25°C 0.003 0.003 µV/mo
IIO
Input offset current
O
R
S
= 50
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
125°C 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
125°C 800 800
pA
0
0.3
0
0.3
25
°
C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
RS = 50
|VIO |≤5 mV
25 C
to
2
to
2.2
to
2
to
2.2
V
V
ICR
Common-mode input
voltage range
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
1.7
to
1.7
IOH = −20 µA 25°C 2.99 2.99
High-level output
IOH = −100 µA
25°C 2.85 2.85
V
OH
High-level output
voltage
I
OH
= −100
µ
A
Full range 2.82 2.82 V
VOH
voltage
IOH = −400 µA
25°C 2.7 2.7
V
I
OH
= −400
µ
A
Full range 2.6 2.6
VIC = 1.5 V, IOL = 50 µA 25°C 10 10
Low-level output
VIC = 1.5 V,
IOL = 500 µA
25°C 100 150 100 150
V
OL
Low-level output
voltage
V
IC
= 1.5 V,
I
OL
= 500
µ
A
Full range 150 150 mV
VOL
voltage
VIC = 1.5 V,
IOL = 1 A
25°C 200 300 200 300
mV
V
IC
= 1.5 V,
I
OL
= 1
A
Full range 300 300
Large-signal differential
VIC = 1.5 V,
RL = 50 k
25°C 60 100 60 100
A
VD
Large-signal differential
voltage amplification
VIC = 1.5 V,
VO = 1 V to 2 V
R
L
= 50 k
Full range 25 25 V/mV
AVD
voltage amplification
V
O
= 1 V to 2 V
RL = 1 M25°C 100 100
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, N package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 270 270
CMRR
Common-mode rejection
VIC = 0 to 1.7 V, VO = 1.5 V,
25°C 65 75 65 77
dB
CMRR
Common-mode rejection
ratio
VIC = 0 to 1.7 V, VO = 1.5 V,
RS = 50 Full range 60 60
dB
kSVR
Supply voltage rejection
ratio ( V/V)
VDD = 2.7 V to 8 V, 25°C 80 95 80 100
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)VIC = VDD/2, No load Full range 80 80
dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2264Q,
TLV2264M TLV2264AQ,
TLV2264AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current (four
amplifiers)
VO = 1.5 V,
No load
25°C 0.8 1 0.8 1
mA
I
DD
Supply current (four
amplifiers)
V
O
= 1.5 V,
No load
Full range 1 1
mA
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2264Q and TLV2264M operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2264Q,
TLV2264M TLV2264AQ,
TLV2264AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
25°C
0.35
0.55
0.35
0.55
Slew rate at unity
VO = 0.5 V to 1.7 V,
RL = 50 k,
25°C 0.35 0.55 0.35 0.55
SR Slew rate at unity
gain
VO = 0.5 V to 1.7 V,
CL = 100 pF
RL = 50 k
,
Full
0.25
0.25
V/µs
SR
gain
CL = 100 pF
Full
range 0.25 0.25
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 43 43
nV/Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.6 0.6
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1 1 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.03% 0.03%
THD + N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.05% 0.05%
Gain-bandwidth
f = 1 kHz,
RL = 50 k
,
25°C
0.67
0.67
MHz
Gain-bandwidth
product
f = 1 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.67 0.67 MHz
BOM
Maximum output-
VO(PP) = 1 V,
AV = 1,
25°C
395
395
kHz
BOM
Maximum output-
swing bandwidth
VO(PP) = 1 V,
R
L
= 50 k,
AV = 1,
C
L
= 100 pF25°C395 395 kHz
AV = −1,
To 0.1%
5.6
5.6
ts
Settling time
AV = −1,
Step = 1 V to 2 V,
To 0.1%
25°C
5.6 5.6
s
tsSettling time
Step = 1 V to 2 V,
R
L
= 50 k,
To 0.01%
25°C
12.5
12.5
µs
RL = 50 k,
CL = 100 pFTo 0.01% 12.5 12.5
φmPhase margin at
unity gain R
L
= 50 k, C
L
= 100 pF25°C 55°55°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TLV2264Q,
TLV2264M TLV2264AQ,
TLV2264AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient of
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient of
input offset voltage
V = 2.5 V,
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4)
VDD± = ±2.5 V,
VIC = 0,
VO = 0,
RS = 50
25°C 0.003 0.003 µV/mo
IIO
Input offset current
R
S
= 50
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
125°C 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
125°C 800 800
pA
0
0.3
0
0.3
25°C
0
to
0.3
to
0
to
0.3
to
VICR
Common-mode input
|VIO |≤5 mV,
RS = 50
25 C
to
4
to
4.2
to
4
to
4.2
V
V
ICR
Common-mode input
voltage range |
V
IO
| ≤
5 mV,
R
S
= 50
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
3.5
to
3.5
IOH = −20 µA 25°C 4.99 4.99
IOH = −100 µA
25°C 4.85 4.94 4.85 4.94
V
OH
High-level output voltage
I
OH
= −100
µ
A
Full range 4.82 4.82 V
VOH
High-level output voltage
IOH = −400 µA
25°C 4.7 4.85 4.7 4.85
V
I
OH
= −400
µ
A
Full range 4.5 4.5
VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01
VIC = 2.5 V,
IOL = 500 µA
25°C 0.09 0.15 0.09 0.15
V
OL
Low-level output voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
Low-level output voltage
VIC = 2.5 V,
IOL = 1 A
25°C 0.2 0.3 0.2 0.3
V
V
IC
= 2.5 V,
I
OL
= 1
A
Full range 0.3 0.3
Large-signal differential
VIC = 2.5 V,
RL = 50 k
25°C 80 170 80 170
A
VD
Large-signal differential
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 50 k
Full range 50 50 V/mV
AVD
voltage amplification
V
O
= 1 V to 4 V
RL = 1 M25°C 550 550
V/mV
ri(d) Differential input
resistance 25°C 1012 1012
ri(c) Common-mode input
resistance 25°C 1012 1012
ci(c) Common-mode input
capacitance f = 10 kHz, N package 25°C 8 8 pF
zoClosed-loop output
impedance f = 100 kHz, AV = 10 25°C 240 240
CMRR
Common-mode rejection
VIC = 0 to 2.7 V, VO = 2.5 V,
25°C 70 83 70 83
dB
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V, VO = 2.5 V,
R
S
= 50 Full range 70 70
dB
kSVR
Supply voltage rejection VDD = 4.4 V to 8 V, 25°C 80 95 80 95
dB
k
SVR
Supply voltage rejection
ratio (VDD/VIO)VIC = VDD/2, No load Full range 80 80
dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
21
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA
TLV2264Q,
TLV2264M TLV2264AQ,
TLV2264AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current (four
VO = 2.5 V,
No load
25°C 0.8 1 0.8 1
mA
I
DD
Supply current (four
amplifiers)
V
O
= 2.5 V,
No load
Full range 1 1
mA
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2264Q and TLV2264M operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2264Q,
TLV2264M TLV2264AQ,
TLV2264AM
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX MIN TYP MAX
UNIT
25°C
0.35
0.55
0.35
0.55
Slew rate at unity
VO = 0.5 V to 3.5 V,
RL = 50 k,
25°C 0.35 0.55 0.35 0.55
SR Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF
RL = 50 k
,
Full
0.25
0.25
V/µs
SR
gain
CL = 100 pF
Full
range 0.25 0.25
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 40 40
nV/Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 12 12
nV/Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.7 0.7
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.3 1.3 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/Hz
THD + N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.017% 0.017%
THD + N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kAV = 10 25°C0.03% 0.03%
Gain-bandwidth
f = 50 kHz,
RL = 50 k
,
25°C
0.71
0.71
MHz
Gain-bandwidth
product
f = 50 kHz,
C
L
= 100 pF
RL = 50 k,
25°C 0.71 0.71 MHz
BOM
Maximum
output-swing
VO(PP) = 2 V,
AV = 1,
25°C
185
185
kHz
BOM
output-swing
bandwidth
VO(PP) = 2 V,
RL = 50 k,
AV = 1,
CL = 100 pF25°C185 185 kHz
AV = −1,
To 0.1%
6.4
6.4
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
To 0.1%
25°C
6.4 6.4
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 50 k,
To 0.01%
25°C
14.1
14.1
µs
RL = 50 k,
CL = 100 pFTo 0.01% 14.1 14.1
φmPhase margin at
unity gain
RL = 50 k
,
CL = 100 pF
25°C 56°56°
Gain margin
RL = 50 k,
CL = 100 pF
25°C11 11 dB
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
22 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
VIO Input offset voltage
Distribution
vs Common-mode voltage
6, 7
αVIO Input offset voltage temperature coefficient Distribution 8 − 11
IIB/IIO Input bias and input offset currents vs Free-air temperature 12
VI
Input voltage
vs Supply voltage
VIInput voltage
vs Supply voltage
vs Free-air temperature
14
VOH High-level output voltage vs High-level output current 15, 18
VOL Low-level output voltage vs Low-level output current 16, 17, 19
VO(PP) Maximum peak-to-peak output voltage vs Frequency 20
IOS
Short-circuit output current
vs Supply voltage
IOS Short-circuit output current
vs Supply voltage
vs Free-air temperature
22
VID Differential input voltage vs Output voltage 23, 24
AVD Differential voltage amplification vs Load resistance 25
AVD
Large-signal differential voltage amplification
vs Frequency
AVD Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
28, 29
zoOutput impedance vs Frequency 30, 31
CMRR
Common-mode rejection ratio
vs Frequency
CMRR Common-mode rejection ratio
vs Frequency
vs Free-air temperature
33
kSVR
Supply-voltage rejection ratio
vs Frequency
kSVR Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
36, 37
IDD Supply current vs Free-air temperature 38, 39
SR
Slew rate
vs Load capacitance
SR Slew rate
vs Load capacitance
vs Free-air temperature
41
VOInverting large-signal pulse response 42, 43
VOVoltage-follower large-signal pulse response 44, 45
VOInverting small-signal pulse response 46, 47
VOVoltage-follower small-signal pulse response 48, 49
VnEquivalent input noise voltage vs Frequency 50, 51
Input noise voltage Over a 10-second period 52
Integrated noise voltage vs Frequency 53
THD + N Total harmonic distortion plus noise vs Frequency 54
Gain-bandwidth product
vs Supply voltage
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
56
φm
Phase margin
vs Frequency
φmPhase margin
vs Frequency
vs Load capacitance
57
Gain margin vs Load capacitance 58
B1Unity-gain bandwidth vs Load capacitance 59
Overestimation of phase margin vs Load capacitance 60
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
23
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
9
6
3
0
Precentage of Amplifiers − %
12
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
15
VIO − Input Offset Voltage − mV
1.6 0.8 0 0.8 1.6
841 Amplifiers From 2 Wafer Lots
VDD± = ± 1.5 V
TA = 25°C
Figure 3
9
6
3
0
Precentage of Amplifiers − %
12
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
15
VIO − Input Offset Voltage − mV
1.6 0.8 0 0.8 1.6
841 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
TA = 25°C
Figure 4
12
8
4
0
Percentage of Amplifiers − %
16
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
20
1.6 0.8 0 0.8 1.6
2272 Amplifiers From 2 Wafer Lots
VDD±= ±1.5 V
TA = 25°C
VIO − Input Offset Voltage − mV
Figure 5
12
8
4
0
Percentage of Amplifiers − %
16
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
20
1.6 0.8 0 0.8 1.6
2272 Amplifiers From 2 Wafer Lots
VDD±= ±2.5 V
TA = 25°C
VIO − Input Offset Voltage − mV
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
24 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
0
− Input Offset Voltage − mV
0.5
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.5
−1
−1 −0.5 0 0.5 1 1.5 2 2.5 3
VDD = 3 V
RS = 50
TA = 25°C
ÁÁ
ÁÁ
VIO
VIC − Common-Mode Input Voltage − V
Figure 7
0
− Input Offset Voltage − mV
0.5
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.5
−1
−1 0 512 43
VDD = 5 V
RS = 50
TA = 25°C
ÁÁ
ÁÁ
VIO
VIC − Common-Mode Input Voltage − V
Figure 8
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
15
10
5
0
Percentage of Amplifiers − %
20
25
30
−5 −4 −3 −2 −1 0 1 2 3 4 5
128 Amplifiers From 2 Wafer Lots
VDD± = ±1.5 V
P Package
TA = 25°C to 85°C
αVIO − Temperature Coefficient µV/°C
Figure 9
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
15
10
5
0
Percentage of Amplifiers − %
20
25
30
−5 −4 −3 −2 −1 0 1 2 3 4 5
128 Amplifiers From 2 Wafer Lots
VDD± = ±2.5 V
P Package
TA = 25°C to 85°C
αVIO − Temperature Coefficient µV/°C
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
25
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
Percentage of Amplifiers − %
10
5
30
0
20
15
25
35
−5 −4 −3 −2 −1 0 1 2 3 4 5
128 Amplifiers From
2 Wafer Lots
VDD± = ±1.5 V
N Package
TA = 25°C to 125°C
αVIO − Temperature Coefficient
of Input Offset Voltage − µV/°C
Figure 11
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
Percentage of Amplifiers − %
10
5
30
0
20
15
25
35
−5 −4 −3 −2 −1 0 1 2 3 4 5
128 Amplifiers From
2 Wafer Lots
VDD± = ±2.5 V
N Package
TA = 25°C to 125°C
αVIO − Temperature Coefficient
of Input Offset Voltage − µV/°C
Figure 12
10
5
30
025 45 65 85
IIB and IIO − Input Bias and Input Offset Currents − pA
20
15
25
INPUT BIAS AND INPUT OFFSET CURRENTS
vs
FREE-AIR TEMPERATURE
35
105 125
IIB
IIO
VDD± = ±2.5 V
VIC = 0
VO = 0
RS = 50
TA − Free-Air Temperature − °C
ÁÁ
ÁÁ
IIB IIO
Figure 13
0
2
1 1.5 2 2.5
− Input Voltage − V
1
0.5
1.5
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
2.5
3 3.5 4
0.5
−1
1.5
−2
2.5
RS = 50
TA = 25°C
| VIO | 5 mV
ÁÁ
ÁÁ
VI
|VDD±| − Supply Voltage − V
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
26 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
2
1
0
− Input Voltage − V
3
4
INPUT VOLTAGE†‡
vs
FREE-AIR TEMPERATURE
5
−1
55 35 15 5 25 45 65 85
| VIO | 5 mV
VDD = 5 V
ÁÁ
VI
TA − Free-Air Temperature − °C105 125
Figure 15
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
| IOH | − High-Level Output Current − µA
2
1
0.5
00 500 1000
3
3.5
4
1500 2000
2.5
1.5
TA = −55°C
VDD = 3 V
TA = 85°C
TA = −40°C
TA = 125°C
TA = 25°C
Figure 16
0.6
0.4
0.2
00123
− Low-Level Output Voltage − V
0.8
1
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.2
45
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
VDD = 3 V
TA = 25°C
VIC = 0
VIC = 0.75 V
VIC = 1.5 V
Figure 17
− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOL
0.4
0.2
1.2
0012 3
0.8
0.6
1
1.4
45
TA = 85°C
TA = − 40°C
TA = 25°C
VDD = 3 V
VIC = 1.5 V
TA = − 55°C
TA = 125°C
IOL − Low-Level Output Current − mA
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
27
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOH
| IOH | − High-Level Output Current − µA
3
2
1
00 500 1000
4
5
6
1500 2000 2500 3000
TA = 25°C
TA = 85°C
VDD = 5 V
TA = −40°C
TA = 125°C
TA = −55°C
Figure 19
0.6
0.4
0.2
001 2 3
− Low-Level Output Voltage − V
1
1.2
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
1.4
456
0.8
VDD = 5 V
VIC = 2.5 V
TA = −40°C
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
TA = 85°C
TA = 25°C
TA = 125°CTA = −55°C
Figure 20
4
2
1
5
3
− Maximum Peak-to-Peak Output Voltage − V
f − Frequency − Hz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
0103104105106
ÁÁ
ÁÁ
ÁÁ
VO(PP)
RI = 10 k
TA = 25°C
VDD = 5 V
VDD = 3 V
Figure 21
6
2
0
2345
− Short-Circuit Output Current − mA
8
10
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
12
678
4
−2
IOS
VDD − Supply Voltage − V
VID = −100 mV
VID = 100 mV
VIC = VDD/2
TA = 25°C
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
28 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
− Short-Circuit Output Current − mA
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
IOS
TA − Free-Air Temperature − °C
4
2
6
10
12
8
0
−4 50 25 0 25 50 75 100
−2
VO = 2.5 V
VDD = 5 V
VID = −100 mV
VID = 100 mV
75 125
Figure 23
0
800
0 0.5 1 1.5
− Differential Input Voltage −
400
200
600
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
1000
2 2.5 3
200
400
600
800
1000
VDD = 3 V
RI = 50 k
VIC = 1.5 V
TA = 25°C
VID Vµ
VO − Output Voltage − V
Figure 24
0
800
01 3
− Differential Input Voltage −
400
200
600
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
1000
245
200
400
600
800
1000
VID Vµ
VO − Output Voltage − V
VDD = 5 V
VIC = 2.5 V
RL = 50 k
TA = 25°C
Figure 25
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
RL − Load Resistance − k
− Differential Voltage Amplification − V/mV
ÁÁ
ÁÁ
AVD
100
10
1
1000
VDD = 3 V
VDD = 5 V
VO(PP) = 2 V
TA = 25°C
103104105106
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
29
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
om − Phase Margin
φm
20
f − Frequency − Hz
80
60
40
0
−20
−40103104105106107
180°
135°
90°
45°
0°
−45°
−90°
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Gain
Phase Margin
VDD = 5 V
CL= 100 pF
TA = 25°C
Figure 26
om − Phase Margin
φm
20
f − Frequency − Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
40
0
−20
−40103104105106107
180°
135°
90°
45°
0°
−45°
−90°
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Gain
Phase Margin
VDD = 3 V
CL = 100 pF
TA = 25°C
Figure 27
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
30 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
10
100
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
1000
50 25 0 25 50 75 100
TA − Free-Air Temperature − °C
− Large-Signal Differential Voltage
AVD Amplification − V/mV
RL = 1 M
RL = 50 k
RL = 10 k
VDD = 3 V
VIC = 1.5 V
VO = 0.5 V to 2.5 V
125−75
Figure 29
10
100
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
1000
50 25 0 25 50 75 100
TA − Free-Air Temperature − °C
− Large-Signal Differential Voltage
AVD Amplification − V/mV
RL = 1 M
10000
125−75
RL = 50 k
RL = 10 k
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
Figure 30
0.1
1
− Output Impedance −
f− Frequency − Hz
OUTPUT IMPEDANCE
vs
FREQUENCY
10
100
1000
102103104105
VDD = 3 V
TA = 25°C
AV = 100
AV = 10
AV = 1
zo
Figure 31
0.1
1
− Output Impedance −
f− Frequency − Hz
OUTPUT IMPEDANCE
vs
FREQUENCY
10
100
1000
10210310410
5
VDD = 5 V
TA = 25°C
AV = 100
AV = 10
AV = 1
zo
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
31
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
80
40
20
0
100
60
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
101102103104105106
VDD = 5 V
VIC = 2.5 V
VDD = 5 V
VIC = 1.5 V
TA = 25°C
Figure 33
80
78
74
72
70
88
76
CMMR − Common-Mode Rejection Ratio − dB
84
82
86
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
90
− 50 − 25 0 25 50 75 100
TA − Free-Air Temperature − °C125− 75
VDD = 5 V
VDD = 3 V
Figure 34
60
40
20
100
− Supply-Voltage Rejection Ratio − dB
80
f − Frequency − Hz
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
0
−20
kSVR
kSVR+
101102103104105106
ÁÁ
ÁÁ
kSVR
VDD = 3 V
TA = 25°C
Figure 35
60
40
20
100
− Supply-Voltage Rejection Ratio − dB
80
f − Frequency − Hz
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
0
−20
kSVR+
101102103104105106
ÁÁ
ÁÁ
ÁÁ
kSVR
kSVR
VDD = 5 V
TA = 25°C
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
32 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
100
95
90
− Supply-Voltage Rejection Ratio − dB
105
110
50 25 0 25 50 75 100
ÁÁ
ÁÁ
kSVR
TA − Free-Air Temperature − °C
VDD = 2.7 V to 8 V
VIC = VO = VDD /2
125−75
TLV2262
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
Figure 37
100
95
90
− Supply-Voltage Rejection Ratio − dB
105
110
50 25 0 25 50 75 100
ÁÁ
ÁÁ
ÁÁ
kSVR
TA − Free-Air Temperature − °C
VDD = 2.7 V to 8 V
VIC = VO = VDD /2
125−75
TLV2264
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
Figure 38
400
300
200
500
600
50 25 0 25 50 75 100
− Supply Current − Aµ
ÁÁ
ÁÁ
IDD
TA − Free-Air Temperature − °C
VDD = 5 V
VO = 2.5 V
VDD = 3 V
VO = 1.5 V
125−75
TLV2262
SUPPLY CURRENT†‡
vs
FREE-AIR TEMPERATURE
Figure 39
800
600
400
1000
1200
50 25 0 25 50 75 100
− Supply Current − Aµ
ÁÁ
ÁÁ
ÁÁ
IDD
TA − Free-Air Temperature − °C
VDD = 5 V
VO = 2.5 V
VDD = 3 V
VO = 1.5 V
125−75
TLV2264
SUPPLY CURRENT†‡
vs
FREE-AIR TEMPERATURE
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
33
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 40
0.8
0.4
0.2
0
1
0.6
SR − Slew Rate −
SLEW RATE
vs
LOAD CAPACITANCE
SR
SR+
VDD = 5 V
AV = −1
TA = 25°C
101102103104
CL − Load Capacitance − pF
sµ
V/
Figure 41
0.6
0.4
0.2
0
SR − Slew Rate −
0.8
1
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
1.2
50 25 0 25 50 75 100
SR
SR+
sµ
V/
TA − Free-Air Temperature − °C
VDD = 5 V
RL = 50 k
CL = 100 pF
AV = 1
125−75
Figure 42
1.5
1
0.5
0024681012
− Output Voltage − V
2
2.5
INVERTING LARGE-SIGNAL PULSE
RESPONSE
3
14 16 18 20
VO
t − Time − µs
AV = −1
TA = 25°C
VDD = 3 V
RL = 50 k
CL = 100 pF
Figure 43
2
1
0024681012
3
4
5
14 16 18 20
INVERTING LARGE-SIGNAL PULSE
RESPONSE
t − Time − µs
− Output Voltage − V
VO
AV = −1
TA = 25°C
VDD = 5 V
RL = 50 k
CL = 100 pF
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
34 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 44
1.5
1
0.5
0024681012
2
2.5
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
3
14 16 18 20
− Output Voltage − V
VO
t − Time − µs
AV = −1
TA = 25°C
VDD = 3 V
RL = 50 k
CL = 100 pF
Figure 45
2
1
0024681012
3
4
5
14 16 18 20
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
− Output Voltage − V
VO
t − Time − µs
VDD = 5 V
RL = 50 k
CL = 100 pF
AV = −1
TA = 25°C
Figure 46
0.7
0.65
0.9
0.60 2 4 6 8 10 12
0.8
0.75
0.85
INVERTING SMALL-SIGNAL
PULSE RESPONSE
0.95
14 16 18 20
VDD = 3 V
RL = 50 k
CL = 100 pF
− Output Voltage − V
VO
t − Time − µs
AV = − 1
TA = 25°C
Figure 47
2.5
2.45
2.4 0 2 4 6 8 10 12
VO − Output Voltage − V
2.55
2.6
INVERTING SMALL-SIGNAL
PULSE RESPONSE
2.65
14 16 18 20
VO
VDD = 5 V
RL = 50 k
CL = 100 pF
AV = −1
TA = 25°C
t − Time − µs
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
35
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 48
0.8
0.75
0.7 024681012
0.85
0.9
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
0.95
14 16 18 20
VDD = 3 V
RL = 50 k
CL = 100 pF
VO − Output Voltage − V
VO
t − Time − µs
AV = 1
TA = 25°C
Figure 49
2.5
2.45
2.4 0 2 4 6 8 10 12
2.55
2.6
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
2.65
14 16 18 20
VDD = 5 V
RL = 50 k
CL = 100 pF
AV = 1
TA = 25°C
VO − Output Voltage − V
VO
t − Time − µs
Figure 50
40
30
20
0
60
− Equivalent Input Noise Voltage −
50
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
10
101102103104
VDD = 3 V
RS = 20
TA = 25°C
VnnV/ Hz
Figure 51
40
30
20
0
60
− Equivalent Input Noise Voltage −
50
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
10
101102103104
VDD = 5 V
RS = 20
TA = 25°C
VnnV/ Hz
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
36 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 52
0
0246
Input Noise Voltage − nV
250
750
t − Time − s
INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD
1000
810
500
250
500
750
1000
VDD = 5 V
f = 0.1 Hz
to 10 Hz
TA = 25°C
Figure 53
0.1
Integrated Noise Voltage −
f − Frequency − Hz
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
1
10
100
110
1102103104105
Vµ
Calculated Using Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA = 25°C
Figure 54
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10−1
10−2
10−3
101102103104104
AV = 100
AV = 10
AV = 1
VDD = 5 V
RL = 50 k
TA = 25°C
Figure 55
Gain-Bandwidth Product − kHz
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
820
780
740
700 0235
860
900
78
146
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
37
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 56
Gain-Bandwidth Product − kHz
GAIN-BANDWIDTH PRODUCT†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
800
600
400
1000
1200
50 25 0 25 50 10075
VDD = 5 V
f = 10 kHz
CL = 100 pF
75 125
Figure 57
om − Phase Margin
PHASE MARGIN
vs
LOAD CAPACITANCE
10 102103104
CL − Load Capacitance − pF
m
φ
75°
60°
45°
30°
15°
0°
Rnull = 50
Rnull = 100
TA = 25°C
Rnull = 20
Rnull = 10
50 k
50 k
VDD/GND
VDD+ Rnull
CL
VI+
Rnull = 0
Figure 58
20
10
5
0
15
Gain Margin − dB
GAIN MARGIN
vs
LOAD CAPACITANCE
10 102103104
CL − Load Capacitance − pF
Rnull = 20
RL = 50 k
AV = 1
TA = 25°C
Rnull = 0
Rnull = 10
Rnull = 100
Rnull = 50
Figure 59
600
400
200
− Unity-Gain Bandwidth − kHz
800
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
1000
10 10210310
4
CL − Load Capacitance − pF
ÁÁ
ÁÁ
B1
TA = 25°C
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
38 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Overestimation of Phase Margin
OVERESTIMATION OF PHASE MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
10°
8°
6°
4°
2°
010 102103104
Rnull = 100
Rnull = 50
Rnull = 20
12°
14°
Rnull = 10
TA = 25°C
See application information
Figure 60
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
39
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51
and Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 61) improves the gain and phase margins
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of
10 , 20 , 50 , and 100 . The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation (1) can be used.
∆θm1 +tan–1 ǒ2×π×UGBW×Rnull ×CLǓ
∆θm1 +improvement in phase margin
UGBW +unity-gain bandwidth frequency
Rnull +output series resistance
CL+load capacitance
(1)
Where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To
use equation 1, UGBW must be approximated from Figure 53.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
F+1
1)gm×Rnull
F+factor reducing frequency of pole
gm+small-signal output transconductance (typically 4.83 ×10–3mhos)
Rnull +output series resistance
(2)
Where :
For the TLV226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with CL: at CL = 10 pF, use 70 MHz, at CL = 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result o f this equation can be subtracted from the result of the equation 1 to better approximate the improvement
in phase margin.
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
40 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads (continued)
∆θm2 +tan–1ȧ
ȱ
ȲUGBW
ǒF×P2Ǔȧ
ȳ
ȴ tan–1 ǒUGBW
P2Ǔ
∆θm2 +reduction in phase margin
UGBW +unity-gain bandwidth frequency
F+factor from equation (2)
P2+unadjusted pole (70 MHz @ 10 pF, 7 MHz @100 pF, etc.)
(3)
Where :
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
50 k
50 k
VDD/GND
VDD+
Rnull
CL
VI+
Figure 61. Series-Resistance Circuit
 
  
 
SLOS186C − FEBRUAR Y 1997 − REVISED AUGUST 2006
41
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using
the TLV226x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
+
+
+
+
+
+
+
+
.SUBCKT TLV226x 1 2 3 4 5
C1 11 12 5.5E−12
C2 6 7 20.00E−12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 43DX
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY (5) VB VC VE VLP
+ VLN 0 8.84E6 −10E6 10E6 10E6 −10E6
GA 6 0 11 12 62.83E−6
GCM 0 6 10 99 12.34E−9
ISS 3 10 DC 11.05E−6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 60 11 15.92E3
RD2 60 12 15.92E3
R01 8 5 135
R02 7 99 135
RP 3 4 15.87E3
RSS 10 99 18.18E6
VAD 60 4 −.5
VB 9 0 DC 0
VC 3 53 DC .615
VE 54 4 DC .615
VLIM 7 8 DC 0
VLP 91 0 DC 1
VLN 0 92 DC 5.1
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=325E−6
+ VTO=−.08)
.ENDS
VCC+
RP
IN 2
IN+ 1
VCC
VAD
RD1
11
J1 J2
10
RSS ISS
3
12
RD2
60
VE
54 DE
DP
VC
DC
4
C1
53
R2 6
9
EGND
VB
FB
C2
GCM GA VLIM
8
5RO1
RO2
HLIM
90 DLP
91
DLN
92
VLNVLP
99
7
Figure 62. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9550401Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9550401QHA ACTIVE CFP U 10 1 TBD Call TI Call TI
5962-9550401QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
5962-9550402Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9550402QCA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-9550402QDA ACTIVE CFP W 14 1 TBD Call TI Call TI
5962-9550403Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9550403QHA ACTIVE CFP U 10 1 TBD Call TI Call TI
5962-9550403QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
5962-9550404Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9550404QCA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-9550404QDA ACTIVE CFP W 14 1 TBD Call TI Call TI
TLV2262AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2262AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2262AIPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TLV2262AIPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AIPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2262AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLV2262AMUB ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type
TLV2262AQD ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2262AQDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262AQDR ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2262AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2262IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2262IPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2262MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLV2262MUB ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type
TLV2262QD ACTIVE SOIC D 8 TBD Call TI Call TI
TLV2262QDG4 ACTIVE SOIC D 8 1500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2262QDR ACTIVE SOIC D 8 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2262QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2264AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2264AIPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
TLV2264AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AIPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2264AMJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
TLV2264AMWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
TLV2264AQD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AQDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264AQDR ACTIVE SOIC D 14 TBD Call TI Call TI
TLV2264AQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2264IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2264INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2264IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLV2264MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
TLV2264MWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
TLV2264QD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264QDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2264QDR ACTIVE SOIC D 14 TBD Call TI Call TI
TLV2264QDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 5
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2262, TLV2262A, TLV2262AM, TLV2262M, TLV2264, TLV2264A, TLV2264AM, TLV2264M :
Catalog: TLV2262A, TLV2262, TLV2264A, TLV2264
Automotive: TLV2262-Q1, TLV2262A-Q1, TLV2262A-Q1, TLV2262-Q1, TLV2264-Q1, TLV2264A-Q1, TLV2264A-Q1, TLV2264-Q1
Military: TLV2262M, TLV2262AM, TLV2264M, TLV2264AM
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2262AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2262AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLV2262IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2262IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLV2264AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2264AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV2264IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2264IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2262AIDR SOIC D 8 2500 340.5 338.1 20.6
TLV2262AIPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLV2262IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2262IPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLV2264AIDR SOIC D 14 2500 333.2 345.9 28.6
TLV2264AIPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLV2264IDR SOIC D 14 2500 333.2 345.9 28.6
TLV2264IPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated