fax id: 5418 " CY7C4421V/4201V/4211V/4221V PRELIMINARY _CY7C4231V/4241V/4251V CYPRESS Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs io Features * 32-pin PLCC * High-speed, low-power, first-in, first-out (FIFO) Functional Description memories * 64x 9 (CY7C4421V) The CY7C42X1V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Alf * 256 x 9 (CY7C4201V) are 9 bits wide. Programmable features include Almost Full/Al- + 512 x 9 (CY7C4211V) most Empty flags. These FIFOs provide solutions for a wide 1K x9 (CY7C4221V)} variety of data buffering needs, including high-speed data ac- 2K x 9 (CY7C4231V) quisition, multiprocessor interfaces, and communications buff- 4K x 9 (CY7C4241V} ering. 8K x 9 (CY7C4251V} These FIFOs have 9-bit input and output ports that are con- igh- ti i trolled by separate clock and enable signals. The input port is ee speed 66-MHz operation (15 ns read/write cycle controlled by a free-running clock (WCLK) and two write-en- * Low power (leg = 20 mA) able pins (WENT, WEN2/[D). * 3.3V operation for low power consumption and easy When WENT is LOW and WEN2/CD is HIGH, data is written integration into low voltage systems into the FIFO on the rising edge of the WCLK signal. While 5V tolerant inputs Vij max= 5V WENT, WEN2/(D is held active, data is continually written into the FIFO on each WCLK cycle. The output part is controlled in * Fully asynchronous and simultaneous read and write a similar manner by a free-running read clock (RCLK) and two operation read-enable pins (RENT, REND). In addition, the CY7C42Xx1V . Empty, Full and Programmable Almost Empty and has an output enable pin (OE). The read (RCLK) and write imost Full status flags (WCLK} clocks may be tied together for single-clock operation * TTL compatible or the two clacks may be run independently for asynchronous * Output Enable (OE) pin read/write applications. Clock frequencies up to 66 MHz are * Independent read and write enable pins achievable. Center power and ground pins for reduced noise Depth expansion is possible using one enable input for system * Width Expansion Capability control, white the other enable is controlled by expansion logic * Space saving 32-pin 7mm x 7mm TQFP to direct the flow of data Logic Block Diagram bee Pin Configuration (NPUT EGISTER WCLKWENT WEN2/LD { FLAG r PROGRAM REGISTER WRITE CONTROL [7 Toit EF we TES a LOoaic > Rg f J eax . f WRITE READ POINTER 9 POINTER < : TOIT 1 RESET FS) Logic a 3 4 THREE-STATE OUTPUTREGISTER onset 7 rT | o- 8 RCLK RENT RERZ 42K1V-4 For the most recent information, visit the Cypress web site at www.cypress.com 2-19PRELIMINARY CYPRESS CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Functional Description (continued) The CY7C42X1V provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are program- mable to single word granuarity. The programmable flags default to Empty-7 and Full-7. The flags are synchronous, i.e., they change state relative to either the read clack (ROLK) or the write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at feast one cycle All configurations are fabricated using an advanced 0.65u P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Selection Guide Current (mA) CY7C4421V | CY7C4201V | CY7C4211V | CY7C4221V | CY7CA231V | CY7C4241V | CY7C4251V | Density 64x9 256 x 9 512x9 1Kx9 2K x9 4K x9 8K x9 | Maximum Ratings Output Current into Outputs (LOW)... ee 20 MA (Above which the useful life may be impaired. For user guide- eer MIL STD B89. Method 3018) sees >2001V lines, not tested.) Lateh-Up C Storage Temperature .ooocccccceecnenmmnne 65C to +180C atch-Up Current... cece centers cn eectee renee estn eaten >200 mA Ambient Temperature with Operating Range Power Applied 0.0... cc cescccsceseseeeeteeseereeneeenesees ~55C to +125C Supply Voltage to Ground Potential -0.5V to +5.0V Ambient ae A - lied 4 6 out rrrrrennneraeee ne AL . Range Temperature Vec oltage Applied to Outputs 7 3 3 in High Z State ncn -0.5Vt0+5.0V Commercial OC to +70C 3.3V +300mV DC Input Voltage .. ~-0.5V to +5.0V Pin Definitions Signal Name Description | I/O Description Dog Data Iriputs | | Data Inputs for 9-bit bus Qo. Data Outputs | Data Outputs for 9-bit bus WEN1 Write Enable 1 | | The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WENT is asserted and FF is HIGH. ifthe FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WENT is LOW and WEN2/D and FF are HIGH. WEN2/LD Write Enable 2 1 | If HIGH at reset, this pin operates as a second write enable. if LOW at reset, this pin Dual Mode Pin Load i operates as a control to write or read the programmabie flag offsets. WENT must be oa LOW and WEN2 must be HIGH to write data into the FIFO. Data will notbe written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. RENT, REN2 | Read Enable 1! | Enables the device for Read operation. Inputs ! WCLK Write Clock 1 | The rising edge clocks data into the FIFO when WENT is LOW and WEN2/(D is HIGH and the FIFO is not Full. When CD is asserted, WCLK writes data into the programmable flag-of- set register.CYPRESS Pin Definitions (continued) CY7C4421V/4201V/4211V/4221V PRELIMINARY CY7C4231V/4241V/4251V Signal Name | Description | /O Description RCLK Read Clock | | The rising edge clocks data out of the FIFO when RENT and REN@Z are LOW and the FIFO is not Empty. When WEN2/CD is LOW, RCLK reads data out of the programmable flag-offset register. EF Empty Flag O | When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O | When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable | O | When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro- Aimost Empty grammed into the FIFO. PAF Programmable | O | When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed Almost Full into the FIFO. RS Reset | | Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable | | When GE is LOW, the FIFOs data outputs drive the bus to which they are connected. if OE is HIGH, the FIFOs outputs are in High Z (high-impedance) state. Electrical Characteristics Over the Operating Range! 7C42X1V-15 I TC42K1V-25 7C42XK1V-35 Parameter | Description Test Conditions Min. Max. | Min. Max. Min. Max. | Unit Vou Output HIGH Voltage =| Ver = Min., 2.4 2.4 24 v toy =-2.0 mA Voi Output LOW Voltage Voc = Min., 0.4 0.4 04 ; V lg, = 8.0 mA Vin Input HIGH Voltage 2.0 5.0 2.0 .0 2.0 5.0 Vv Vie Input LOW Voltage 0.5 0.8 -0.5 0.8 -0.5 0.8 v hx Input Leakage Voc = Max. ~10 +10 ~10 +16 ~10 +10 uA Current L loz. Output OFF, OE = Vin, -10 +10 ~10 +10 ~10 +10 pA loz High Z Current Vgs < Vo < Vec { Igcl4! Active Power Supply Com'l 20 20 20 mA Current tga! Average Standby Com) 6 6 / 6 mA Current | Capacitance"! Parameter Description Test Conditions Max. Unit Cw Input Capacitance Ty = 25C, f= 1 MHz, 5 pF | Cour Output Capacitance Voc = 5.0V 7 pF Notes: 1. See the last page of this specification for Group A subgroup testing information. 2. Outputs open. 3. Ail inputs = Vog ~0.2V, except ested at Fraquency = 20 MHz. WCLK and RCLK, which are swiiching at 20MHz, 4. Tested initially find after any design or process changes that may affect these parameters. 2-21CY7C4421V/4201V/4211V/4221V PRELIMINARY CY7C42 CYPRESS 31V/4241V/4251V AC Test Loads and Waveforms:4 Fil= 330 Ohms 3.3V On ALL INPUT PULSES OUTPUTS CF R2=510 Ohms INCLUDING = JIG AND = = SCOPE 42X1V-4 42X1V-5 Equivaient to: THEVENIN EQUIVALENT Rth=200 Ohms OUTPUT 6-9-9 Vihi=2.0V Switching Characteristics Over the Operating Range 7C42X1V-15 7C42X1V-25 7C42X1V-35 Parameter Description Min. Max. | Min. Max. Min. Max. | Unit ts Clock Cycle Frequency 66.7 40 28.6 | MHz ta Data Access Time 2 im 2 15 2 20 ns tou Clock Cycle Time 15 25 35 ns toLkH Clock HIGH Time 6 10 14 ns touKe Clock LOW Time 6 10 14 ns tos Data Set-Up Time 4 6 ns tox Data Hold Time 1 2 2 ns tens Enable Set-Up Time 4 ns tenH Enable Hold Time 1 2 2 ns tas Reset Pulse Width! 15 25 35 ns tass Reset Set-Up Time 10 15 20 ns taser Reset Recovery Time 10 15 20 ns tase Reset to Flag and Output Time 15 25 35 ns toz Output Enable to Output in Low ZE! , 0 0 0 ns toe Output Enable to Output Valid 3 8 3 2: 3 15 | ons ton Output Enable to Output in High Zi! 3 8 3 12 3 15 ns wre Write Clock to Full Fiag 11 15 20 ns trer Read Clock to Empty Flag 11 15 20 ns par Clock to Programmable Almost-Full Flag "1 15 20 ns {pa Clock to Programmabie Aimost-Fuil Flag VW 15 20 ns toxew1 Skew Time between Read Clock and Write Clock 6 10 12 ns for Empty Flag and Full Flag igkewe Skew Time between Read Clock and Write Clock 15 18 20 ns for Almost-Empty Flag and Almest-Full Flag Notes: 5. & =30 pF or all AC parameters except for to.2. 6. =5 r . 7, Pulse widths less than minimum values are not allowed, 8. Values guaranteed by design, not currently tested. 2-22CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V =p. CYPRESS PRELIMINARY Switching Waveforms Write Cycle Timing WCLK Dp -Dg NO OPERATION WENT NO OPERATION WEN2 (if applicable} FF RCLK RENT, RENZ f 42xX1V-6 Read Cycie Timing ACLK RENT,RENZ NO OPERATION Qo -Qg VAUD DATA OE tskewt WCLK peat WEN2 f/f Notes: tsxew1 is the minimum time between a rising ROLK edge and a rising WCLK edge to guarantee that FF will go HIGH oumng the current clock cycle. If the time between the K rising edge. 42X1V-7 9. rising edge of RCLK and the rising edge of WCLK is less than toaw, then FF may not change state until the next W 10. taxewi iS the minimum time between a rising WCLK edge and arising CLK edge to quarantee that EF will go HIGH during the current clock cycle, lt the time between the rising edge of WCLK and the rising edge of RCLK is less than tgxeyw;, then EF may not change state until the next RCLK rising edge. 2-23ay CY7C4421V/4201V/4211V/4221V PRELIMINARY CYPRESS CY7C4231V/4241V/4251V Switching Waveforms (continued) Reset Timing!" i RS WEN2ED |") EF.PAE FF,PAF, Oger Al Qo- OE=0 A2X1V-B Notes: 11. The clocks (RCLK, WCLK) can be free-running during reset. 12. After reset. the outputs wil! be LOW if 13. Holding WEN2/D OE =0 and three-state f OE=1. programmanie flag offset HIGH during reset will make the pin act as a second enable pin. Holding WEN2/CD LOW during reset will make the pin act as a load enable for the 2-24CY7C4421V/4201V/4211V/4221V PRELIMINARY CY7C4231V/4241V/4251V CYPRESS Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK Do -Dg Dp (FIRSTVALID WRITE) WENT WEN2 (it applicable) rex, \ \ 7 oo XXXXXLE . tovz OE aN toe 42K1V-9 Notes: 14, Wher texewy 2 irnimum specification, +t . When tex ews <fninimum specification, tea, (maximum) = either 2"te + tgxew Olen + igen The extey tn rary (ERE LG fring apples only ty at the Emp +5, The tirst word is available the cycie after P toes Me TIGH, always. 2-25CY7C4421V/4201V/4211V/4221V PRELIMINARY v/4241 BaP o05: CY7C4231V/4241V/4251V Switching Waveforms (continued) Empty Flag Timing fo NSN Do-Ds DATAWRITE XX OX XK XXX DATAWRITE? XX XX XX ten: tenn Wan \ t WENT K lens tens tenH tens tENH WEN2 " (if applicable) K\, (14) . 14) < Ira. ! ba tera! J WCLK I~ tskews ther m| ther EF RENT, RENZ LOW DE ty o Qo -Qg DATA IN OUTPUT REGISTER DATA READ 42X1V-10 2-26CY7C4421V/4201V/4211V/4221V 5 PRELIMINARY CYPRESS CY7C4231V/4241V/4251V Switching Waveforms (continued) Full Flag Timing NO WRITE NO WRITE NO WRITE WCLK / \ 7 tos tgxews DATA WRITE tsxewr | Wer he twee twee a / . oN NI WEN2 5 (if applicable) val RCL NLA NL NI VK ONY SS tent tenH RENT, tens tens REN2 WwW OE LO < ta w ta Qo -Qg DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ 42X1V~11 Programmable Almost Empty Flag Timing touKH 1 tcuKL WeLk MON N INYO rererenel tens | tenn WENT QS LA, (if applicable) JL Aa MA tens | tenH Note 17 PAE N+ 1 WORDS Note 18 = INFIFO tear tskewe!"@l < tpag ACLK tens tens | tenn RENT, SS Y YA 42X1V~-12 FRENZ KA 7 Notes: 16. tgxewo is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the tiang ACL is less than tgxeyo, then PAE may not change state until the next RCL. 17. PAE offset =n. 18. ifa read is performed on this rising edge of the read clock, there will be Empty + (n-) words in the FIFO when PAE goes LOW 2-27CY7C4421V/4201V/4211V/4221V PRELIMINARY CY7C4231V/4241V/4251V CYPRESS Switching Waveforms (continued) Programmable Almost Full Flag Timing Note 19 toLKH feL kL WCLK MON NY NNN tens | tenn MN v Wwe Sa LA WEN2 Note 20 (if applicable) WA, / Ys N tens | tenn Ie tpar | PAF FULL - M WORDS FULL M+1 WORDS IN FIFO 21) iN FIFO tsxewe!*l trae RCL NL ANY VY VN KX NY \ tens tens | teny ey NN. Za Write Programmable Registers < tok | toLKH f toLke wcLK __ MON NINN tens tenH WEN2/LD NS \ <, o~ ENS ><> WENT ~~ KK tos toy 05-05 IOK KKK XOX KEK KKK PAE OFFSET PAE OFFSET PAF OFFSET PAF OFFSET LSB MSB LSB MSB 42X1V-14 Notes: 19. If awrite is performed on this rising edge of the wrte clock, there wili be Full - (m1) words of the FIFO when PAF goes LOW. 20. PAF offset =m. 21. 64-m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512--m words tor CY7C4211V, 1024m words for CY7C4221V, 2048-m words for CY7C4231V, 4096-m words for CY7C4241V, 8192-m words far CY7C4251V. 22. tgxewe is the minimum tme between a rising RCLK and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and We rising edge of WCLK is less than tgewa. then PAF may nat change state unti the next WCLK. 2-28=. CYPRESS PRELIMINARY CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Switching Waveforms (continued) Read Programmable Registers fouk feLKH f toLKL CLK J MON NY ONLY OV tens teny WeN2iD XX SK MLZ TENS fegpol HENT, NX NJ PAF OFFSET REND K MSB, nee ta Architecture The CY7C42X1V consists of an array of 64 to 8K words of 9 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, RENT, REN2, WENT, WEN2, RS), and flags (EF, PAE, PAF, FF). Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition sig- nified by EF being LOW. All data outputs (Q9_g) go LOW tpsp after the rising edge of RS. tn order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. All flags are guaran- teed to be valid trop after RS is taken LOW. FIFO Operation When the WEN? signal is active LOW and WEN2 is active HIGH, data present on the Dp_g pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the RENT and REN2 signals are active LOW, data in the FIFO memory will be presented on the Qg_g outputs. New data will be presented on each rising edge of RCLK while RENT and REN2 are ac- tive. RENT and REN2 must set up tens before RCLK for it to be a valid read function. WENT and WEN2 must occur tens before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Qo_g outputs when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Qo_g outputs after toe. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Qo., outputs even after additional reads occur. Write Enable 1 (WENT) - If the FIFO is configured for pro- grammable flags, Write Enable 1 (WENT) is the only write en- able control pin. In this configuration, when Write Enable 1 (WENT) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored is the RAM array sequentially and in- dependently of any on-going read operation. PAE OFFSET LSB PAE OFFSET MSE PAF OFFSE =x 4 42X1V-15 Write Enable 2/Load (WEN2/LD) - This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. If Write Enable 2/Load (WEN2/TD) is set active HIGH at Reset (RS=LOW), this pin operates as a second write enable pin. if the FIFO is configured to have two write enables. when Write Enable (WENT) is LOW and Write Enable 2/Load (WEN2/CD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK), Data is stored in the RAM array sequentially and in- dependently of any on-going read operation. Programming When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/CD can be used to access the four 8-bit offset registers contained in the CY7C42X1V for writing or reading data to these registers. When the device is configured for programmabie flags and both WEN2/ED and WENT are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the emp- ty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB)} register, fuil offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WENT are LOW. The fifth LOW-to-HIGH tran- sition of WCLK while WEN2/CD and WENT are LOW writes data to the empty LSB register again. Figure 1 shows the reg- isters sizes and default values for the various device types. itis not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write operation stores data in the next offset register in se- quence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both RENT and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register con- tents to the data outputs. Writes and reads should not be pre- formed simultaneously on the offset registers. 2-29CY7C04421V/4201V/4211V/4221V 64x9 256 x9 512x9 1Kx9 8 6 0 8 7 0 8 7 0 8 7 0 Empty Offset (LSB) Reg. xX) Empty Offset (LSB) Reg. Empty Offset (LSB) Reg. Empty Offset (LSB) Aeg. Defauit Value= O07h Defauit Value= 007h Defautt Value= 007h Default Vatue= 007h 8 0 8 0 8 0 8 1 o Q 00 \ LV 8 6 0 8 7 0 8 7 0 8 7 oO XX Full Offset (LSB) Aeg Full Offset (LSB) Reg x Fut Offset (LSB) Reg x Ful Offset (LSB} Reg Default Valua= CO7h Detautt Value= 007h Detauit Value= 007h Default Value= 007h 8 0 8 9 8 0 8 i Q Oo 00: 2Kx9 4Kx@ 8Kx9 8 7 0 3 7 0 8 7 0 Empty Offset (1 S8) Reg. Ernoty Offset (LSB) Reg. x) Empty Offsel (LSBi Req. Default Value= 007h Default Value= CO7h Detautt Value = CO7h 8 2 0 8 3 Q 8 4 0 X) {MSB) {MSB) x {MSB} 000 000 90000 8 7 0 8 7 Q 8 Z Q x Full Offset (LS8) Reg Full Offset (LSB) Reg x) Full Offset (LSB) Reg Default Value= O07h Default Value= 007K Detauit Value = 007h 8 2 0 a 3 0 8 4 0 N, (MSB) XXX (MSB) x (MSB) 000 coca 00000 Figure 1. Offset Register Location and Default Values Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable aimost-empty flag (PAE) and programmable atmost-fuill flag (PAF) states are determined by their corresponding offset reg- isters and the difference between the read and write pointers. Table 1. Writing the Offset Registers LD] WEN | WCLKE! Selection 0 0 Empty Offset (LSB) Sf Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 1 _f- No Operation 1 0 ff Write Into FIFO 1 1 _f No Operation Note: The number formed by the empty offset least significant bit register and empty offset mest significant register is referred to as nand determines the operation of PAE. PAE is synchro- nized to the LOW-io-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread words. The number formed by the full offset least significant bit regis- ter and full offset most significant bit register is referred to as mand determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421V. (64 - m), CY7C4201V (256 m), CY7C4211V (512 m), CY7C4221V (1K m), CY7C4231V (2K - m), CY7C4241V (4K ~ m), and CY7C4251V (8K m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory lo- cations is greater than m. 23. The same selection sequence applies to reading trom the registers. RENT and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK. 2-30CY7C4421V/4201V/4211V/4221V CYPRESS PRELIMINARY CY7C4231V/4241V/4251V Table 2. Status Flags Number of Words in FIFO CY7C4421V CY7C4201V CY7C4211V FF | PAF | PAE | EF 0 0 0 H H L L 1 to nl@4] 1 to nl@4l 1 to nl@4l H H L H (n+1) to 32 (n+1) to 128 (n+1) to 256 H H H H 33 to (64(m+1)) 129 to (256-(m+1)) 257 to (512-(m+1)) H H H H (64m)4l to 63 (256~m) I to 255 (512-m)! to 511 lH L H H 64 256 512 L L H H Number of Words in FIFO CY7C4221V CY7C4231V CY7C4241V CY7C4251V FF | PAF | PAE) EF 0 0 0 0 H | H L L + to net 1 to net 4 to n@4l 110 n@4l Hq H L H (n+1) to 512 (n+1) to 1024 (n+1)} to 2048 (n+1) to 4096 H H H H 513 to (1024 -(m+1)) | 1025 to (2048 ~(m+1))} | 2049 to (4096 -(m+1)) | 4097 to (8192 -(m41)} ) H | H | H | OH (1024m)!5l to 1023 | (2048~m)lto 2047 | (4096-m)*Ito4095 =| (8192-m)ltoai91 HIOL H H 1024 2048 4096 8192 Leek H | H Notes: 38. imw Bul Orteat me? default value) Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. A compas- ite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42X1Vs. Any word width can be attained by adding additional CY7C42X1Vs. When the CY7C42X1V is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (See Figure 2). in this configuration, the Write Enable 2/Load (WEN2/(B) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable fiag offsets. Flag Operation The CY7C42X5 devices provide five flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Fuil Flag The Full Flag (FF) wilt go LOW when device is full. Write oper- ations are inhibited whenever FF is LOW regardless of the state of WENT and WEN2/(D. FF is synchronized to WCLK, i.8., itis exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regard- tess of the state of RENT and RENZ. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of ACLK. 2-31CY7C4421V/4201V/4211V/4221V PRELIMINARY CY7C4231V/4241V/4251V CYPRESS RESET(RS) RESET (RS) DATAIN(D) 13 | 9, a, READ CLOCK (RCLK) WRITE CLOCK(WCLK) [00000000 Re nr rrr rns TT TTToaoaoa ee REN WRITE ENABLE 1 (WENT) we ewe ee =e] | EAD ENABLE 1 (RENT) WRITE ENABLEDILOAD ENABLEDLOAD | tCt*~C~CS~S*~d ee OUTPUT ENABLE (OE) (WEN2/LD) oe eee PROGRAMMABLE (PAE) EMPTY FLAG (EF) #1 CY7C42x1V cy7c4axiv PROGRAMMABLE (PAF) $f ~~FULLFLAG(FF)# 1 | EL I EF | EMPTY FLAG (EF) #2 i_____|------..-.-4 9 , DATA OUT(Q) ig, FULL FLAG (FF) # 2 3 + 7 a Read Enable 2 (REN2) Read Enable 2 (REN2) F2X1V-16 Figure 2. Block Diagram of 64 x 9,256 x 9,512 x 9,1024 x 9,2048 x 9,4096 x 9,8192 x 9 Low Voltage Synchronous FIFO Memory Used in a Width Expansion Configuration Ordering Information 64 x 9 Low Voltage Synchronous FIFO Ordering Code 256 x 9 Low Voltage Synchronous FIFO ns) Ordering Code 2-32CY7C4421V/4201V/4211V/4221V PRELIMINARY 7 =p. CYPRESS CY7C4231V/4241V/4251V Ordering Information (continued) 512 x 9 Low Voltage Synchronous FIFO ) Ordering Code 1 1K x 9 Low Voltage Synchronous FIFO ) Ordering Code 1 2K x 9 Low Voltage Synchronous FIFO ) Ordering Code V-1 4K x 9 Low Voltage Synchronous FIFO ns) Ordering Code 1 1 8K x 9 Low Voltage Synchronous FIFO ns) Ordering Code 1 1 1 Document #: 38-00622 2-33