SEMICONDUCTOR TECHNICAL DATA The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4-stage counters. The counter stages are type D flip-flops, with interchangeable Clock and Enable lines for incrementing on either the positive-going or negative-going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC14518B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi-stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 * * * * DW SUFFIX SOIC CASE 751G Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Internal and External Speeds Logic Edge-Clocked Design -- Incremented on Positive Transition of Clock or Negative Transition on Enable * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Value Unit - 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin 10 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature - 65 to + 150 _C 260 _C TL Lead Temperature (8-Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C TRUTH TABLE Clock Enable Reset Action 1 0 Increment Counter 0 Increment Counter 0 No Change 0 No Change 0 No Change 0 No Change 1 Q0 thru Q3 = 0 0 X X 0 1 X X X = Don't Care ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = - 55 to 125C for all packages. BLOCK DIAGRAM CLOCK 1 Q0 Q1 Q2 C 2 ENABLE R 3 4 Q3 5 6 Q0 11 Q1 Q2 Q3 12 7 CLOCK 9 C 10 ENABLE R 13 14 15 VDD = PIN 16 VSS = PIN 8 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14518B MC14520B 409 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc 5.0 10 15 -- -- -- 1.5 3.0 4.0 -- -- -- 2.25 4.50 6.75 1.5 3.0 4.0 -- -- -- 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 5.0 10 20 -- -- -- 0.005 0.010 0.015 5.0 10 20 -- -- -- 150 300 600 Adc IT 5.0 10 15 Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL "1" Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (0.6 A/kHz) f + IDD IT = (1.2 A/kHz) f + IDD IT = (1.7 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002. PIN ASSIGNMENT MC14518B MC14520B 410 CA 1 16 VDD EA 2 15 RB Q0A 3 14 Q3B Q1A 4 13 Q2B Q2A 5 12 Q1B Q3A 6 11 Q0B RA 7 10 EB VSS 8 9 CB MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q/Enable to Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL VDD Min Typ # Max 5.0 10 15 -- -- -- 100 50 40 200 100 80 Unit ns ns 5.0 10 15 -- -- -- 280 115 80 560 230 160 5.0 10 15 -- -- -- 330 130 90 650 230 170 tw(H) tw(L) 5.0 10 15 200 100 70 100 50 35 -- -- -- ns fcl 5.0 10 15 -- -- -- 2.5 6.0 8.0 1.5 3.0 4.0 MHz tTHL, tTLH 5.0 10 15 -- -- -- -- -- -- 15 5 4 s Enable Pulse Width tWH(E) 5.0 10 15 440 200 140 220 100 70 -- -- -- ns Reset Pulse Width tWH(R) 5.0 10 15 280 120 90 125 55 40 -- -- -- ns trem 5.0 10 15 -5 15 20 - 45 - 15 -5 -- -- -- ns Reset to Q tPHL = (1.7 ns/pF) CL + 265 ns tPHL = (0.66 ns/pF) CL + 117 ns tPHL = (0.66 ns/pF) CL + 95 ns tPHL Clock Pulse Width Clock Pulse Frequency Clock or Enable Rise and Fall Time Reset Removal Time ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 500 F PULSE GENERATOR ID 0.01 F CERAMIC C Q0 Q1 Q2 E Q3 R CL CL CL CL VSS 20 ns 20 ns 50% 90% VARIABLE WIDTH 10% VSS Figure 1. Power Dissipation Test Circuit and Waveform MOTOROLA CMOS LOGIC DATA MC14518B MC14520B 411 20 ns VDD PULSE GENERATOR C 20 ns 90% 50% 10% CLOCK INPUT Q0 tWH Q1 E R Q2 Q3 CL VSS CL CL VSS tWL tPHL tPLH CL VDD 90% 50% 10% Q tr tf Figure 2. Switching Time Test Circuit and Waveforms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 0 1 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 CLOCK ENABLE RESET 2 3 4 5 Q0 MC14518B Q1 Q2 Q3 4 Q0 MC14520B Q1 Q2 Q3 Figure 3. Timing Diagram MC14518B MC14520B 412 MOTOROLA CMOS LOGIC DATA Q0 D C R Q1 Q D Q C R Q2 Q D Q C R Q3 Q D Q C Q R Q RESET ENABLE CLOCK Figure 4. Decade Counter (MC14518B) Logic Diagram (1/2 of Device Shown) Q0 D C R Q1 Q D Q C R Q2 Q D Q C R Q3 Q D Q C Q R Q RESET ENABLE CLOCK Figure 5. Binary Counter (MC14520B) Logic Diagram (1/2 of Device Shown) MOTOROLA CMOS LOGIC DATA MC14518B MC14520B 413 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C L DIM A B C D E F G H K L M N -T- K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- SEATING PLANE K H G D 16 PL 0.25 (0.010) MC14518B MC14520B 414 J M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A -A- 16 9 -B- 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. M B M 8 16X J D 0.010 (0.25) M T A B S S F R X 45 _ C -T- 14X G K SEATING PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CMOS LOGIC DATA *MC14518B/D* MC14518B MC14520B MC14518B/D 415