5962-9326101MEA - Texas Instruments High-Performance Analog

6/98

BL OCK DIAGRAM

•Con trol Boost PWM to 0. 99 Power Factor

•Limit Line Current D ist ortion To <5%

•World-Wide Operation Without Switches

•Feed-Forward Line Regulation

•Average Cur rent- Mode Con trol

•Low Noise Sensitivity

•Low Start- Up Supply Curr ent

•Fixed-Fr equenc y PWM Drive

•Low-Offset Analog Multiplier/Divider

•1A Totem-Pole Gate Driver

•Precision Voltage Reference

The UC1854 provides active power factor correction for power sys-

tems that otherwise would draw non-sinusoidal current from sinusoi-

dal power lines. This device implements all the control functions

necessary to build a power supply capable of optimally using available

p ower-line current while minimizing line-current d istortion. To do this,

the UC1854 contains a vo ltage amplifier, an analog multiplier/divider,

a current amplifier, and a fixed-frequency PWM. In addition, the

UC1854 contain s a powe r MOSFET compatible gate driver, 7.5V ref-

erence, line anticipator, load-enable comparator, low-supply detector,

and over -cu rrent comparator.

The UC1854 uses averag e current-mode control to accomplish fixed-

freque ncy current control with stability and low distortion. Unlike peak

cur rent-mode, average current control accurately maintains sinusoidal

l ine current without s lope compen s ation and w ith minimal res ponse t o

noise transients.

The UC1854’s high reference voltage and high oscillator amplitude

mi nimi ze noi se sensitivity while f ast PWM elements permit chopping

frequencies above 200kHz. The UC1854 can be used in single and

three pha se systems with line voltages that vary from 75 to 275 volts

a nd line frequencies across the 50Hz to 400H z range. To reduce the

bur den on the c ircuitry t hat suppl ies pow er to t his device, t he UC 1854

f eat ures low st arting supply current.

These devices are available packaged in 16-pin plastic and ceramic

dual in-line packages, and a variety of surface-mount packages.

UC1854

UC2854

UC3854

High Power Factor Preregulator

FEATURES DESCRIPTION

UDG-92055

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V

GT Drv Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

GT Drv Current, 50% Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 1.5A

Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

Input Voltage, ISENSE, Mult Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65oC to +150oC

Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . +300oC

ABSOLUTE MAXI MUM RATI NG S

PA CKAG E PIN FUNCTI ON

FUNCTION PIN

N/C 1

Gnd 2

PKLMT 3

CA Out 4

ISENSE 5

N/C 6

Mult Out 7

IAC 8

VA Out 9

VRMS 10

N/C 11

VREF 12

ENA 13

VSENSE 14

RSET 15

N/C 16

SS 17

CT18

VCC 19

GT Drv 20

PLCC- 2 0 & LCC-20

(To p V iew)

Q & L Packages

CONNECTION DIAGRAMS

D IL–16 & SO IC-16

(Top View)

J, N & DW Packages

Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,

VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out,

VA Out, REF, GT Drv, –55oC<TA<125oC for the UC1854, –40oC<TA<85oC for the UC2854, and

0oC<TA<70oC for the UC3854, and TA=TJ.

ELECTRICAL

CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

OVERALL

Supply Current, Off ENA=0V 1.5 2.0 mA

Supply Current, On 10 16 mA

VCC Turn-On Threshold 14.5 16 17.5 V

VCC Turn-Off Threshold 9 10 11 V

ENA Threshold, Rising 2.4 2.55 2.7 V

ENA Threshold Hysteresis 0.2 0.25 0.3 V

ENA Input Current ENA=0V –5.0 –0.2 5.0 µA

VRMS Input Current VRMS=5V –1.0 –.01 1.0 µA

VOLTAGE AMPLIFIER

Voltage Amp Offset Voltage VA Out=5V –8 8 mV

VSENSE Bias Current –500 –25 500 nA

Voltage Amp Gain 70 100 dB

Voltage Amp Output Swing 0.5 to 5.8 V

Voltage Amp Short Circuit Current VA Out=0V –36 –20 –5 mA

SS Current SS=2.5V –20 –14 –6 µA

UC1854

UC2854

UC3854

Note 1: All voltages with respect to Gnd (Pin 1).

Note 2: All currents are positive into the specified termi-

nal.

Note 3: ENA input is internally clamped to approximately

14V.

Note 4: Consult Unitrode Integrated Circuits databook for

information regarding thermal specifications and limita-

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CURRENT AMPLIFIER

Current Amp Offset Voltage –4 4 mV

ISENSE Bias Current –500 –120 500 nA

Input Range, ISENSE, Mult Out –0.3 to 2.5 V

Current Amp Gain 80 110 dB

Current Amp Output Swing 0.5 to 16 V

Current Amp Short Circuit Current CA Out=0V –36 –20 –5 mA

Current Amp Gain-BW Product TA=25oC (Note 6) 400 800 kHz

REFERENCE

Reference Output Voltage IREF=0mA, TA=25oC 7.4 7.5 7.6 V

IREF=0mA, Over Temp. 7.35 7.5 7.65 V

VREF Load Regulation –10mA<IREF<0mA –15 5 15 mV

VREF Line Regulation 15V<VCC<35V –10 2 10 mV

VREF Short Circuit Current REF=0V –50 –28 –12 mA

MULTIPLIER

Mult Out Current IAC Limited IAC=100µA, RSET=10k, VRMS=1.25V –220 –200 –180 µA

Mult Out Current Zero IAC=0µA, RSET=15k –2.0 –0.2 2.0 µA

Mult Out Current RSET Limited IAC=450µA, RSET=15k, VRMS=1V, VA Out = 6V –280 –255 –220 µA

Mult Out Current IAC=50µA, VRMS=2V, VA=4V –50 –42 –33 µA

IAC=100µA, VRMS=2V, VA=2V –38 –27 –12 µA

IAC=200µA, VRMS=2V, VA=4V –165 –150 –105 µA

IAC=300µA, VRMS=1V, VA=2V –250 –225 –150 µA

IAC=100µA, VRMS=1V, VA=2V –95 –80 –60 µA

Multiplier Gain Constant (Note 5) –1.0 V

OSCILLATOR

Oscillator Frequency RSET=15k 46 55 62 kHz

RSET=8.2k 86 102 118 kHz

CT Ramp Peak-to-Valley Amplitude 4.9 5.4 5.9 V

CT Ramp Valley Voltage 0.8 1.1 1.3 V

GATE DRIVER

Maximum GT Drv Output Voltage 0mA load on GT Drv, 18V<VCC<35V 13 14.5 18 V

GT Drv Output Voltage High –200mA load on GT Drv, VCC=15V 12 12.8 V

GT Drv Output Voltage Low, Off VCC=0V, 50mA load on GT Drv 0.9 1.5 V

GT Drv Output Voltage Low 200mA load on GT Drv 1.0 2.2 V

10mA load on GT Drv 0.1 0.4 V

Peak GT Drv Current 10nF from GT Drv to Gnd 1.0 A

GT Drv Rise/Fall Time 1nF from GT Drv to Gnd 35 ns

GT Drv Maximum Duty Cycle VCA Out=7V 95 %

CURRENT LIMIT

PKLMT Offset Voltage –10 10 mV

PKLMT Input Current PKLMT=–0.1V –200 –100 µA

PKLMT to GT Drv Delay PKLMT falling from 50mV to –50mV 175 ns

Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,

VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out,

VA Out, REF, GT Drv, –55oC<TA<125oC for the UC1854, –40oC<TA<85oC for the UC2854, and

0oC<TA<70oC for the UC3854, and TA=TJ.

UC1854

UC2854

UC3854

Note 5: Multiplier Gain Constant (k) is defined by:

Mult

Out

× (

Out

−1)

RMS

Note 6: Guaranteed by design. Not 100% tested in production.

ELECTRICAL

CHARACTERISTICS

Gnd (Pin 1) (ground): All vo ltages are measured with re-

spect to Gnd. VCC and REF sh ould be bypassed di rectly

t o Gnd wi th an 0.1µF or larger ceramic capacitor. The tim-

in g capacitor di scharge curr ent als o retur ns to this pi n, so

the lead from the oscillator timing capacitor to Gnd should

also be as short and as direct as possibl e.

PKLMT (Pin 2) (peak limit): The threshold for PKLMT is

0.0V. Connect this input to the negative voltage on the

cur r ent sense r es i s t or as shown i n Figure 1. Use a resis-

tor to REF to offset the negative current sense sig nal up

to Gnd.

CA Out (Pin 3) (current amplifier output): This is the out-

put of a wide-band width op a mp that senses line current

and com m ands the pul se w idt h mo dulator (P WM) t o force

the co rrect curren t. T his output can swing close to Gnd,

allowing the PWM to force zero duty cycle when neces-

sary . The current amplif ier will remain active even if the IC

is dis able d. The curre nt amplifier output stage is an NPN

emitter follower pull-up and an 8k resistor to ground.

ISENSE (Pi n 4) (curr ent sense m inu s ): Thi s is the inv erting

input to the current amplifier. This input and the non-in-

ver t ing input M ul t Out r emain f unct ional down to and be-

low Gnd. Care should be taken to avoid taking these

inputs below –0.5V, because they are protected with di-

odes to Gnd.

Mult Out (Pin 5) (multiplier output and current sense

plus): The output of the analog multiplier and the non-in-

verting input of the current amplifier are connected to-

gether at Mult Out. The cautions about taking ISENSE

bel ow –0.5V als o apply to Mult Out. As t he m ul ti plier out -

put is a cu rrent , this is a high imp edance input similar to

ISENSE, so the current amplifier can be configured as a

differential amplifier to reject Gnd noise. Figure 1 shows

an exam ple of using the current amplifier dif fer entially .

IAC (Pin 6) (input AC current): This input to the analog

multiplier is a current. The multiplier is tailored for very

low distortion from this current input (IAC) to Mult Out, so

this is the only multiplier input that should be used for

sensing instantaneous line voltage. The nominal voltage

on IAC is 6V, so in addition to a resistor from IAC to recti -

f ied 60Hz , connect a resist or fr om I AC to REF. If the resis-

tor to REF is one fourth o f th e val ue of the resistor to the

rectifier, then the 6V offset will be cancel led, and the line

curr ent will have minimal cross-over distortion.

VA Ou t ( Pi n 7) ( voltage am pli fi er out put): This i s the out -

put of the op amp t hat regulates outpu t voltage. Like the

current amplifier, the voltage amplifier will stay active

even if the IC is disabled with either ENA or VCC. This

means that large feedback capacitor s across the amplifier

will stay ch ar ged thro ugh moment ary disable cycles. Volt -

age a mplifier output levels bel ow 1V will inhibit multiplier

out put . The volt age am plif ier output is i nternall y limi ted to

approximately 5.8V to prevent overshoot. The voltage

ampl ifier ou tpu t stage is an NPN emitt er follower p ull-up

and an 8k re sistor to ground.

VRMS (Pin 8) (RMS line voltage): The output of a boost

PWM is propor tional to the input voltage, so when the line

voltage into a low-bandwidth boost PWM voltage regula-

tor changes, the output will change immediately and

slowly recove r to the regula ted le vel. Fo r these devices,

t he VRMS input com pensat es for li ne volt age changes if it

is connected to a voltage proportional to the RMS input

line voltage. For best control, the VRMS voltage should

stay between 1.5V and 3.5V.

REF (Pin 9) (vol tag e reference output): R EF is the output

of an accurate 7.5V voltage reference. This output is ca-

pab le of delive ring 10mA to peripheral circuitry a nd is in-

ternally short circuit current limited. REF is disabled and

will remain at 0V when VCC is low or when ENA is low.

Byp ass REF to Gnd with an 0.1µF or l arger ceramic ca-

pacitor f or best st ability.

ENA (Pin 10) (enable): ENA is a logic input that will en-

able the PWM output, voltage reference, and oscillator.

ENA also wi ll r eleas e t he soft star t c lamp, all owin g SS to

rise. When unused, connect ENA to a +5V supply or pull

ENA high w it h a 22k r esist or. The ENA pin is not int ended

t o be used as a high speed shu tdow n to t he PWM output.

VSENSE (Pin 11) ( voltage ampl ifier inver ti ng input) : Thi s is

normally connected to a feedback network and to the

boost conver t er output through a divider network .

RSET (Pin 12) (oscillator charging current and multiplier

limit set): A resistor from RSET to gr ound w ill pro gram os-

cillator charging current and maximum multiplier output.

Multiplier output current will not exceed 3.75 V divided by

the resistor from RSET to ground.

SS ( Pi n 13) (soft start ): SS will r emain at Gnd as long as

the IC is disabled or VCC is too low. SS will pull up to over

8V by an internal 14µA current source when both VCC be-

com es vali d and t he I C is enabl ed. SS w il l act as t he r ef-

erence input to the vol tage amplifier if SS is below REF.

With a large capacitor from SS to Gnd, the reference to

the voltage regulating amplifier will rise slowly, and in-

crease the PWM duty cycle slowly. In the event of a dis-

able command or a supply dropout, SS will quickly

discharge to ground and disable the PWM.

CT (Pin 14) (osci llator timing capacitor): A capacitor from

CT to Gnd will set the P WM osci llator frequency accord-

ing to this relatio nship:

= 1.25

SET

VCC (Pin 15) (positive supply voltage) : Connect VCC to a

st abl e s our ce of at least 20m A above 17V for norm al op-

eration. Also bypass VCC directly to Gnd to absorb supply

cur r ent spikes re quired to charge ex te rnal M OSF ET gate

capacitances. To prevent inadequate GT Drv signals,

these devices will be inhibited unless VCC exceeds the

upper under-voltage lockout threshold and remains

above the low er threshol d.

PIN DESCRIPTIONS (Pin Number s Refer to DI L P ackages)

UC1854

UC2854

UC3854

GT Drv (Pin 16) ( gate d rive): The output of the PWM is a

t otem pole MO SFET gate driv er on GT Drv. This outp ut is

internally clamped to 15V so th at the IC ca n be operated

wi th VCC as hig h as 35V. Us e a ser i es gate r es is tor of at

least 5 ohms to preve nt interac tion between the gate im-

pedance and the GT Drv output driver that might cause

the GT Drv output to overshoot excessively. Some over-

shoot of the GT Drv output is always e xpected when dr iv-

ing a capacitive load.

T YPI CAL CHARACTERISTICS at T A = TJ = 2 5°C

UC1854

UC2854

UC3854

Load Capacitance, µF

100

200

300

400

500

600

700

0 0.01 0.02 0.03 0.04 0.05

Rise Time

Fall Time

SET

, k Ω

Duty

Cycle

70%

75%

80%

85%

90%

95%

100%

1 10 100

I,A

Multiplier

Output

µA

100

200

300

400

500

600

0 100 200 300 400 500

600

700 800

Mult Out=1 Mult Out=2V

Mult Out=3V

Mult Out=0V

V =2V, VA Out=5V

RMS

R,k

SET

Ω

Frequency

kHz

100

1000

110 100

100pF

200pF

5nF

10nF 3nF

500pF

2nF

1nF

Frequency

kHz

Phase

Margin

degrees

Open-Loop

Gain

-20

100

120

0.1 1 10 100 1000 10000

Frequency

kHz

Phase

Margin

degrees

Open-Loop

Gain

-20

100

120

0.1 1 10 100 1000 10000

PIN DESCRIPTIONS (cont.)

Voltage Amplifier Gain and Phase vs Frequency Current Amplif ier Gai n and P hase v s Frequency

Gate Drive Rise and Fall Tim e Gate Drive Maximum Duty Cy cle

Multiplier Output vs Voltage on Mult Oscillator Frequency vs RSET and CT

T YPI CAL CHARACTERISTICS at T A = TJ = 2 5oC (cont.)

UC1854

UC2854

UC3854

, µA

Mult Out

µA

100

200

300

400

500

600

0 100 200 300 400 500

RMS

=1.5V

VA Out=1.25V

VA Out=2.5V

VA Out=3.5V

, µA

Mult Out

µA

100

150

200

250

0 100 200 300 400 500

VRMS=3V

VA Out=1.25V

VA Out=2V

VA Out=3V

VA Out=5V

, µA

Mult Out,

µA

100

120

140

0100 200 300 400 500

RMS

=5V

VA Out=5V

VA Out=1.5V

VA Out=3V

IAC,

Mult Out

µA

100

120

140

160

0 100 200 300 400 500

RMS

=4V

VA Out=1.25V

VA Out=2V

VA Out=3V

VA Out=4V

VA Out=5V

Multiplier Output vs Multiplier Inputs with Mult Out=0V

APPLICAT IONS INFORMATI ON

A 250W PREREG ULATO R

The circu it of Figure 1 shows a typical ap plication of the

UC3854 as a preregulator with high power factor and effi-

ciency. The assembly consists of two distinct parts, the

control circuit centering on the UC3854 and the power

section.

The p ower section is a "boo st" co nverte r, with the ind uc-

tor operating in the continuous mode. In this mode, the

duty cycle is dependent on the ratio between input and

output voltage s; also, the input current has low sw itching

frequency ripple, which means that the line noise is low.

Furt hermore, the o utput voltage must be higher than the

peak valu e of the h ighe st e xpected A C line voltage, and

all components must be rated accor dingly .

In the control section, the UC3854 provides PWM pulses

(GT Drv, Pin 16) to the power MOSFET gate. The duty

cycle of this output is simultaneously controlled by four

separ ate inputs to the chip:

INPUT PI N # FUNC TIO N

VSENSE. ..... .... .... .. ..... ...11.. ..... .. . Outp u t DC Vo ltag e

IAC... ......... ...... ......... ......6 . ..... .. .. LineVoltage Wavef or m

ISENSE/Mult Out.........4/5.......... Line Current

VRMS.............................8.......... RMS Line Voltage

Additional controls of an auxiliary nature are provided.

They are intended to protect the switching power MOS-

FET S fro m cert ain trans ie nt conditions, as follows:

INPUT PIN # FUNCTION

E NA. ....... .... .... .. ..... .... .10.... ... ... S tar t-Up De l a y

SS...............................13.......... Soft Start

PKLIM........................... 2.......... Maximum Current Limit

UC1854

UC2854

UC3854

PROTECTION INPUTS

ENA (Enable): The ENA input must reach 2.5 volts be-

fore the REF and GT Drv ou tputs are enabled. Thi s pro-

vides a means to shut down the gate in case of trouble, or

to add a time delay at power up. A hysteresis gap of

200mV is provided at this terminal to prevent erratic op-

eration. Undervoltage protection is provided directly at pin

15, where the on/off thresholds are 16V and 10V. If the

ENA input is unused, it should be pulled up to VCC

through a cu rrent limitin g resist or of 100k.

SS (Soft start): The voltage at pin 13 (SS) can reduce

the refe rence vol tage used by the error amplifier to regu-

late the output DC voltage. With pin 13 open, the refer-

ence vol tage is ty pically 7. 5V. An i nt er nal cur r ent sourc e

del iver s appr oxim ately -14µA f r om pin 13. Thus a capaci-

tor connected between that pin and ground will charge

linearly from zero to 7.5V in 0.54C seconds, with C ex-

pressed in microfarads.

PKLIM (Peak current limit): Use pin 2 to establish the

highest value of current to be controlled by the power

MOS FET. With th e r esi s t or di vider val ues sh own in Figure

1, the 0. 0V th res hold at pin 2 is rea ched wh en t he volt age

drop across the 0.25 ohm current sense resistor is

7. 5V*2k/ 10k=1.5V, cor respond ing to 6A. A bypass capaci-

t or from pi n 2 t o gr ound is r ecom m ended to fil ter out v er y

high frequency noise.

CONTROL INPUTS

VSENSE (O utput D C voltage sense): The thresh old voltage

for the VSENSE input is 7.5V and the input bias current is

typically 50nA. The values shown in Figure 1 are for an

out put voltage of 400V DC. I n t his circuit, the voltage am-

plifier operates with a constant low frequency gain for

mini m um output excursions . The 47nF fe edbac k capacitor

places a 15Hz pole in the voltage loop that prevents

120H z ripple from propagating to the i nput curr ent .

IAC (Line waveform): In order to force the line current

waveshape to follow the line voltage, a sample of the

power line voltage in waveform is introduced at pin 6. This

signal is multiplied by the output of the voltage amplifier in

the internal multiplier to generate a reference signal for

the current contr ol loop.

This input is not a voltage, but a current (hence IAC). It is

set up by the 220k a nd 910k resistive divider (see Figure

1). The voltage at pin 6 is internally held at 6V, and the

two resistors are chosen so that the current flowing into

pin 6 varies from zero (at each zero crossing) to about

400µA at the peak of the waveshape. The following for-

mulas were used to calculate these resistors:

ACpk

= 260

VAC

× √2

400µ

= 910

REF

4 = 220

(where Vpk is the peak line voltage)

ISENSE/Mult Out (L ine current): The v oltage dr op acr os s

the 0.25 ohm current-sense resistor is applied to pins 4

and 5 as shown. The current-sense amplifier also oper-

ates with high low-frequency gain, but unlike the voltage

ampli fi er, it is set up to give the cur rent-contr ol loop a very

wide bandwidth. This enables the line current to foll ow the

line v oltage as close ly a s poss ible. In the present exam-

ple, this a mplifier has a zero at about 500Hz, a nd a gain

of about 18dB thereafter.

VRMS (RMS line voltage): An important feature of the

UC3854 pr er egulat or is t hat i t can operate with a three- to-

one range of i nput li ne voltag es, cover ing every t hing from

low line in the US (85VAC) to high line in Europe

(255VAC). This is done using line feedforward, which

keeps the input power constant with varying input voltage

(assum ing c onsta nt load power ) . To do this, t he mul tiplier

divides t he li ne current by the squar e of the RM S value of

th e line v ol tage. The v oltage applied to pin 8, pr opor tiona l

to the average of the rectified line voltage (and propor-

tional to the RMS value), is squared in the UC3854, and

then used as a divisor by the multiplier block. The multi-

plier ou tpu t, at p in 5, is a current that increases with the

curre nt at pin 6 and the voltage at pins 7, and decreases

wi th the square of the voltage at pin 8.

PWM FREQUENCY: The PWM oscillator frequency in

Fig ur e 1 is 100kHz. This value i s dete rmined by CT at pin

14 and RSET at pin 12. RSET should be chosen first be-

cause it affec ts t he m ax i m um v al ue of IMULT ac cording t o

the equation:

MULT

MAX

= −3.75

SET

Thi s effec tively sets a m ax i mu m PWM - c ontrolled c ur r ent.

With RSET=15k,

MULT

MAX

= −3.75

= −250µ

Also note that the multiplier output current will never ex-

ceed twice IAC.

With the 4k r esist or from M ul t O ut t o the 0.25 ohm current

sense r esist or, t he m axim um cur r ent in t he current sense

r esistor wil l be

MAX

= −

IMULT

MAX

×4

0.25Ω = −4

Having thus selected RSET, the current sense resistor,

and the re sistor from Mul t Out to the current sense resis-

to r, calcul ate CT f or th e desir ed PWM oscil lat or fr equency

from the equation

= 1.25

SET

APPLICAT IONS INFORMATI ON (c ont. )

FIGURE 1 - Typical Application

NOTE: Boost inductor can be fabricated with ARNOLD MPP toroidal core part number A-438381-2, using a 55 turn primary and a

13 turn secondary.

UNIT RODE CORP ORAT ION

7 CONTI NENTAL BL VD. • MERRIMACK, N H 03054

TEL. (603) 424-2410  FAX (603) 424 -3460

These products contain pat ented circuitry and are sold under license f rom P ioneer Magneti cs, Inc.

Thi s diagra m depict s a c om ple te 250 Wat t Prer egulator. A t ful l load, this pr ereg ulator will exhibit a power fac tor of 0.99

at a ny power line vo lt age bet ween 80 and 260 VRMS. T his same ci r cuit can be us ed at higher power lev els with minor

modifications to the power s tage. See Design Note 39B and Application Note U-134 for further details.

UC1854

UC2854

UC3854

U DG- 92 056- 1

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-9326101M2A OBSOLETE TO/SOT L 20 TBD Call TI Call TI -55 to 125

5962-9326101MEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9326101ME

UC1854J/883B

UC1854J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1854J

UC1854J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9326101ME

UC1854J/883B

UC1854L OBSOLETE TO/SOT L 20 TBD Call TI Call TI -55 to 125

UC1854L883B OBSOLETE TO/SOT L 20 TBD Call TI Call TI -55 to 125

UC2854BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -40 to 85 UC2854BJ

UC2854DW ACTIVE SOIC DW 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854DW

UC2854DWG4 ACTIVE SOIC DW 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854DW

UC2854DWTR ACTIVE SOIC DW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854DW

UC2854DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854DW

UC2854N ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2854N

UC2854NG4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2854N

UC3854DW ACTIVE SOIC DW 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854DW

UC3854DWG4 ACTIVE SOIC DW 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854DW

UC3854DWTR ACTIVE SOIC DW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854DW

UC3854DWTR-FG4 ACTIVE SOIC DW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854DW-F

UC3854DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854DW

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UC3854N ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3854N

UC3854NG4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3854N

UC3854Q ACTIVE PLCC FN 20 46 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UC3854Q

UC3854QG3 ACTIVE PLCC FN 20 46 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UC3854Q

UC3854QTR ACTIVE PLCC FN 20 1000 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UC3854Q

UC3854QTRG3 ACTIVE PLCC FN 20 1000 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UC3854Q

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 3

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1854, UC2854, UC2854BM, UC3854 :

•Catalog: UC3854, UC2854B

•Enhanced Product: UC2854B-EP

•Military: UC2854M, UC1854

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

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