ADVANCE DATA SHEET BCM8002 Dual 1.25 GBd Transceiver General Description * * * The BCM8002 is a dual 1.25 GigaBaud (GBd) transceiver that enables scaling the performance and functionality of enterprise and service provider networks to multi-gigabit bandwidths. Manufactured in a standard single-poly lowcost CMOS process, the chip enables establishing a costeffective 2.0 Gbps Ethernet link over local fiber networks. * * * * * * * * * * Fully-integrated PLL and CDR enables individual channels to lock to the incoming data. The unique design of the VCO and CDR blocks have resulted in a very low-jitter PLL implemented in CMOS. The transmitter section accepts a 10bit wide (TBI) parallel data and serializes into a CML high speed serial data for each channel. The receiver section enables individual channels to lock to the incoming data. The recovered data is presented at the parallel outputs. The optional 8B/10B encoding and 10B/8B decoding of the PCS layer is addressed through configuration registers. On-chip diagnostics and self-testing capabilities ease system design. * * * * * * Applications The BCM8002 is fabricated in a standard 0.25 micron CMOS process and is supplied in a 256 fpBGA package. * * * * Features TMS TCK TDI TDO TRSTb IEEE 1149.1 JTAG MDIO MDC Configuration Control Server Clusters Switch-to-switch Links Wireless Access Points Cable Head-End RBIAS Ultra Low-Jitter Transmitter Equalizer at each RX REFCLK * * On-chip PLL Two Independent Transceivers Data rate of 1.0 Gb/s (channel rates of 1.25 GBd) Multiple speed reference clock of 62.5 to 125 MHz Enhanced IEEE 802.3z Ten Bit Interface (TBI) LVPECL differential reference clock Parallel-to-Serial and Serial-to-Parallel conversion 50 / 75 ohm Transmit and Receive Ports Receiver Lock to Reference mode Auto Lock-to-Reference upon loss of received signal Selectable 8B/10B encoder / decoder MDC/MDIO management interface Parallel data I/O and clocks compatible with SSTL_2 and HSTL Double Data Rate (DDR) data transfers IEEE 1149.1 (JTAG), including boundary scan for TDn & RDn Parallel or Serial loopback mode Built in Bit Error Rate Tester (BERT) Single 2.5V power supply Power less than 2.8W Clock Multiplier Unit (PLL) FIFO 8B/10B Encoder Serializer TX[9:0] TX_CLK FRST TXCKO TD0+ TD0- EWRAP RX[9:0] COMDET RX_CLK0 RX_CLK1 EN_CDET LCK_REFb Clock Recovery Word Synchronization Deserializer 10B/8B Decoder FIFO RD0+ RD0- RST Figure 1: Functional Block Diagram 8002-DS03-R 16215 Alton Parkway * P.O. Box 57013 * Irvine, California 92619-7013 * Phone: 949-450-8700 * Fax: 949-450-8710 05/22/01 Revision History REVISION Date CHANGE DESCRIPTION 8002-DS00-R 09/10/00 Initial Release. 8002-DS01-R 03/26/01 * * * * * Updated front cover General Description and Features. Updated Tables 2, 8, 22, and 23. Updated Thermal Information. Updated Ordering Information. Various text changes. 8002-DS02-R 05/09/01 Corrected PHYID LOW value to 6144h (see Table 7 on page 12). 8002-DS02-R 5/22/01 Added grounded balls to center field of package (see Figure 2 on page 7 and Section 8 "Ballout Assignment" on page 30) to reflect how the BCM8002 is designed. Broadcom Corporation P.O. Box 57013 16215 Alton Parkway Irvine, California 92619-7013 (c) 2001 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom, the pulse logo, and QAMLink are registered trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners. BCM8002 Advance Data Sheet 05/22/01 TABLE OF CONTENTS Section 1: Functional Description...................................................................................... 1 Overview ....................................................................................................................................................... 1 Global Functions .......................................................................................................................................... 1 Clock Multiplier Unit ................................................................................................................................ 1 Transceiver ................................................................................................................................................... 2 Transmitter .............................................................................................................................................. 2 Data Input FIFO ............................................................................................................................... 2 8B/10B Encoder............................................................................................................................... 2 Serial Output Buffer ......................................................................................................................... 2 Receiver .................................................................................................................................................. 2 Serial Input Receiver ....................................................................................................................... 2 Clock Recovery................................................................................................................................ 2 Signal Detect ................................................................................................................................... 3 Auto Lock to Reference ................................................................................................................... 3 Receive Line Equalization ............................................................................................................... 3 Code Word Synchronization ............................................................................................................ 3 8B/10B Decoder. ............................................................................................................................. 3 Data Output FIFO ............................................................................................................................ 3 Section 2: Hardware Signal Definitions ............................................................................. 4 Conventions ................................................................................................................................................. 4 Section 3: Pinout Diagram ..................................................................................................7 256-Pin fpBGA Diagram............................................................................................................................... 7 Section 4: Operational Description ....................................................................................9 Resetting the BCM8002 ............................................................................................................................... 9 Test Modes ................................................................................................................................................... 9 Loop Back Modes ................................................................................................................................... 9 JTAG, IEEE 1149.1................................................................................................................................. 9 Section 5: Register Summary ........................................................................................... 10 Accessing the Registers via the XMII Management Interface................................................................ 10 PHY Address ........................................................................................................................................ 10 Bro adco m Co rp or atio n Document 8002-DS03-R Page iii BCM8002 Advance Data Sheet 05/22/01 Register Programming...........................................................................................................................10 Global Registers .........................................................................................................................................11 Control Register.....................................................................................................................................11 Status Register ......................................................................................................................................12 PHY Identifier Register ..........................................................................................................................12 Configuration Register...........................................................................................................................12 PMA-Level Registers ..................................................................................................................................14 PMA Configuration Register ..................................................................................................................14 PMA Status Register .............................................................................................................................15 Receiver Equalizer Control Register 1 ..................................................................................................16 Section 6: Timing Diagrams ............................................................................................. 17 Section 7: Electrical Specifications................................................................................. 19 General Specifications ...............................................................................................................................19 PMA Interface Specifications ....................................................................................................................20 PMD Interface Specifications ....................................................................................................................24 Transmitter Electrical Specifications......................................................................................................24 Receiver Electrical Specifications..........................................................................................................26 Section 8: Ballout Assignment ........................................................................................ 30 Ballout by Ball Number ..............................................................................................................................30 Ballout by Signal Name..............................................................................................................................32 Section 9: Mechanical Information .................................................................................. 35 Section 10: Thermal .......................................................................................................... 36 Thermal Information ...................................................................................................................................36 Section 11: Ordering Information .................................................................................... 37 Device Information .....................................................................................................................................37 Bro adco m C orp or atio n Page iv Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 LIST OF FIGURES Figure 1: Functional Block Diagram.................................................................................................................i Figure 2: BCM8002 Pinout Diagram .............................................................................................................. 7 Figure 3: TBI Comma Resynchronization Timing Diagram (in phase) ........................................................ 17 Figure 4: TBI Comma Resynchronization Timing Diagram (2-bits early) .................................................... 18 Figure 5: Input / Output Valid Levels for AC Measurements ....................................................................... 20 Figure 6: Transmit Interface Timing Diagram, SDR .................................................................................... 21 Figure 7: Receiver Interface Timing Diagram SDR ..................................................................................... 22 Figure 8: Receiver Interface Timing Diagram DDR ..................................................................................... 23 Figure 9: Balanced Transmitter Test Load .................................................................................................. 24 Figure 10: Transmit Eye Diagrams at TP1 / TP2 ........................................................................................... 25 Figure 11: TD Transmit Signal Timing Diagram .......................................................................................... 26 Figure 12: Receiver Test Diagram ................................................................................................................. 26 Figure 13: Receive Eye Diagram Mask at TP3.............................................................................................. 27 Figure 14: RD Receiver Signal Timing Diagram.......................................................................................... 28 Figure 15: 256-Pin fpBGA.............................................................................................................................. 35 Bro adco m Co rp or atio n Document 8002 Page v BCM8002 Advance Data Sheet 05/22/01 LIST OF TABLES Table 1: Clock Generation ............................................................................................................................ 1 Table 2: Receiver Error / Exception Conditions ............................................................................................ 3 Table 3: Hardware Signals............................................................................................................................ 4 Table 4: Frame Format ............................................................................................................................... 10 Table 5: Control Register (Address 00h)..................................................................................................... 11 Table 6: Status Register (Address 01h) ...................................................................................................... 12 Table 7: PHY Identifier Registers (Addresses 02h and 03h........................................................................ 12 Table 8: Configuration Register (Address=10h).......................................................................................... 12 Table 9: PMAn Configuration Register (Address=11h) ............................................................................... 14 Table 10: PMAn Status Register (Address=12h, Read Only) ....................................................................... 15 Table 11: Receiver Equalizer Control Register (Address=19h) .................................................................... 16 Table 12: Absolute Maximum Ratings .......................................................................................................... 19 Table 13: Recommended Operating Conditions ........................................................................................... 19 Table 14: PMA Interface DC Specifications .................................................................................................. 20 Table 15: PMA Transmit AC Specifications, SDR......................................................................................... 21 Table 16: PMA Receive Bus AC Specification, SDR .................................................................................... 22 Table 17: PMA Receive Bus AC Specification, DDR .................................................................................... 24 Table 18: Transmitter Characteristics at TP1 / TP2 ...................................................................................... 25 Table 19: Receiver Characteristics at TP4.................................................................................................... 27 Table 20: Ballout by Ball Number.................................................................................................................. 30 Table 21: Ballout by Signal Name................................................................................................................. 32 Table 22: Basic Thermal Data....................................................................................................................... 36 Table 23: Theta-JA vs. Airflow (@2.8 W)...................................................................................................... 36 Bro adco m Co rp or atio n Document 8002-DS03-R Page vi BCM8002 Advance Data Sheet 05/22/01 S e c ti o n 1 : Fu nc t io na l D e s c r i pt i on OVERVIEW The BCM8002 is a two channel serial transceiver that supports 1.25 GigaBaud (GBd) full-duplex operation on each channel. An on-chip Phase-Locked Loop (PLL) provides clock synthesis from 62.5 or 125 MHz reference clocks. Each transmit channel serializes 10-bit (or 8 bit data with the internal 8b/10b encoder enabled) SSTL2/HSTL/LVTTL* compatible parallel data into a high-speed differential CML output. Each differential-input receiver recovers the clock and data at its serial input. After clock recovery and de-serializing, the data is delivered to a 10-bit SSTL2/HSTL/LVTTL* compatible parallel interface (8 bits with the internal 8b/10 decoder enabled). Equalization at each receiver corrects for cable and connector induced distortions. A programmable Pseudo-Random Binary Sequence (PRBS) generator facilitates self-test and BERT of each channel, without the need for external bit-generator hook-up. Internal loopback capabilities facilitate quick diagnosis of system issues. * For LVTTL implementation, please see the BCM8002 Design Guide. GLOBAL FUNCTIONS CLOCK MULTIPLIER UNIT The Clock Multiplier Unit takes the signal on the REFCLK pins and multiplies its frequency up to create the internal serial transmission clock and receive reference clock. A single ultra-low jitter Phase Locked Loop (PLL) is used to generate the transmit data rate clock and the receiver data rate reference clock. An internal PLL filter has been implemented requiring no external components. Table 1 shows the reference clock to serial channel rate relationships, using the equation below: Baud-rate = (fREFCLK / refdiv) * (vcodiv/2) Example: 1.25 = (125/2) * (40/2) Table 1: Clock Generation fREFCLK (MHz) PLL REFDIV /1=bit low /2=bit hi TCKO OUTPUT CLOCK (MHz) PARALLEL DATA RATE (MBd) SERIAL DATA RATE (Gbps) SERIAL CHANNEL BAUD RATE (GBd) 62.5 /1 125 125 1.00 1.25 125 /2 125 125 1.00 1.25 Bro adco m Co rp or atio n Document 8002-DS03-R Page 1 BCM8002 Advance Data Sheet 05/22/01 TRANSCEIVER Each transmitter takes 10 bits of data on the TXn pins and performs a parallel-to-serial conversion at the desired serial rate, producing a serial stream on the TDn outputs. Optionally, 8 bits of data can be encoded with the on-chip 8B/10B encoder, creating 10 bits that go through the parallel-to-serial conversion and are driven out on the TDn pins. TRANSMITTER Data Input FIFO. A transmitter input FIFO is provided for deskew of the external and internal clocks. The data presented on the TXn[9:0] pins can be clocked in by either the corresponding TXn_CLK pin or the TX1_CLK pin. The corresponding TX1_CLK pin is used when the corresponding configuration bit TCKSEL is active otherwise the TXn_CLK is used (default). The transmit FIFO can be reset / initialized by activating the FRST pin. The transmit FIFO should be initialized after the PLL and FIFO clocks have stabilized. If the TXn_CLK is not at the same frequency as the internal code-word rate clock, or a TXn_CLK pulse was suppressed or missing, a FIFO underrun or overrun condition might occur. When this event occurs, the FERR pin and the TFERR bit in the transceiver configuration register are set. The transmit fifo then needs to be reset with the FRST pin to clear the error condition and error bits. 8B/10B Encoder. An on-chip IEEE 802.3z clause 36.2.4 compliant 8B/10B encoder can be selected. The 8B/10B encoder is bypassed (disabled) for a transmitter when the corresponding EDEN configuration bit is inactive. When the encoder is bypassed, the data on TXn[9:0] is directly serialized, Least Significant Bit (LSB) first. The encoder for a transmitter is enabled when the corresponding EDEN configuration bit is active. The data on the corresponding TXn[7:0] pins and the TKDn pin is then encoded according to the IEEE 802.3z clause 36.2.4 8B/10B encoding rules. Serial Output Buffer. The output impedance of the transmit buffer is set by the ZSEL bit in the transceiver configuration register. When ZSEL = 0, the output impedance is nominally 50, and when ZSEL = 1, the output impedance is nominally 75. The transmit output buffer is disabled when the internal serial loop back mode is selected. The "0" state is when TDn+ < TDn- and the "1" state is when TDn+ > TDn-. RECEIVER Each receiver synchronizes its internal VCO clock to the incoming data on the RDn pins recovering the clock in the data stream. The serial data is then converted to 10-bit parallel data and a comma detector can be enabled to automatically align the code-word boundaries. The code words can then optionally be decoded with the IEEE 802.3z clause 36.2.4 compliant 10B/8B decoder. The resulting 10 or 8 bit code-words are then written into the read FIFO where all four channels can be synchronized together with the parallel code-words driven out on the RXn pins. Serial Input Receiver. The receiver must be AC-coupled (0.01 uF in + and - legs). The input impedance of the input buffer is set by an external resistor placed between the RDn pins. The input buffer is disabled when the internal serial loop back mode is selected. The "0" state is when RDn+ < RDn- and the "1" state is when RDn+ > RDn-. Clock Recovery. An independent PLL for each receiver recovers the data and a clock from the incoming data stream. To ensure that the PLL locks to the proper frequency, a lock to reference mode is provided, and is selected when LCK_REFb is active. Once the receive PLL is locked to the reference frequency and proper data is being received, LCK_REFb can be deactivated and the PLL then phase aligns to the incoming data and track the data's phase and frequency. The recovered clock and data are then passed on to the balance of the receive circuits for code-group alignment, de-serialization and channel to channel synchronization. Bro adco m C orp or atio n Page 2 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Signal Detect. The presence of a signal on the RDn pins is indicated by the SIGDET bit in the Transceiver Configuration Register. When SIGDET is active the signal coming in on the RDn is greater than 100mVppd. Auto Lock to Reference. An auto lock to reference or data mode can be enabled by setting the ALOCK bit in the transceiver configuration register. The receive PLL automatically locks to the reference upon power up, reset, in the absence of receive data or when corrupted data causes the receive PLL to become unlocked. The Receive PLL switches to locking to the incoming data after it has locked to the reference and receive data is present. In all cases when the LCK_REFb is active, the receive PLL locks to the reference clock. Receive Line Equalization. A two tap FIR (1-Z-1) equalizer is provided to open the eye for long cable or trace lengths. can be programmed to 0%, 3.25%, ..., 45% by setting the Transceiver Equalizer Register bits RTAP3-0 to 0h, 1h, ..., Fh respectively. Code Word Synchronization. Comma character detection is available to provide a consistent code-word alignment for the de-serialization process. When EN_CDETn is active, the corresponding receiver aligns the code-group of the deserialization process such that the code group containing the comma is aligned with the positive transition of RXn_CLK1 (see Figure 4, "TBI Comma Resynchronization Timing Diagram (2-bits early)," on page 18) and COM_DETn is activated. Both comma+ and comma- characters are detected. 8B/10B Decoder. An on-chip IEEE 802.3z clause 36.4.2 compliant 10B/8B decoder can be selected. The 10B/8B decoder is bypassed (disabled) for a receiver when the corresponding EDEN configuration bit is inactive. When the decoder is bypassed, the data on RXn[9:0] is directly deserialized, LSB first, to the selected RDn inputs. When the decoder is enabled for a receiver, the corresponding EDEN configuration bit is active. The data on the corresponding RXn[7:0] and RKDn pins is the deserialized data from the RDn inputs decoded according to the IEEE 802.3z clause 36.4.2 10B/8B decoding rules. When the decoder is active, the RERRn along with the COM_DETn and RKDn pins indicate when an error or an exception condition has occurred. RERRn RKDn COM_DETn Table 2: Receiver Error / Exception Conditions 0 0 0 Valid D-word received 0 0 1 Reserved 0 1 0 Valid K-word received 0 1 1 Valid K-word with imbedded comma (K28.1, K28.5, K28.7) received 1 0 0 Invalid code group received (also RX[9:0] = K28.7, violation) 1 0 1 Invalid code group with imbedded comma received 1 1 0 Reserved 1 1 1 Reserved Description Data Output FIFO. A receiver output FIFO is provided for deskew of the external and internal clocks. The data presented on the RXn[9:0] pins and the COM_DETn pin can be clocked out by either the corresponding RXn_CLK0 pin or both RXn_CLK0 and RXn_CLK1 pins. The RXn_CLK1 pin is used when the configuration bit RCKSEL is active, otherwise both RXn_CLK0 and RXn_CLK1 pins are used (default). Bro adco m Co rp or atio n Document 8002-DS03-R Page 3 BCM8002 Advance Data Sheet 05/22/01 Section 2: H ardwa re Signal Definitions CONVENTIONS SIGNAME A signal named "signame" is active high. An input signal "signame" activates / enables its function when it is put into the "high" state. An output signal "signame" indicates its status when it is driving a "high" state. SIGNAMEb A signal named "signameb", that is a signal name ending in a lower case "b" is active low. An input signal "signameb" activates / enables its function when it is put into the "low" state. An output signal "signameb" indicates its status when it is driving a "low" state. SIGNAMEn n=1 or 2 is the PMA, or channel, number. active When an active low signal is in the "low" state or when an active high signal is in the "high" state. inactive When an active low signal is in the "high" state or when an active high signal is in the "low" state. Table 3: Pin Label Hardware Signals Type Description Physical Medium Attachment (PMA) Connections per Transceiver TXn[9:0] I Parallel transmit input data TKDn I Transmit K / D code-group select, 1 = K-code group, 0 = D-code group. Shared with TXn[8]. FRSTn I Transmit FIFO ReSeT, 1=reset transmit Fifo, (synchronized internally) FERRn O Transmit FIFO ERRor, 1=under / over run occurred TXn_CLK I Transmit data clock RXn[9:0] O Parallel receive output data RKDn O Receive K / D code-group status, 1=K, 0=D code group received. Shared with RXn[8]. RERRn O Receive ERRor, 1=error. Shared with RXn[9]. COM_DETn O Comma Detect, active high. When active, indicates a comma was detected RXn_CLK0 O Receive clock 0, odd byte clock RXn_CLK1 O Receive clock 1, even byte clock EN_CDETn I Enable comma detect, active high. When active, comma detection is enabled LCK_REFbn I Lock to reference, active low. When active, the receive PLL locks to the internal transmit clock EWRAPn I Enable wrap, active hi. When active, activates the selected internal loopback mode Note: I = input; O = output; I/O = bidirectional; IPU = input w/ internal pull-up; IPD = input w/ internal pull-down; I/OPU = bidirectional w/ internal pull-up; B = bias; AO = Analog output, P = power; G = ground Bro adco m C orp or atio n Page 4 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Table 3: Pin Label Hardware Signals (Continued) Type Description Medium Connections per Transceiver RDn I Differential receive data inputs (AC couple) TDn O Differential transmit data outputs PLL and Bias Connections REFCLK I Data rate reference clock (AC couple) TXCKO O Transmit code-word rate clock out RBIAS B Analog Bias Set Resistor Managed Data Interface MDC IPD Management Data Clock MDIO I/OPU Management Data In / Out RST I Chip ReSeT, completely powers down and resets the BCM8002, (synchronized internally, make width at least 16 REF_CLKs beyond power stable) PHYAD[4:0] IPD PHY ADdress identification: the 5-bits of the PHY address field used by the Managed Data Interface. TMS IPU JTAG Mode Select TCK IPD JTAG Test Clock TDI IPU JTAG Test Data Input TDO O JTAG Test Data Output TRSTb IPU JTAG Test Reset VDDQ P SSTL/HSTL I/O power VTT P SSTL/HSTL inputs termination voltage (use regulator, typically set to VDDQ /2,) VREF P SSTL/HSTL inputs reference level (typ. VDDQ / 2, generate separately from VTT) DVDD P Digital logic power CVDD P Power for digital sections of analog macro-functions AVDD P Analog power DVSS P Digital ground AVSS P Analog ground JTAG Test Port Power Note: I = input; O = output; I/O = bidirectional; IPU = input w/ internal pull-up; IPD = input w/ internal pull-down; I/OPU = bidirectional w/ internal pull-up; B = bias; AO = Analog output, P = power; G = ground Bro adco m Co rp or atio n Document 8002-DS03-R Page 5 BCM8002 Advance Data Sheet 05/22/01 Table 3: Pin Label Hardware Signals (Continued) Type Description Factory Test TPORTPn TPORTNn TVCOUT TVCON TVCOP AO Used for factory test, leave open Note: I = input; O = output; I/O = bidirectional; IPU = input w/ internal pull-up; IPD = input w/ internal pull-down; I/OPU = bidirectional w/ internal pull-up; B = bias; AO = Analog output, P = power; G = ground Bro adco m C orp or atio n Page 6 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 S e c t i o n 3 : Pi n ou t D i ag r a m 256-PIN FPBGA DIAGRAM A B C D E F L M N P R T 16 DVSS DVSS VDDQ RX1_9 RX1_6 RX1_1 RX2_CLK1 RX2_1 RX2_6 RX2_7 VDDQ DVSS DVSS 16 15 DVSS DVSS VDDQ COM_DET1 RX1_8 VDDQ RX2_CLK0 RX2_2 RX2_8 COM_DET2 VDDQ DVSS DVSS 15 14 DVSS DVSS DVSS DVSS VDDQ DVSS RX2_0 RX2_5 RX2_9 DVSS DVSS DVSS DVSS 14 13 VTT VTT DVSS DVSS VDDQ DVSS RX2_3 RX2_4 FERR2 DVSS DVSS VTT VTT 13 12 FRST1 TX1_7 TX1_2 VREF DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS VREF TX2_2 TX2_7 FRST2 12 11 TX1_9 TX1_6 TX1_3 TX1_1 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS TX2_1 TX2_3 TX2_6 TX2_9 11 10 TX1_8 TX1_4 TX1_5 TX1_0 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS TX2_0 TX2_5 TX2_4 TX2_8 10 9 VTT VTT DVSS TX1_CLK DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS TX2_CLK DVSS VTT VTT 9 8 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS 8 7 DVDD DVDD DVDD DVDD DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVDD DVDD DVDD DVDD 7 6 TXCKO TDO EN_CDET1 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS EN_CDET2 PHYAD1 mdc 6 5 RESET LCK_REFB1 TRSTB DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PHYAD4 PHYAD3 MDIO 5 4 TCK AVSS AVSS AVSS AVSS REFCLKN REFCLKP 3 TDI CVDD AVSS AVSS CVDD CVDD 2 TMS CVDD TPORTP1 AVDD RDP1 1 EWRAP1 CVDD AVDD D A B TPORTN1 C G H J RX1_CLK1 DVSS VDDQ RX1_2 RX1_CLK0 DVSS RX1_7 RX1_4 RX1_0 FERR1 RX1_5 RX1_3 K AVDD TVCOUT RBIAS AVSS AVSS AVSS AVSS AVSS PHYAD0 4 CVDD cvdd TVCOP TVCON AVDD CVDD CVDD AVSS AVSS CVDD PHYAD2 3 AVSS TDP1 AVDD AVDD TDP2 AVSS RDP2 AVDD TPORTP2 CVDD LCK_REFB2 2 RDN1 AVSS TDN1 AVDD AVDD TDN2 AVSS RDN2 AVDD TPORTN2 CVDD EWRAP2 1 E F G H J K L M N Figure 2: P R T BCM8002 Pinout Diagram Bro adco m Co rp or atio n Document 8002-DS03-R Page 7 BCM8002 Advance Data Sheet 05/22/01 Bro adco m C orp or atio n Page 8 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 S e c t i o n 4 : O p e r a t io n a l D e s c r i pt i on RESETTING THE BCM8002 A Reset pin is used to initialize all circuits. After power has come up, the RESET signal needs to stay on for at least 16 REFCLK cycles. RESET puts all digital blocks into a reset or known state and initializes all analog blocks. Additionally, each transceiver can be independently reset / powered down by setting the RESET bit in the corresponding transceiver configuration register. After reset, the TX PLL goes through a lock sequence to REF_CLK. Once the TX PLL achieves stable lock (about 6 usec), it resets the RXs (including the RX PLL). The RX PLLs then go through a lock sequence to lock to the TX clock. Once this is achieved, the RX PLLs are switched to the RX data and go through a new lock sequence. A bit (ALOCK) can be set to have the RX PLLs lock to the TX clock whenever they lose lock to data, this allows a quicker lock to data, when the data comes back, than letting the RX PLL run to the end of it's range. Another bit (LCK_REF) can force the RX PLL to lock the TX clock. TEST MODES LOOP BACK MODES There are two loopback modes to help facilitate system testing and debugging. The loopback mode is entered when the EWRAP signal is activated. There are two loopback modes that can be selected: 1) - When the PWRAP bit in the transceiver configuration register is inactive, a serial loopback mode is selected, where the serial transmit data is internally feed back into the serial receiver. 2) - When the PWRAP bit in the transceiver configuration register is active, a parallel loopback mode is selected, where the parallel received data on RXn[0:9] is internally feed back as the parallel data for TXn[0:9]. This mode could be used as a repeater function where the serial input data is resynchronized to the reference clock and transmitted back out as serial transmit data. This effectively removes the jitter on the serial receive data, opening up the re-transmitted eye diagram. CAUTION: For parallel loopback mode, it is assumed that the transmitter and receiver are frequency locked, i.e. the clock source for the incoming RDn data is the same clock source as for the transmit PLL reference clock. JTAG, IEEE 1149.1 The BCM8002 JTAG interface is compliant with the IEEE 1149.1 requirements and is provided to test the connectivity of the pins on the BCM8002. The Test Access Port (TAP) provides access to the BCM8002's test logic. When TRST is active the TAP is put into the initialization state. All digital pins as well as all TDn and all RDn pins are connected to the JTAG boundary scan register, the only pins not connected to the boundary scan register is the analog bias pin RBIAS. The three required instructions, Bypass, Extest, and Sample/Preload, are implemented. Bro adco m Co rp or atio n Document 8002-DS03-R Page 9 BCM8002 Advance Data Sheet 05/22/01 Sec t ion 5 : Regis ter Summa r y ACCESSING THE REGISTERS VIA THE XMII MANAGEMENT INTERFACE PHY ADDRESS The BCM8002 has a unique address for the management set, using the PHYAD[4:0] pins. The pins are latched on the trailing edge of the RESET pin. Every time an MDIO write or read operation is executed, the BCM8002 compares the PHY address with its own PHY address. The operation is executed only when the PHYAD matches the internal PHY address. REGISTER PROGRAMMING The registers are serially written-to and read-from using a common pair of MDIO and MDC pins. A clock must be provided to the BCM8002 at a rate of 0-25 MHz through the MDC pin. The serial data is communicated on the MDIO pin. Every MDIO bit must have the same period as the MDC clock. The MDIO bits are latched on the rising edge of the MDC clock. Table 4 shows the fields in read or write instruction frames. Table 4: Frame Format Operation PRE ST OP PHYAD REGAD TA DATA IDle Direction READ 1 ... 1 01 10 AAAAA nnnnn ZZ Z0 Z ... Z D ... D Z Z Driven to BCM8002 Driven by BCM8002 WRITE 1 ... 1 01 01 AAAAA nnnnn 10 D ... D Z Driven to BCM8002 Preamble (PRE) - Thirty two consecutive "1" bits must be sent through the MDIO pin to the BCM8002 to signal the beginning of an instruction. Fewer than 32 "1" bits cause the remainder of the instruction to be ignored. Start of Frame (ST) - A "01" pattern indicates that the start of the instruction follows. Operation Code (OP) - A READ instruction is indicated by "10", while a WRITE instruction is indicated by "01". PHY Address (PHYAD) - A 5-bit PHY Address follows, with the Most Significant Bit (MSB) transmitted first. Register Address (REGAD) - A 5-bit Register Address follows, with the MSB transmitted first. The register map of the BCM8002, containing register addresses and bit definitions, are provided on the following pages. Turnaround (TA) - The next two bit times are used to avoid contention on the MDIO pin when a Read operation is performed. For a Write operation, "10" must be sent to the BCM8002 chip during these two bit times. For a Read operation, the MDIO pin must be placed into High-Impedance during these two bit times. The chip drives the MDIO pin to "0" during the second bit time. Data - The last 16 bits of the frame are the actual data bits. For a write operation, these bits are sent to the BCM8002, whereas, for a read operation, these bits are driven by the BCM8002. In either case, the MSB is transmitted first. When writing to the BCM8002, the data field bits must be stable 10 ns before the rising-edge of MDC, and must be held valid for 10 ns after the rising edge of MDC. When reading from the BCM8002, the data field bits are valid after the rising-edge of MDC until the next rising-edge of MDC. Idle - A high impedance state of the MDIO line (Z represents a bit of tri-state). The MDIO tri-state driver is disabled and the pull-up resistor pulls the MDIO line to logic "1". Bro adco m C orp or atio n Page 10 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Following are two examples of write and read instructions: Ex. 1: In order to put the BCM8002 into the loopback state, the following write instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0101 AAAAA 00000 10 0100 0000 0000 0000 Ex. 2: In order to determine the link status, the following read instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0110 00000 00001 ZZ ZZZZ ZZZZ ZZZZ ZZZZ For the read operation, the BCM8002 drives the MDIO line during the TA and Data fields (the last 17 bit times). GLOBAL REGISTERS When writing to reserved bits, always write a 0 value, and when reading from these bits, ignore the output value. Never write any value to an undefined register address. CONTROL REGISTER Table 5: BIT NAME R/W Control Register (Address 00h) DESCRIPTION DEFAULT 15 Reset R/W 1 = Reset 0 = Normal operation 0 14 Loopback R/W 1 = Loopback 0 = Normal operation 0 13:12 Reserved N/A 11 Power Down R/W 1= Power down state 0 = Normal operation 0 10 Isolate R/W 1 = Isolate 0 = Normal operation 0 9:0 Reserved N/A 0 0 Reset - All registers are put into their default state, and all circuits are reset. This bit is automatically cleared after 16 refclk cycles. Loopback - Each transmit serial output is fed back to its corresponding receiver serial input. All transmitter output drivers are turned off. Power Down - All analog blocks are powered down and all VCOs are off. The register values remain unchanged. Isolate - All outputs are tri-stated and the BCM8002 does not respond to any signals on the inputs. All transmitter output drivers put out a constant 0. Bro adco m Co rp or atio n Document 8002-DS03-R Page 11 BCM8002 Advance Data Sheet 05/22/01 STATUS REGISTER Table 6: BIT NAME R/W Status Register (Address 01h) DESCRIPTION DEFAULT 15:3 Reserved NA 0 2 Reserved NA 0 1:0 Reserved NA 0 PHY IDENTIFIER REGISTER Table 7: PHY Identifier Registers (Addresses 02h and 03h BIT NAME R/W DESCRIPTION VALUE 15:0 MII Address 00010 R PHYID HIGH 0040h 15:0 MII Address 00011 R PHYID LOW 6144h Broadcom Corporation has been issued an Organizationally Unique Identifier (OUI) by the IEEE. It is a 24-bit number, 00-10-18, expressed as hex values. That number, along with the Broadcom Model Number for the BCM8002 part, 1Ch, and Broadcom Revision number, 00h, is placed into two MII Registers. The translation from OUI, Model Number and Revision Number to PHY Identifier Register occurs as follows: PHYID HIGH [15:0] = OUI[21:6] PHYID LOW [15:0] = OUI[5:0] + MODEL[5:0] + REV[3:0] CONFIGURATION REGISTER Table 8: BIT NAME R/W Configuration Register (Address=10h) DESCRIPTION 1 = Shared TX PLL is locked to the reference clock 0 = Shared TX PLL is not locked DEFAULT 15 PLLOCK R 14:12 Reserved NA 0 11 Reserved NA 0 10 PMA[2] R/W 1 = Selects the PMA2 register set 0 = BCM8002 quad level selected if all PMA[n] bits = 0 0 9 PMA[1] R/W 1 = Selects the PMA1 register set 0 = BCM8002 quad level selected if all PMA[n] bits = 0 0 8 Reserved NA 0 7 Reserved NA 0 6 Reserved NA 0 5 HSTL R/W 1 = Specified pads must be set to 1.5V 0 = Specified pads must be set to 2.5V 0 0 Bro adco m C orp or atio n Page 12 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Table 8: Configuration Register (Address=10h) (Continued) BIT NAME R/W DESCRIPTION 1= Specified pads are disabled and specified internal bits are used 0 = Internal bits are disabled and specified pads are used DEFAULT 4 ICTRL R/W 0 3 Reserved NA 2 VCOBYP R/W 1 = REFCLK input is used as the internal channel bit rate clock 0 = Shared PLL generates the internal channel bit rate clock 0 1 Reserved (was VCODIV) R/W (Needs a "1" written in Revs A0 - A3) 0 0 REFDIV R/W 1 = Reference clock divided by 2 is sent to the PLL's phase detector 0 0 = Reference clock divided by 1 is sent to the PLL's phase detector 0 PLLOCK - When active, the shared PLL is locked to the reference clock. When inactive, the shared PLL is not locked. PMA(2) - When active, PMA(2) selects PMA2's register set to be accessed for REGAD=11h-1Fh. During a write operation more than one PMA may be selected at a time. During a read operation, only one PMA should be selected at a time, otherwise unknown data could be read. When all PMA(n) are inactive, then the BCM8002 quad level registers are selected. PMA(1) - When active, PMA(1) selects PMA1's register set to be accessed for REGAD=11h-1Fh. During a write operation more than one PMA may be selected at a time. During a read operation, only one PMA should be selected at a time, otherwise unknown data could be read. When all PMA(n) are inactive, then the BCM8002 quad level registers are selected. HSTL - When active, pads TXn, FERRn, FRSTn, TXn_CLK, RXn, COM_DETn, RXn_CLK0, RXn_CLK1 are HSTL pads and VDDQ must be set to 1.5V with VTT and VREF = VDDQ / 2. When inactive, pads TXn, FERRn, FRSTn, TXn_CLK, RXn, COM_DETn, RXn_CLK0, RXn_CLK1 are SSTL_2 pads and VDDQ must be set to 2.5V with VTT and VREF = VDDQ / 2. Note: No damage will occur from the part resetting to SSTL when configured externally for HSTL. ICTRL - When active, pads EN_CDET, LCK_REFb and EWRAP are disabled and the internal bits, CDETEN, WRAPEN & LCKREF in each of the Transceiver Configuration Registers, are used to configure each transceiver. When inactive, the internal bits, CDETEN, WRAPEN & LCKREF in each of the Transceiver Configuration Registers, are disabled and pads EN_CDET, LCK_REFb and EWRAP are used to configure each transceiver. VCOBYP - When active, the REFCLK input is used as the internal channel bit rate clock. When inactive, normal operation, the shared PLL generates the internal channel bit rate clock. REFDIV - When active, the reference clock divided by 2 is sent to the shared PLL's phase detector (used for a 125 MHz REFCLK). When inactive, the reference clock divided by 1 is sent to the shared PLL's phase detector (used for a 62.5 MHz REFCLK ). Bro adco m Co rp or atio n Document 8002-DS03-R Page 13 BCM8002 Advance Data Sheet 05/22/01 PMA-LEVEL REGISTERS To access a PMA's registers, the corresponding PMA select bit in the Quad Level Configuration Register (Address=10h) must be set. When writing to reserved bits, always write a 0 value, and when reading from these bits, ignore the output value. Never write any value to an undefined register address. PMA CONFIGURATION REGISTER Table 9: BIT NAME R/W PMAn Configuration Register (Address=11h) DESCRIPTION DEFAULT 15:12 Reserved NA 0 11 ALOCK R/W 1 = Receiver automatically locks to the reference clock 0 = Automatic switch is disabled 10 RCKSEL R/W 1 = RCKSEL selects RX_CLK0 to clock rx parallel data out 0 0 = RXn_CLK0 and RXn_CLK1 are used to clock rx parallel data out 9 TCKSEL R/W 1 = TCKSEL selects TX(1)_CLK to clock in the TXn<9:0> data 0 = TXn_CLK is used to clock in the TXn<9:0> data 0 8 PWRAP R/W 1 = Parallel loopback mode is selected when WRAPEN is active 0 = Serial loopback mode is selected when WRAPEN is active 0 7 ZSEL R/W 1 = Transmit serial ports have a 75 ohm single-ended impedance 0 = Transmit serial ports have a 50 ohm single-ended impedance 0 6 RESERVED R/W Reserved 0 5 EDEN R/W 1 = Enables internal transmitter encoder and receiver decoder 0 = Bypasses internal transmitter encoder and receiver decoder 0 4 CDETEN R/W 1 = Enables comma detection 0 = Disables comma detection 0 3 WRAPEN R/W 1 = Enables selected wrap (loopback) mode (serial or parallel) 0 = Enables normal transmit and receive mode 0 2 LCKREF R/W 1 = Receiver PLL locks to the internal global transmit clock 0 = Receive PLL phase locks to the incoming receive data stream 0 1 PWRDWN R/W 1 = Selected PMA is put into the power-down state 0 = Selected PMA is in its normal operational mode 0 0 RESET R/W 1= Transmitter and receiver are completely powered down 0 = Transmitter and receiver are operational 0 0 ALOCK - When active, the receiver automatically locks to the reference clock when there is no signal on the RDSP/N inputs, and switches back to locking and tracking the receive data when there is a signal on the RDSP/N inputs. When inactive, automatic switch between locking to the reference clock and the receive data is disabled. RCKSEL - When active, RCKSEL selects RX_CLK0 to clock out, at the code group rate, the RXn<9:0> data. One code group per rising edge of RXn_CLK0 is clocked out on RX<9:0>. RXn_CLK1 is driven low. When inactive, RXn_CLK0 and RXn_CLK1 are used to clock out, at half the code group rate, the RXn<9:0> data. One code Bro adco m C orp or atio n Page 14 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 group per each rising edge of RXn_CLK0 and RXn_CLK1 is clocked out on RXn<9:0>. TCKSEL - When active, TCKSEL selects TX1_CLK to clock in the TXn<9:0> data on all four channels. When inactive, TXn_CLK is used to clock in the TXn<9:0> data. PWRAP - When active, the parallel loopback mode is selected when WRAPEN is active. Parallel loopback takes the output of the receive fifo into the input of the transmit fifo of the corresponding transmitter. When inactive, the serial loopback mode is selected when WRAPEN is active. Serial loopback takes the input to the transmit buffer as the output of the receive buffer. Both transmit and receive buffers are turned off. ZSEL - When active, the transmit serial ports have a 75 ohm single-ended impedance. When inactive, the transmit serial ports have a 50 ohm single-ended impedance. EDEN - When active, the internal 8B/10B encoder for the transmitter and decoder for the receiver is enabled. When inactive, the internal 8B/10B encoder for the transmitter and the internal 8B/10B decoder for the receiver are bypassed. CDETEN - When active, along with the ICTRL bit in the Global Configuration register active, enables comma detection. When inactive, along with ICTRL bit in the Global Configuration register active, disables comma detection. WRAPEN - When active, along with the ICTRL bit in the Global Configuration register active, the selected wrap (loopback) mode (serial or parallel) is enabled. When inactive, along with ICTRL bit in the Global Configuration register active, normal transmit and receive mode is enabled. LCKREF - When active, along with the ICTRL bit in the Global Configuration register active, the receiver PLL locks to the internal global transmit clock. When inactive, along with ICTRL bit in the Global Configuration register active, the receive PLL attempts to phase lock to the incoming receive data stream on the RDn+/- pins. PWRDWN - When active, the selected PMA is put into the power-down state. All analog blocks are powered down, all clocks are off. The register values remain unchanged. When inactive, the selected PMA is in its normal operational mode. RESET - When active the transmitter and receiver are completely powered down. When inactive the transmitter and receiver are operational. PMA STATUS REGISTER Table 10: BIT NAME R/W PMAn Status Register (Address=12h, Read Only) DESCRIPTION DEFAULT 15:3 Reserved NA 0 2 TFERR R 1 = An over-run or under-run occurred in the transmit FIFO 0 = There are no error conditions from the transmit FIFO 0 1 SIGDET R 1 = Indicates there is a signal on the RDSP/N inputs 0 = Indicates there is no signal on the RDSP/N inputs 0 0 RXLOCK R 1 = Receive PLL is locked to the TX reference or RX data 0 = Receive PLL is not locked 0 TFERR - When active, there was an over run or under run in the transmit FIFO. When inactive, there are no error conditions from the transmit fifo. SIGDET - When active, indicates there is a signal on the RDSP/N inputs. When inactive, indicates there is no signal on the RDSP/N inputs. RXLOCK - When active, the receive PLL is locked to either the internal TX clock (see ALOCK and LCK_REF bit descriptions) or to the incoming RX serial data stream. When inactive, the receive PLL is not locked. Bro adco m Co rp or atio n Document 8002-DS03-R Page 15 BCM8002 Advance Data Sheet 05/22/01 RECEIVER EQUALIZER CONTROL REGISTER 1 Table 11: BIT NAME R/W Receiver Equalizer Control Register (Address=19h) DESCRIPTION DEFAULT 15 Reserved NA 0 14 EQEN R/W 1 = Receive FIR tap automatically adapts to incoming signal 0 = Receive FIR tap is set by the value in the RTAP bits 1 13 RTAP[5] R/W Sets the amount of receive equalization. 1 12 RTAP[4] R/W Sets the amount of receive equalization. 0 11 RTAP[3] R/W Sets the amount of receive equalization. 0 10 RTAP[2] R/W Sets the amount of receive equalization. 1 9 RTAP[1] R/W Sets the amount of receive equalization. 0 8 RTAP[0] R/W Sets the amount of receive equalization. 1 7:0 Reserved NA 0Fh EQEN - When active, the receive FIR tap automatically adapts to the incoming signal on RDSP/N. When inactive, the receive FIR tap is set by the value in the RTAP bits. RTAP[5] - Sets the amount of receive equalization. RTAP[4] - Sets the amount of receive equalization. RTAP[3] - Sets the amount of receive equalization. RTAP[2] - Sets the amount of receive equalization. RTAP[1] - Sets the amount of receive equalization. RTAP[0] - Sets the amount of receive equalization. Bro adco m C orp or atio n Page 16 Document 8002-DS03-R RX COM_DET RX_CLK0 code-group -3 Trclat = 20-bits Broadco m C or por ati on code-group 1 code-group 3 Comma, K28.5 code-group 2 code-group -1 code-group 1 code-group -2 Comma, K28.5 Figure 3: TBI Comma Resynchronization Timing Diagram (in phase) Trclat = 20-bits code-group -4 code-group -1 Se cti on 6: T im in g Di agr ams code-group -2 code-group -5 code-group -3 RX_CLK1 RD+/- Document 8002-DS03-R 05/22/01 Advance Data Sheet Page 17 BCM8002 Page 18 BCM8002 RX COM_DET RX_CLK0 Figure 4: code-group -2 Corrupted data code-group -1 code-group 2 Trclat = 22-bits code-group 1 Broadco m C or por ati on TBI Comma Resynchronization Timing Diagram (2-bits early) Trclat = 20-bits code-group -3 over lap code-group -1 Comma, K28.5 code-group -4 code-group -2 code-group -5 code-group -3 RX_CLK1 RD+/- Comma, K28.5 code-group 3 Document 8002-DS03-R code-group 1 05/22/01 Advance Data Sheet BCM8002 Advance Data Sheet 05/22/01 Sec t ion 7: Ele ctrica l Specifications GENERAL SPECIFICATIONS Table 12: Symbol Absolute Maximum Ratingsa Parameter Min Typ Max Units VDD Supply Voltage GND-0.3 3.3 V VI Input Voltage, all signal inputs GND-0.3 VDD+0.3 V II Input Current, all signal inputs (SSTL/HSTL depends on VTT) 10 mA TSTG Storage temperature 125 o VESD Electrostatic Discharge 2000 V -40 C a. These specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operations at absolute maximum conditions for extended periods may adversely affect long-term reliability of the device. Table 13: Recommended Operating Conditions Symbo l Parameter Conditions 5% Min VDD Power supply voltage IDD Power Supply Current PD Power Dissipation FREF REFCLK Frequency 62.5 REFCLK Accuracy -100 RBIAS RBIAS Value 2.38 Typ 2.5 Pd(max) @ VDD=Max, Pd(typ) @ VDD=Typ 1% resistor to ground - 1.24K Max Units 2.62 V 1100 mA 2.5 W 125 MHz 100 ppm Bro adco m Co rp or atio n Document 8002-DS03-R Page 19 BCM8002 Advance Data Sheet 05/22/01 PMA INTERFACE SPECIFICATIONS Inputs Outputs Vih Voh Vil Vol Tr Tf Figure 5: Input / Output Valid Levels for AC Measurements Table 14: Symbol Parameter PMA Interface DC Specifications Conditions Min Typ Max Units PINS: TX[9:0], TX_CLK, FRST (SSTL_2 compliant inputs, have 50 Ohm terminators to VTT) VIH Input High Voltage Vref+0.18 VDDQ+0.3 V VIL Input Low Voltage -0.3 Vref-0.18 V IIH Input High Current IOVDD = Max, Vin = IOVDD 1 A IIL Input Low Current IOVDD = Max, Vin = 0V 1 A CIN Input Capacitance 1.4 pf PINS: EN_CDET, EWRAP, LCK_REFb VIH Input High Voltage 2.0 VDD+0.5 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = Max, Vin = VDD 1 A IIL Input Low Current VDD = Max, Vin = 0V 1 A CIN Input Capacitance 1.5 pf PINS: RX[9:0], RX_CLK0, RX_CLK1, COM_DET, FERR (SSTL_2 compliant outputs) VOH Output High Voltage Ioh = -7.6mA, VDDQ = min VOL Output Low Voltage Iol = 7.6mA, VDDQ = max TR Rise Time 1.5 ns TF Fall Time 1.5 ns 2.0 V 0.4 V * For information on interfacing with LVTTL, please refer to the Application Note. Bro adco m C orp or atio n Page 20 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 TX_CLK Tperiod TX[9:0] VALID DATA 0 VALID DATA 2 VALID DATA 1 Tsetup Thold TD+/- abcde i fgh j abcde i fgh j abcde i fgh j Ttrlat Figure 6: Table 15: Symbol Parameter DATA 0 DATA 1 Transmit Interface Timing Diagram, SDR PMA Transmit AC Specifications, SDR Conditions Min Typ Max Units TPERIOD TX_CLK period TSETUP Data setup to rising TX_CLK 500 ps THOLD Data hold from rising TX_CLK 500 ps TDUTY TX_CLK duty cycle 45 65 % TTRLAT TX to TD latency 7 8.5 bits 8.0 ns Bro adco m Co rp or atio n Document 8002-DS03-R Page 21 BCM8002 Advance Data Sheet 05/22/01 RX_CLK1 (May Toggle) VALID DATA 1 RX[9:0] COMMA code-group VALID DATA 2 Tsetup COM_DET Thold RX_CLK0 Symbol "0" Figure 7: Receiver Interface Timing Diagram SDR Table 16: PMA Receive Bus AC Specification, SDR Parameter Conditions Min Typ Max Units For PMAn Reg(11h) bit 10 "RCKSEL" = 1 TFREQ RXn_CLK frequency TDRIFT RXn_CLK drift rate TPERIOD 125 MHz 0.2 s/ MHz RXn[9:0] setup before rising RXn_CLK 1200 ps THOLD RXn[9:0] hold after RXn_CLK rising 800 ps TDUTY RXn_CLK duty cycle 45 65 % TRCLAT RD to RX latency 14 16 bits Time to drift from 126MHz to 127MHz or 120MHz to 119MHz or 63.5MHz to 64.5MHz or 60MHz to 59MHz after lock was established. Bro adco m C orp or atio n Page 22 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 RX_CLK1 RX[9:0] Tsetup VALID DATA 1 COMMA code-group VALID DATA 2 Tsetup Tsetup Thold COM_DET Thold RX_CLK0 Ta-b Figure 8: Receiver Interface Timing Diagram DDR Bro adco m Co rp or atio n Document 8002-DS03-R Page 23 BCM8002 Advance Data Sheet 05/22/01 Table 17: Symbol PMA Receive Bus AC Specification, DDR Parameter Conditions Min Typ Max Units For PMAn Reg(11h) bit 10 "RCKSEL" = 0 TFREQ RXn_CLK frequency TDRIFT RXn_CLK drift rate TSETUP 62.5 MHz 0.2 s/ MHz RXn[9:0] setup before rising or falling RXn_CLK 1200 ps THOLD RXn[9:0] hold after RXn_CLK rising or falling 800 ps TDUTY RXn_CLK duty cycle 45 65 % TA-B RXn_CLK skew 7.5 8.5 ns Time to drift from 126MHz to 127MHz or 120MHz to 119MHz or 63.5MHz to 64.5MHz or 60MHz to 59MHz after lock was established. Channel Rate = 1.25GBd PMD INTERFACE SPECIFICATIONS TRANSMITTER ELECTRICAL SPECIFICATIONS Transmit Network 68nFd + TD+ - TD- 68nFd 75 1%/ 50 1% + - TP1 75 1%/ 50 1% TP2 Figure 9: Balanced Transmitter Test Load Bro adco m C orp or atio n Page 24 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Normalized Eye Diagram Absolute Eye Diagram 1.1 1000 Differential Amplitude (mVppd) 1.0 Normalized Amplitude 0.8 0.5 0.2 550 0 550 0.0 -0.1 0.0 -1000 0.14 0.66 0.34 0.86 1.0 0.0 0.14 0.66 0.34 0.86 1.0 Normalized Time (Unit Interval) Normalized Time (Unit Interval) Figure 10: Transmit Eye Diagrams at TP1 / TP2 Table 18: Transmitter Characteristics at TP1 / TP2 Symbol Parameter Conditions Min Typ CKTOL1 Clock Tolerance FSIG1 Nominal Signalling Speed 1.25 GBd VOD1 Differential Output Amplitude 1000 mVppd VOO1 Differential Output Off Voltage PMDn powered-down or EWRAP = 1, etc. TRF1 Rise / Fall Time 20% - 80% TDS11 Differential Skew TOVS1 TUDS1 -100 Max +100 Units ppm 170 mVppd 100 ps T(50% rising / falling) of TD+ - T(50% falling / rising) of TD- 25 ps Overshoot amount over the average amplitude of the driving "1" or "0" value. 10 % Undershoot amount under the average amplitude of the driving "1" or "0" value. 20 % 85 Bro adco m Co rp or atio n Document 8002-DS03-R Page 25 BCM8002 Advance Data Sheet 05/22/01 Table 18: Transmitter Characteristics at TP1 / TP2 Symbol TJIT1 Parameter peak-to-peak Jitter Conditions Min Typ Total jitter = random jitter + deterministic jitter peak-to-peak = 7 (14) Max 0.15 120 Units UIa ps a. UI (Unit Interval) = 1 / Fsig. Tovs TD+/- Tuds Vod 50% Tuds Tovs Tds Tds Figure 11: TD Transmit Signal Timing Diagram RECEIVER ELECTRICAL SPECIFICATIONS Receive Network + + RD+ - - RD- TP4 TP3 Figure 12: Receiver Test Diagram Bro adco m C orp or atio n Page 26 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Differential Amplitude (mVppd) 1000 200 0 -200 -1000 0.0 0.3 0.5 0.7 1.0 Normalized Time (Unit Interval) Figure 13: Receive Eye Diagram Mask at TP3 Table 19: Symbol Parameter Receiver Characteristics at TP4 Conditions CKTOL4 Clock Tolerance FSIG4 Nominal Signalling Speed VIS4 Differential Input Sensitivity ZI4F Input Impedance, 50 mode Through Connectiona ZI4S Input Impedance, 75 mode Through Connection At Termination TDS4 Differential Skew T(50% rising / falling) of TD+ to T(50% falling / rising) of TD- Min Typ -100 Max +100 1.25 200 At Terminationb Units ppm GBd 2000 mVppd 80 93 100 100 120 107 120 140 150 150 180 160 0.21 UIc Bro adco m Co rp or atio n Document 8002-DS03-R Page 27 BCM8002 Advance Data Sheet 05/22/01 Table 19: Symbol TJIT4 Receiver Characteristics at TP4 Parameter Conditions peak-to-peak Jitter Tolerance Total jitter tolerance = random jitter + deterministic jitter: peak-to-peak = 7 (14) Min Typ Max 0.749 Units UI a. TDR rise time = 85ps, exception window = 700ps. Within the exception window no single impedance excursion shall exceed the "through connection" impedance tolerance for a period of twice the TDR rise time. b. The input impedance at TP3 shall be recorded 4.0ns following the reference location determined by an open connector between TP3 and TP4. c. UI (Unit Interval) = 1 / Fsig. RD Vis 50% Tds Figure 14: Tds RD Receiver Signal Timing Diagram Bro adco m C orp or atio n Page 28 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Bro adco m Co rp or atio n Document 8002-DS03-R Page 29 BCM8002 Advance Data Sheet 05/22/01 S e c t io n 8: Ba l l ou t A s s ig nm e n t BALLOUT BY BALL NUMBER Table 20: Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 Signal Name EWRAP1 TMS TDI TCK RESET TXCKO DVDD DVSS VTT TX1_8 TX1_9 FRST1 VTT DVSS DVSS DVSS CVDD CVDD CVDD AVSS LCK_REFB1 TDO DVDD DVSS VTT TX1_4 TX1_6 TX1_7 VTT DVSS DVSS DVSS RESERVED RESERVED AVSS AVSS TRSTB EN_CDET1 Ball C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 Ballout by Ball Number Signal Name DVDD DVSS DVSS TX1_5 TX1_3 TX1_2 DVSS DVSS VDDQ VDDQ AVDD AVDD AVSS AVSS DVSS DVSS DVDD DVSS TX1_CLK TX1_0 TX1_1 VREFL DVSS DVSS COM_DET1 RX1_9 RDN1 RDP1 CVDD AVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS Ball E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 Signal Name FERR1 RX1_7 RX1_8 RX1_6 AVSS AVSS CVDD REFCLKN DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS RX1_5 RX1_4 RX1_2 RX1_1 TDN1 TDP1 CVDD REFCLKP DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS RX1_3 RX1_0 RX1_CLK0 RX1_CLK1 AVDD AVDD Bro adco m Co rp or atio n Page 30 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Ball H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 Signal Name RESERVED AVDD DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS VDDQ VDDQ DVSS DVSS AVDD AVDD RESERVED RESERVED DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS VDDQ VDDQ TDN2 TDP2 AVDD RBIAS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS RX2_3 RX2_0 RX2_CLK0 RX2_CLK1 Ball L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 Signal Name AVSS AVSS CVDD AVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS RX2_4 RX2_5 RX2_2 RX2_1 RDN2 RDP2 CVDD AVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS FERR2 RX2_9 RX2_8 RX2_6 AVDD AVDD AVSS AVSS DVSS DVSS DVDD DVSS TX2_CLK TX2_0 TX2_1 VREFR DVSS DVSS Ball N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Signal Name COM_DET2 RX2_7 RESERVED RESERVED AVSS AVSS PHYAD4 EN_CDET2 DVDD DVSS DVSS TX2_5 TX2_3 TX2_2 DVSS DVSS VDDQ VDDQ CVDD CVDD CVDD AVSS PHYAD3 PHYAD1 DVDD DVSS VTT TX2_4 TX2_6 TX2_7 VTT DVSS DVSS DVSS EWRAP2 LCK_REFB2 PHYAD2 PHYAD0 MDIO MDC DVDD DVSS VTT TX2_8 TX2_9 FRST2 Bro adco m Co rp or atio n Document 8002-DS03-R Page 31 BCM8002 Advance Data Sheet 05/22/01 Ball T13 T14 T15 T16 Signal Name VTT DVSS DVSS DVSS BALLOUT BY SIGNAL NAME Table 21: Signal Name Ball Ballout by Signal Name Signal Name Ball Signal Name Ball AVDD D1 COM_DET2 N15 DVSS C14 AVDD D2 CVDD B1 DVSS C8 AVDD H1 CVDD B2 DVSS C9 AVDD H2 CVDD B3 DVSS D13 AVDD H4 CVDD E3 DVSS D14 AVDD J1 CVDD F3 DVSS D5 AVDD J2 CVDD G3 DVSS D6 AVDD K3 CVDD L3 DVSS D8 AVDD N1 CVDD M3 DVSS E5 AVDD N2 CVDD R1 DVSS E6 AVSS B4 CVDD R2 DVSS E7 AVSS C3 CVDD R3 DVSS E8 AVSS C4 DVDD A7 DVSS E9 AVSS D3 DVDD B7 DVSS E10 AVSS D4 DVDD C7 DVSS E11 AVSS E4 DVDD D7 DVSS E12 AVSS F1 DVDD N7 DVSS F5 AVSS F2 DVDD P7 DVSS F6 AVSS L1 DVDD R7 DVSS F7 AVSS L2 DVDD T7 DVSS F8 AVSS L4 DVSS A14 DVSS F9 AVSS M4 DVSS A15 DVSS F10 AVSS N3 DVSS A16 DVSS F11 AVSS N4 DVSS B14 DVSS F12 AVSS P3 DVSS B15 DVSS G5 AVSS P4 DVSS B16 DVSS G6 AVSS R4 DVSS B8 DVSS G7 COM_DET1 D15 DVSS C13 DVSS G8 Bro adco m Co rp or atio n Page 32 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Signal Name Ball Signal Name Ball Signal Name Ball DVSS G9 DVSS L10 LCK_REFB2 T2 DVSS G10 DVSS L11 MDC T6 DVSS G11 DVSS L12 MDIO T5 DVSS G12 DVSS M5 PHYAD0 T4 DVSS H5 DVSS M6 PHYAD1 R6 DVSS H6 DVSS M7 PHYAD2 T3 DVSS H7 DVSS M8 PHYAD3 R5 DVSS H8 DVSS M9 PHYAD4 P5 DVSS H9 DVSS M10 RBIAS K4 DVSS H10 DVSS M11 RDN1 E1 DVSS H11 DVSS M12 RDN2 M1 DVSS H12 DVSS N13 RDP1 E2 DVSS H15 DVSS N14 RDP2 M2 DVSS H16 DVSS N5 REFCLKN F4 DVSS J5 DVSS N6 REFCLKP G4 DVSS J6 DVSS N8 RESERVED C1 DVSS J7 DVSS P13 RESERVED C2 DVSS J8 DVSS P14 RESERVED H3 DVSS J9 DVSS P8 RESERVED J3 DVSS J10 DVSS P9 RESERVED J4 DVSS J11 DVSS R14 RESERVED P1 DVSS J12 DVSS R15 RESERVED P2 DVSS J13 DVSS R16 RESET A5 DVSS J14 DVSS R8 RX1_0 G14 DVSS K5 DVSS T14 RX1_1 F16 DVSS K6 DVSS T15 RX1_2 F15 DVSS K7 DVSS T16 RX1_3 G13 DVSS K8 DVSS T8 RX1_4 F14 DVSS K9 EN_CDET1 C6 RX1_5 F13 DVSS K10 EN_CDET2 P6 RX1_6 E16 DVSS K11 EWRAP1 A1 RX1_7 E14 DVSS K12 EWRAP2 T1 RX1_8 E15 DVSS L5 FERR1 E13 RX1_9 D16 DVSS L6 FERR2 M13 RX1_CLK0 G15 DVSS L7 FRST1 A12 RX1_CLK1 G16 DVSS L8 FRST2 T12 RX2_0 K14 DVSS L9 LCK_REFB1 B5 RX2_1 L16 Bro adco m Co rp or atio n Document 8002-DS03-R Page 33 BCM8002 Advance Data Sheet 05/22/01 Signal Name Ball Signal Name Ball RX2_2 L15 TX2_7 R12 RX2_3 K13 TX2_8 T10 RX2_4 L13 TX2_9 T11 RX2_5 L14 TX2_CLK N9 RX2_6 M16 TXCKO A6 RX2_7 N16 VDDQ C15 RX2_8 M15 VDDQ C16 RX2_9 M14 VDDQ H13 RX2_CLK0 K15 VDDQ H14 RX2_CLK1 K16 VDDQ J15 TCK A4 VDDQ J16 TDI A3 VDDQ P15 TDN1 G1 VDDQ P16 TDN2 K1 VREFL D12 TDO B6 VREFR N12 TDP1 G2 VTT A13 TDP2 K2 VTT A9 TMS A2 VTT B13 TRSTB C5 VTT B9 TX1_0 D10 VTT R13 TX1_1 D11 VTT R9 TX1_2 C12 VTT T13 TX1_3 C11 VTT T9 TX1_4 B10 TX1_5 C10 TX1_6 B11 TX1_7 B12 TX1_8 A10 TX1_9 A11 TX1_CLK D9 TX2_0 N10 TX2_1 N11 TX2_2 P12 TX2_3 P11 TX2_4 R10 TX2_5 P10 TX2_6 R11 Bro adco m Co rp or atio n Page 34 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 Sec t ion 9 : M echa nica l Info rm ation Figure 15: 256-Pin fpBGA Bro adco m Co rp or atio n Document 8002-DS03-R Page 35 BCM8002 Advance Data Sheet 05/22/01 Section 1 0: Ther mal THERMAL INFORMATION This section includes basic thermal information pertaining to the BCM8002 and the 256 ball fpBGA package. Table 22: PACKAGE 256 17x17 mm fpBGA Basic Thermal Data ja (still air) jb AMBIENT TEMPERATURE RANGE 19.02 C/W 0 to 70 C Table 23: jc 6.02 C/W 5.84 C/W Theta-JA vs. Airflow (@2.8 W) AIR FLOW (feet per minute) 256 fpBGA Package Theta-JA (deg C/W) 0 100 200 400 600 19.02 16.70 15.85 14.84 14.16 Bro adco m C orp or atio n Page 36 Document 8002-DS03-R BCM8002 Advance Data Sheet 05/22/01 S e c t io n 1 1 : O rd e r i n g I nfo r m a t io n DEVICE INFORMATION PART NUMBER BCM8002KPB PIN PACKAGE 256 17x17mm fpBGA AMBIENT TEMPERATURE RANGE 0 to 70 C Bro adco m Co rp or atio n Document 8002-DS03-R Page 37 BCM8002 Advance Data Sheet 05/22/01 Broadcom Corporation 16215 Alton Parkway P.O. Box 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710 Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. Document 8002-DS03-R