BCM8002KPB - Broadcom - Datasheet.Live

ADVANCE DATA SHEET

■BCM8002

8002-DS03-R

16215 Alton Parkway • P.O. Box 57013 • Irvine, California 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 05/22/01

Dual 1.25 GBd Transceiver

Figure 1: Functional Block Diagram

General Description

The BCM8002 is a dual 1.25 GigaBaud (GBd) transceiver

that enables scaling the performance and functionality of

enterprise and service provider networks to multi-gigabit

bandwidths. Manufactured in a standard single-poly low-

cost CMOS process, the chip enables establishing a cost-

effective 2.0 Gbps Ethernet link over local fiber networks.

Fully-integrated PLL and CDR enables individual channels

to lock to the incoming data. The unique design of the VCO

and CDR blocks have resulted in a very low-jitter PLL im-

plemented in CMOS. The transmitter section accepts a 10-

bit wide (TBI) parallel data and serializes into a CML high

speed serial data for each channel. The receiver section

enables individual channels to lock to the incoming data.

The recovered data is presented at the parallel outputs.

The optional 8B/10B encoding and 10B/8B decoding of the

PCS layer is addressed through configuration registers.

On-chip diagnostics and self-testing capabilities ease sys-

tem design.

The BCM8002 is fabricated in a standard 0.25 micron

CMOS process and is supplied in a 256 fpBGA package.

Features

•Ultra Low-Jitter Transmitter

•Equalizer at each RX

•On-chip PLL

•Two Independent Transceivers

•Data rate of 1.0 Gb/s

(channel rates of 1.25 GBd)

•Multiple speed reference clock of 62.5 to 125 MHz

•Enhanced IEEE 802.3z Ten Bit Interface (TBI)

•LVPECL differential reference clock

•Parallel-to-Serial and Serial-to-Parallel conversion

•50 / 75 ohm Transmit and Receive Ports

•Receiver Lock to Reference mode

•Auto Lock-to-Reference upon loss of received signal

•Selectable 8B/10B encoder / decoder

•MDC/MDIO management interface

•Parallel data I/O and clocks compatible with SSTL_2

and HSTL

•Double Data Rate (DDR) data transfers

•IEEE 1149.1 (JTAG), including boundary scan for TDn

& RDn

•Parallel or Serial loopback mode

•Built in Bit Error Rate Tester (BERT)

•Single 2.5V power supply

•Power less than 2.8W

Applications

•Server Clusters

•Switch-to-switch Links

•Wireless Access Points

•Cable Head-End

IEEE 1149.1

JTAG

Configuration

Control

TXCKO

TD0+

TD0-

RD0+

RD0-

TMS

TCK

TDI

TDO

TRSTb

MDIO

MDC

Clock Multiplier Unit

(PLL)

FIFO

8B/10B Encoder

Serializer

Clock Recovery

Word Synchronization

Deserializer

10B/8B Decoder

FIFO

TX[9:0]

TX_CLK

FRST

EWRAP

RX[9:0]

COMDET

RX_CLK0

EN_CDET

RX_CLK1

LCK_REFb

RST

REFCLK

RBIAS

Broadcom Corporation

P.O. Box 57013

16215 Alton Parkway

Irvine, California 92619-7013

Printed in the U.S.A.

Broadcom, the pulse logo, and QAMLink are registered trademarks of Broadcom Corporation and/or its subsidiaries in the

United States and certain other countries. All other trademarks are the property of their respective owners.

Revision History

REVISION Date CHANGE DESCRIPTION

8002-DS00-R 09/10/00 Initial Release.

8002-DS01-R 03/26/01 •Updated front cover General Description and Features.

•Updated Tables 2, 8, 22, and 23.

•Updated Thermal Information.

•Updated Ordering Information.

•Various text changes.

8002-DS02-R 05/09/01 Corrected PHYID LOW value to 6144h (see Table 7 on page 12).

8002-DS02-R 5/22/01 Added grounded balls to center field of package (see Figure 2 on page

7 and Section 8 ”Ballout Assignment” on page 30) to reflect how the

BCM8002 is designed.

Advance Data Sheet ■ BCM8002
05/22/01           
Broadcom Corporation
Document  8002-DS03-R Page  iii 
TABLE OF CONTENTS
Section 1: Functional Description......................................................................................1
Overview ....................................................................................................................................................... 1
Global Functions.......................................................................................................................................... 1
Clock Multiplier Unit ................................................................................................................................ 1
Transceiver ................................................................................................................................................... 2
Transmitter.............................................................................................................................................. 2
Data Input FIFO ............................................................................................................................... 2
8B/10B Encoder............................................................................................................................... 2
Serial Output Buffer ......................................................................................................................... 2
Receiver.................................................................................................................................................. 2
Serial Input Receiver ....................................................................................................................... 2
Clock Recovery................................................................................................................................ 2
Signal Detect ................................................................................................................................... 3
Auto Lock to Reference ................................................................................................................... 3
Receive Line Equalization ............................................................................................................... 3
Code Word Synchronization ............................................................................................................ 3
8B/10B Decoder. ............................................................................................................................. 3
Data Output FIFO ............................................................................................................................ 3
Section 2: Hardware Signal Definitions .............................................................................4
Conventions ................................................................................................................................................. 4
Section 3: Pinout Diagram ..................................................................................................7
256-Pin fpBGA Diagram............................................................................................................................... 7
Section 4: Operational Description....................................................................................9
Resetting the BCM8002 ............................................................................................................................... 9
Test Modes ................................................................................................................................................... 9
Loop Back Modes ................................................................................................................................... 9
JTAG, IEEE 1149.1................................................................................................................................. 9
Section 5: Register Summary...........................................................................................10
Accessing the Registers via the XMII Management Interface................................................................ 10
PHY Address ........................................................................................................................................ 10

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■ BCM8002 Advance Data Sheet
05/22/01
Register Programming...........................................................................................................................10
Global Registers ......................................................................................................................................... 11
Control Register.....................................................................................................................................11
Status Register ......................................................................................................................................12
PHY Identifier Register..........................................................................................................................12
Configuration Register...........................................................................................................................12
PMA-Level Registers .................................................................................................................................. 14
PMA Configuration Register ..................................................................................................................14
PMA Status Register .............................................................................................................................15
Receiver Equalizer Control Register 1 ..................................................................................................16
Section 6: Timing Diagrams............................................................................................. 17
Section 7: Electrical Specifications................................................................................. 19
General Specifications...............................................................................................................................19
PMA Interface Specifications ....................................................................................................................20
PMD Interface Specifications ....................................................................................................................24
Transmitter Electrical Specifications......................................................................................................24
Receiver Electrical Specifications..........................................................................................................26
Section 8: Ballout Assignment ........................................................................................ 30
Ballout by Ball Number ..............................................................................................................................30
Ballout by Signal Name..............................................................................................................................32
Section 9: Mechanical Information .................................................................................. 35
Section 10: Thermal .......................................................................................................... 36
Thermal Information ...................................................................................................................................36
Section 11: Ordering Information .................................................................................... 37
Device Information .....................................................................................................................................37

Broadcom Corporation
Document  8002 Page  v 
Advance Data Sheet ■ BCM8002
05/22/01
LIST OF FIGURES
Figure 1: Functional Block Diagram.................................................................................................................i
Figure 2: BCM8002 Pinout Diagram.............................................................................................................. 7
Figure 3: TBI Comma Resynchronization Timing Diagram (in phase) ........................................................ 17
Figure 4: TBI Comma Resynchronization Timing Diagram (2-bits early) .................................................... 18
Figure 5: Input / Output Valid Levels for AC Measurements ....................................................................... 20
Figure 6: Transmit Interface Timing Diagram, SDR .................................................................................... 21
Figure 7: Receiver Interface Timing Diagram SDR ..................................................................................... 22
Figure 8: Receiver Interface Timing Diagram DDR ..................................................................................... 23
Figure 9: Balanced Transmitter Test Load .................................................................................................. 24
Figure 10: Transmit Eye Diagrams at TP1 / TP2 ........................................................................................... 25
Figure 11: TD± Transmit Signal Timing Diagram .......................................................................................... 26
Figure 12: Receiver Test Diagram ................................................................................................................. 26
Figure 13: Receive Eye Diagram Mask at TP3.............................................................................................. 27
Figure 14: RD± Receiver Signal Timing Diagram.......................................................................................... 28
Figure 15: 256-Pin fpBGA.............................................................................................................................. 35

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05/22/01           
Broadcom Corporation
Document  8002-DS03-R Page  vi 
LIST OF TABLES
Table 1: Clock Generation ............................................................................................................................ 1
Table 2: Receiver Error / Exception Conditions ............................................................................................ 3
Table 3: Hardware Signals............................................................................................................................ 4
Table 4: Frame Format ............................................................................................................................... 10
Table 5: Control Register (Address 00h)..................................................................................................... 11
Table 6: Status Register (Address 01h) ...................................................................................................... 12
Table 7: PHY Identifier Registers (Addresses 02h and 03h........................................................................ 12
Table 8: Configuration Register (Address=10h).......................................................................................... 12
Table 9: PMAn Configuration Register (Address=11h) ...............................................................................14
Table 10: PMAn Status Register (Address=12h, Read Only) ....................................................................... 15
Table 11: Receiver Equalizer Control Register (Address=19h) .................................................................... 16
Table 12: Absolute Maximum Ratings .......................................................................................................... 19
Table 13: Recommended Operating Conditions ........................................................................................... 19
Table 14: PMA Interface DC Specifications .................................................................................................. 20
Table 15: PMA Transmit AC Specifications, SDR......................................................................................... 21
Table 16: PMA Receive Bus AC Specification, SDR .................................................................................... 22
Table 17: PMA Receive Bus AC Specification, DDR .................................................................................... 24
Table 18: Transmitter Characteristics at TP1 / TP2 ...................................................................................... 25
Table 19: Receiver Characteristics at TP4.................................................................................................... 27
Table 20: Ballout by Ball Number.................................................................................................................. 30
Table 21: Ballout by Signal Name................................................................................................................. 32
Table 22: Basic Thermal Data....................................................................................................................... 36
Table 23: Theta-JA vs. Airflow (@2.8 W)...................................................................................................... 36

Broadcom Corporation

Document 8002-DS03-R Page 1

Advance Data Sheet ■ BCM8002

05/22/01

Section 1: Functional Description

OVERVIEW

The BCM8002 is a two channel serial transceiver that supports 1.25 GigaBaud (GBd) full-duplex operation on each channel.

An on-chip Phase-Locked Loop (PLL) provides clock synthesis from 62.5 or 125 MHz reference clocks.

Each transmit channel serializes 10-bit (or 8 bit data with the internal 8b/10b encoder enabled) SSTL2/HSTL/LVTTL* com-

patible parallel data into a high-speed differential CML output.

Each differential-input receiver recovers the clock and data at its serial input. After clock recovery and de-serializing, the data

is delivered to a 10-bit SSTL2/HSTL/LVTTL* compatible parallel interface (8 bits with the internal 8b/10 decoder enabled).

Equalization at each receiver corrects for cable and connector induced distortions.

A programmable Pseudo-Random Binary Sequence (PRBS) generator facilitates self-test and BERT of each channel, with-

out the need for external bit-generator hook-up. Internal loopback capabilities facilitate quick diagnosis of system issues.

* For LVTTL implementation, please see the BCM8002 Design Guide.

GLOBAL FUNCTIONS

CLOCK MULTIPLIER UNIT

The Clock Multiplier Unit takes the signal on the REFCLK± pins and multiplies its frequency up to create the internal serial

transmission clock and receive reference clock. A single ultra-low jitter Phase Locked Loop (PLL) is used to generate the

transmit data rate clock and the receiver data rate reference clock. An internal PLL filter has been implemented requiring no

external components. Table 1 shows the reference clock to serial channel rate relationships, using the equation below:

Baud-rate = (fREFCLK / refdiv) * (vcodiv/2)

Example: 1.25 = (125/2) * (40/2)

Table 1: Clock Generation

fREFCLK (MHz)

PLL

REFDIV

/1=bit low

/2=bit hi

TCKO OUTPUT

CLOCK (MHz)

PARALLEL DATA

RATE (MBd)

SERIAL DATA

RATE (Gbps)

SERIAL CHANNEL

BAUD RATE (GBd)

62.5 /1 125 125 1.00 1.25

125 /2 125 125 1.00 1.25

Broadcom Corporation

Page 2 Document 8002-DS03-R

■ BCM8002 Advance Data Sheet

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TRANSCEIVER

Each transmitter takes 10 bits of data on the TXn pins and performs a parallel-to-serial conversion at the desired serial rate,

producing a serial stream on the TDn outputs. Optionally, 8 bits of data can be encoded with the on-chip 8B/10B encoder,

creating 10 bits that go through the parallel-to-serial conversion and are driven out on the TDn pins.

TRANSMITTER

Data Input FIFO. A transmitter input FIFO is provided for deskew of the external and internal clocks. The data presented

on the TXn[9:0] pins can be clocked in by either the corresponding TXn_CLK pin or the TX1_CLK pin. The corresponding

TX1_CLK pin is used when the corresponding configuration bit TCKSEL is active otherwise the TXn_CLK is used (default).

The transmit FIFO can be reset / initialized by activating the FRST pin. The transmit FIFO should be initialized after the PLL

and FIFO clocks have stabilized.

If the TXn_CLK is not at the same frequency as the internal code-word rate clock, or a TXn_CLK pulse was suppressed or

missing, a FIFO underrun or overrun condition might occur. When this event occurs, the FERR pin and the TFERR bit in the

transceiver configuration register are set. The transmit fifo then needs to be reset with the FRST pin to clear the error

condition and error bits.

8B/10B Encoder. An on-chip IEEE 802.3z clause 36.2.4 compliant 8B/10B encoder can be selected. The 8B/10B encoder

is bypassed (disabled) for a transmitter when the corresponding EDEN configuration bit is inactive. When the encoder is

bypassed, the data on TXn[9:0] is directly serialized, Least Significant Bit (LSB) first.

The encoder for a transmitter is enabled when the corresponding EDEN configuration bit is active. The data on the

corresponding TXn[7:0] pins and the TKDn pin is then encoded according to the IEEE 802.3z clause 36.2.4 8B/10B encoding

rules.

Serial Output Buffer. The output impedance of the transmit buffer is set by the ZSEL bit in the transceiver configuration

75Ω.

The transmit output buffer is disabled when the internal serial loop back mode is selected. The “0” state is when TDn+ <

TDn- and the “1” state is when TDn+ > TDn-.

RECEIVER

Each receiver synchronizes its internal VCO clock to the incoming data on the RDn pins recovering the clock in the data

stream. The serial data is then converted to 10-bit parallel data and a comma detector can be enabled to automatically align

the code-word boundaries. The code words can then optionally be decoded with the IEEE 802.3z clause 36.2.4 compliant

10B/8B decoder. The resulting 10 or 8 bit code-words are then written into the read FIFO where all four channels can be

synchronized together with the parallel code-words driven out on the RXn pins.

Serial Input Receiver. The receiver must be AC-coupled (0.01 uF in + and - legs). The input impedance of the input

buffer is set by an external resistor placed between the RDn± pins. The input buffer is disabled when the internal serial loop

back mode is selected. The “0” state is when RDn+ < RDn- and the “1” state is when RDn+ > RDn-.

Clock Recovery. An independent PLL for each receiver recovers the data and a clock from the incoming data stream. To

ensure that the PLL locks to the proper frequency, a lock to reference mode is provided, and is selected when LCK_REFb

is active. Once the receive PLL is locked to the reference frequency and proper data is being received, LCK_REFb can be

deactivated and the PLL then phase aligns to the incoming data and track the data’s phase and frequency. The recovered

clock and data are then passed on to the balance of the receive circuits for code-group alignment, de-serialization and

channel to channel synchronization.

Broadcom Corporation

Document 8002-DS03-R Page 3

Advance Data Sheet ■ BCM8002

05/22/01

Signal Detect. The presence of a signal on the RDn± pins is indicated by the SIGDET bit in the Transceiver Configuration

Auto Lock to Reference. An auto lock to reference or data mode can be enabled by setting the ALOCK bit in the

transceiver configuration register. The receive PLL automatically locks to the reference upon power up, reset, in the absence

of receive data or when corrupted data causes the receive PLL to become unlocked. The Receive PLL switches to locking

to the incoming data after it has locked to the reference and receive data is present. In all cases when the LCK_REFb is

active, the receive PLL locks to the reference clock.

Receive Line Equalization. A two tap FIR (1-αZ-1) equalizer is provided to open the eye for long cable or trace lengths.

α can be programmed to 0%, 3.25%, ..., 45% by setting the Transceiver Equalizer Register bits RTAP3-0 to 0h, 1h, ..., Fh

respectively.

Code Word Synchronization. Comma character detection is available to provide a consistent code-word alignment for

the de-serialization process. When EN_CDETn is active, the corresponding receiver aligns the code-group of the de-

serialization process such that the code group containing the comma is aligned with the positive transition of RXn_CLK1

(see Figure 4, ”TBI Comma Resynchronization Timing Diagram (2-bits early),” on page 18) and COM_DETn is activated.

Both comma+ and comma- characters are detected.

8B/10B Decoder. An on-chip IEEE 802.3z clause 36.4.2 compliant 10B/8B decoder can be selected. The 10B/8B

decoder is bypassed (disabled) for a receiver when the corresponding EDEN configuration bit is inactive. When the decoder

is bypassed, the data on RXn[9:0] is directly deserialized, LSB first, to the selected RDn± inputs.

When the decoder is enabled for a receiver, the corresponding EDEN configuration bit is active. The data on the

corresponding RXn[7:0] and RKDn pins is the deserialized data from the RDn± inputs decoded according to the IEEE 802.3z

clause 36.4.2 10B/8B decoding rules. When the decoder is active, the RERRn along with the COM_DETn and RKDn pins

indicate when an error or an exception condition has occurred.

Data Output FIFO. A receiver output FIFO is provided for deskew of the external and internal clocks. The data presented

on the RXn[9:0] pins and the COM_DETn pin can be clocked out by either the corresponding RXn_CLK0 pin or both

RXn_CLK0 and RXn_CLK1 pins. The RXn_CLK1 pin is used when the configuration bit RCKSEL is active, otherwise both

RXn_CLK0 and RXn_CLK1 pins are used (default).

Table 2: Receiver Error / Exception Conditions

RERRn

RKDn

COM_DETn

Description

0 0 0 Valid D-word received

001Reserved

0 1 0 Valid K-word received

0 1 1 Valid K-word with imbedded comma (K28.1, K28.5, K28.7) received

1 0 0 Invalid code group received (also RX[9:0] = K28.7, violation)

1 0 1 Invalid code group with imbedded comma received

110Reserved

111Reserved

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■ BCM8002 Advance Data Sheet

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Section 2: Hardware Signal Definitions

CONVENTIONS

SIGNAME A signal named “signame” is active high. An input signal “signame” activates / enables its function when

it is put into the “high” state. An output signal “signame” indicates its status when it is driving a “high”

state.

SIGNAMEb A signal named “signameb”, that is a signal name ending in a lower case “b” is active low. An input signal

“signameb” activates / enables its function when it is put into the “low” state. An output signal “signameb”

indicates its status when it is driving a “low” state.

SIGNAMEn n=1 or 2 is the PMA, or channel, number.

active When an active low signal is in the “low” state or when an active high signal is in the “high” state.

inactive When an active low signal is in the “high” state or when an active high signal is in the “low” state.

Table 3: Hardware Signals

Pin Label Type Description

Physical Medium Attachment (PMA) Connections per Transceiver

TXn[9:0] I Parallel transmit input data

TKDn I Transmit K / D code-group select, 1 = K-code group, 0 = D-code group. Shared with

TXn[8].

FRSTn I Transmit FIFO ReSeT, 1=reset transmit Fifo, (synchronized internally)

FERRn O Transmit FIFO ERRor, 1=under / over run occurred

TXn_CLK I Transmit data clock

RXn[9:0] O Parallel receive output data

RKDn O Receive K / D code-group status, 1=K, 0=D code group received. Shared with RXn[8].

RERRn O Receive ERRor, 1=error. Shared with RXn[9].

COM_DETn O Comma Detect, active high. When active, indicates a comma was detected

RXn_CLK0 O Receive clock 0, odd byte clock

RXn_CLK1 O Receive clock 1, even byte clock

EN_CDETn I Enable comma detect, active high. When active, comma detection is enabled

LCK_REFbn I Lock to reference, active low. When active, the receive PLL locks to the internal trans-

mit clock

EWRAPn I Enable wrap, active hi. When active, activates the selected internal loopback mode

Note: I = input; O = output; I/O = bidirectional; IPU = input w/ internal pull-up; IPD = input w/ internal pull-down; I/OPU =

bidirectional w/ internal pull-up; B = bias; AO = Analog output, P = power; G = ground

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Document 8002-DS03-R Page 5

Advance Data Sheet ■ BCM8002

05/22/01

Medium Connections per Transceiver

RDn±I Differential receive data inputs (AC couple)

TDn±O Differential transmit data outputs

PLL and Bias Connections

REFCLK±I Data rate reference clock (AC couple)

TXCKO O Transmit code-word rate clock out

RBIAS B Analog Bias Set Resistor

Managed Data Interface

MDC IPD Management Data Clock

MDIO I/OPU Management Data In / Out

RST I Chip ReSeT, completely powers down and resets the BCM8002, (synchronized inter-

nally, make width at least 16 REF_CLKs beyond power stable)

PHYAD[4:0] IPD PHY ADdress identification: the 5-bits of the PHY address field used by the Managed

Data Interface.

JTAG Test Port

TMS IPU JTAG Mode Select

TCK IPD JTAG Test Clock

TDI IPU JTAG Test Data Input

TDO O JTAG Test Data Output

TRSTb IPU JTAG Test Reset

Power

VDDQ P SSTL/HSTL I/O power

VTT P SSTL/HSTL inputs termination voltage (use regulator, typically set to VDDQ /2,)

VREF P SSTL/HSTL inputs reference level (typ. VDDQ / 2, generate separately from VTT)

DVDD P Digital logic power

CVDD P Power for digital sections of analog macro-functions

AVDD P Analog power

DVSS P Digital ground

AVSS P Analog ground

Table 3: Hardware Signals (Continued)

Pin Label Type Description

Note: I = input; O = output; I/O = bidirectional; IPU = input w/ internal pull-up; IPD = input w/ internal pull-down; I/OPU =

bidirectional w/ internal pull-up; B = bias; AO = Analog output, P = power; G = ground

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Page 6 Document 8002-DS03-R

■ BCM8002 Advance Data Sheet

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Factory Test

TPORTPn

TPORTNn

TVCOUT

TVCON

TVCOP

AO Used for factory test, leave open

Table 3: Hardware Signals (Continued)

Pin Label Type Description

Note: I = input; O = output; I/O = bidirectional; IPU = input w/ internal pull-up; IPD = input w/ internal pull-down; I/OPU =

bidirectional w/ internal pull-up; B = bias; AO = Analog output, P = power; G = ground

Broadcom Corporation

Document 8002-DS03-R Page 7

Advance Data Sheet ■ BCM8002

05/22/01

Section 3: Pinout Diagram

256-PIN FPBGA DIAGRAM

Figure 2: BCM8002 Pinout Diagram

TXCKO

RESET

TDO

TCK

TDI

LCK_REFB1

TMS

EWRAP1

EN_CDET1

TRSTB

CVDD

TPORTN1

TPORTP1

AVDD

AVDD RDP1

RDN1

CVDD CVDD

TDN1

TDP1

AVDD

REFCLKN REFCLKP AVDD

cvddCVDD TVCOP TVCON

TVCOUT

AVDD

RBIAS

AVDD

TDP2

TDN2

CVDD CVDD

RDN2

RDP2

AVDD

AVDD TPORTP2

TPORTN2

CVDD

PHYAD4

EN_CDET2

EWRAP2

PHYAD3

LCK_REFB2

PHYAD2

PHYAD1

PHYAD0

MDIO

mdc

VREF

TX2_CLK

TX2_0

TX2_1

TX2_2

TX2_3

TX2_5 TX2_4

TX2_6

TX2_7

TX2_8

TX2_9

FRST2

FERR2

COM_DET2

RX2_9

RX2_8

RX2_7RX2_6

RX2_5

RX2_4RX2_3

RX2_2

RX2_1

RX2_0

RX2_CLK0

RX2_CLK1RX1_CLK1

RX1_CLK0

RX1_0

RX1_1

RX1_2

RX1_3

RX1_4

RX1_5

RX1_6

RX1_7

RX1_8

RX1_9

COM_DET1

FERR1

FRST1

TX1_9

TX1_8

TX1_7

TX1_6

TX1_4 TX1_5

TX1_3

TX1_2

TX1_1

TX1_0

TX1_CLK

VREF

DVSS

AVSS

AVSS AVSS

AVSS

AVSS AVSS

AVSS

AVSS AVSS

VDDQ

VTT

DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD

ABCDEFGHJKLMNPRT

DVSS

DVSSDVSS

DVSS

DVSS DVSS

DVSS DVSS DVSS

DVSSDVSSDVSSDVSS

DVSS

DVSSDVSS

DVSS

DVSSDVSS

DVSS

DVSSDVSSDVSS

DVSS DVSS

DVSS DVSS DVSS

DVSS

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■ BCM8002 Advance Data Sheet

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Broadcom Corporation

Document 8002-DS03-R Page 9

Advance Data Sheet ■ BCM8002

05/22/01

Section 4: Operational Description

RESETTING THE BCM8002

A Reset pin is used to initialize all circuits. After power has come up, the RESET signal needs to stay on for at least 16 REF-

CLK± cycles. RESET puts all digital blocks into a reset or known state and initializes all analog blocks. Additionally, each

transceiver can be independently reset / powered down by setting the RESET bit in the corresponding transceiver configu-

ration register.

After reset, the TX PLL goes through a lock sequence to REF_CLK. Once the TX PLL achieves stable lock (about 6 usec),

it resets the RXs (including the RX PLL). The RX PLLs then go through a lock sequence to lock to the TX clock. Once this

is achieved, the RX PLLs are switched to the RX data and go through a new lock sequence. A bit (ALOCK) can be set to

have the RX PLLs lock to the TX clock whenever they lose lock to data, this allows a quicker lock to data, when the data

comes back, than letting the RX PLL run to the end of it's range. Another bit (LCK_REF) can force the RX PLL to lock the

TX clock.

TEST MODES

LOOP BACK MODES

There are two loopback modes to help facilitate system testing and debugging. The loopback mode is entered when the

EWRAP signal is activated. There are two loopback modes that can be selected:

1) - When the PWRAP bit in the transceiver configuration register is inactive, a serial loopback mode is selected, where the

serial transmit data is internally feed back into the serial receiver.

2) - When the PWRAP bit in the transceiver configuration register is active, a parallel loopback mode is selected, where the

parallel received data on RXn[0:9] is internally feed back as the parallel data for TXn[0:9]. This mode could be used as a

repeater function where the serial input data is resynchronized to the reference clock and transmitted back out as serial

transmit data. This effectively removes the jitter on the serial receive data, opening up the re-transmitted eye diagram.

CAUTION: For parallel loopback mode, it is assumed that the transmitter and receiver are frequency locked, i.e. the clock

source for the incoming RDn data is the same clock source as for the transmit PLL reference clock.

JTAG, IEEE 1149.1

The BCM8002 JTAG interface is compliant with the IEEE 1149.1 requirements and is provided to test the connectivity of the

pins on the BCM8002. The Test Access Port (TAP) provides access to the BCM8002’s test logic. When TRST is active the

TAP is put into the initialization state. All digital pins as well as all TDn and all RDn pins are connected to the JTAG boundary

scan register, the only pins not connected to the boundary scan register is the analog bias pin RBIAS. The three required

instructions, Bypass, Extest, and Sample/Preload, are implemented.

Broadcom Corporation

Page 10 Document 8002-DS03-R

■ BCM8002 Advance Data Sheet

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Section 5: Register Summary

ACCESSING THE REGISTERS VIA THE XMII MANAGEMENT INTERFACE

PHY ADDRESS

The BCM8002 has a unique address for the management set, using the PHYAD[4:0] pins. The pins are latched on the trailing

edge of the RESET pin.

Every time an MDIO write or read operation is executed, the BCM8002 compares the PHY address with its own PHY ad-

dress. The operation is executed only when the PHYAD matches the internal PHY address.

The registers are serially written-to and read-from using a common pair of MDIO and MDC pins. A clock must be provided

to the BCM8002 at a rate of 0-25 MHz through the MDC pin. The serial data is communicated on the MDIO pin. Every MDIO

bit must have the same period as the MDC clock. The MDIO bits are latched on the rising edge of the MDC clock.

Table 4 shows the fields in read or write instruction frames.

Preamble (PRE) - Thirty two consecutive “1” bits must be sent through the MDIO pin to the BCM8002 to signal the beginning

of an instruction. Fewer than 32 “1” bits cause the remainder of the instruction to be ignored.

Start of Frame (ST) - A “01” pattern indicates that the start of the instruction follows.

Operation Code (OP) - A READ instruction is indicated by “10”, while a WRITE instruction is indicated by “01”.

PHY Address (PHYAD) - A 5-bit PHY Address follows, with the Most Significant Bit (MSB) transmitted first.

BCM8002, containing register addresses and bit definitions, are provided on the following pages.

Turnaround (TA) - The next two bit times are used to avoid contention on the MDIO pin when a Read operation is per-

formed. For a Write operation, “10” must be sent to the BCM8002 chip during these two bit times. For a Read operation, the

MDIO pin must be placed into High-Impedance during these two bit times. The chip drives the MDIO pin to “0” during the

second bit time.

Data - The last 16 bits of the frame are the actual data bits. For a write operation, these bits are sent to the BCM8002, where-

as, for a read operation, these bits are driven by the BCM8002. In either case, the MSB is transmitted first.

When writing to the BCM8002, the data field bits must be stable 10 ns before the rising-edge of MDC, and must be held valid

for 10 ns after the rising edge of MDC. When reading from the BCM8002, the data field bits are valid after the rising-edge of

MDC until the next rising-edge of MDC.

Idle - A high impedance state of the MDIO line (Z represents a bit of tri-state). The MDIO tri-state driver is disabled and the

pull-up resistor pulls the MDIO line to logic “1”.

Table 4: Frame Format

Operation PRE ST OP PHYAD REGAD TA DATA IDle Direction

READ 1 ... 1 01 10 AAAAA nnnnn ZZ

Z...Z

D...D

Driven to BCM8002

Driven by BCM8002

WRITE 1 ... 1 01 01 AAAAA nnnnn 10 D ... D Z Driven to BCM8002

Broadcom Corporation

Document 8002-DS03-R Page 11

Advance Data Sheet ■ BCM8002

05/22/01

Following are two examples of write and read instructions:

Ex. 1:

In order to put the BCM8002 into the loopback state, the following write instruction must be issued:

1111 1111 1111 1111 1111 1111 1111 1111 0101 AAAAA 00000 10 0100 0000 0000 0000

Ex. 2:

In order to determine the link status, the following read instruction must be issued:

1111 1111 1111 1111 1111 1111 1111 1111 0110 00000 00001 ZZ ZZZZ ZZZZ ZZZZ ZZZZ

For the read operation, the BCM8002 drives the MDIO line during the TA and Data fields (the last 17 bit times).

GLOBAL REGISTERS

When writing to reserved bits, always write a 0 value, and when reading from these bits, ignore the output value. Never

write any value to an undefined register address.

CONTROL REGISTER

Reset - All registers are put into their default state, and all circuits are reset. This bit is automatically cleared after 16 refclk

cycles.

Loopback - Each transmit serial output is fed back to its corresponding receiver serial input. All transmitter output drivers

are turned off.

Power Down - All analog blocks are powered down and all VCOs are off. The register values remain unchanged.

Isolate - All outputs are tri-stated and the BCM8002 does not respond to any signals on the inputs. All transmitter output

drivers put out a constant 0.

Table 5: Control Register (Address 00h)

BIT NAME R/W DESCRIPTION DEFAULT

15 Reset R/W 1 = Reset

0 = Normal operation

14 Loopback R/W 1 = Loopback

0 = Normal operation

13:12 Reserved N/A 0

11 Power Down R/W 1= Power down state

0 = Normal operation

10 Isolate R/W 1 = Isolate

0 = Normal operation

9:0 Reserved N/A 0

Broadcom Corporation

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■ BCM8002 Advance Data Sheet

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STATUS REGISTER

PHY IDENTIFIER REGISTER

Broadcom Corporation has been issued an Organizationally Unique Identifier (OUI) by the IEEE. It is a 24-bit number,

00-10-18, expressed as hex values. That number, along with the Broadcom Model Number for the BCM8002 part, 1Ch, and

Broadcom Revision number, 00h, is placed into two MII Registers. The translation from OUI, Model Number and Revision

Number to PHY Identifier Register occurs as follows:

PHYID HIGH [15:0] = OUI[21:6]

PHYID LOW [15:0] = OUI[5:0] + MODEL[5:0] + REV[3:0]

CONFIGURATION REGISTER

Table 6: Status Register (Address 01h)

BIT NAME R/W DESCRIPTION DEFAULT

15:3 Reserved NA 0

2 Reserved NA 0

1:0 Reserved NA 0

Table 7: PHY Identifier Registers (Addresses 02h and 03h

BIT NAME R/W DESCRIPTION VALUE

15:0 MII Address 00010 R PHYID HIGH 0040h

15:0 MII Address 00011 R PHYID LOW 6144h

Table 8: Configuration Register (Address=10h)

BIT NAME R/W DESCRIPTION DEFAULT

15 PLLOCK R 1 = Shared TX PLL is locked to the reference clock

0 = Shared TX PLL is not locked

14:12 Reserved NA 0

11 Reserved NA 0

10 PMA[2] R/W 1 = Selects the PMA2 register set

0 = BCM8002 quad level selected if all PMA[n] bits = 0

9 PMA[1] R/W 1 = Selects the PMA1 register set

0 = BCM8002 quad level selected if all PMA[n] bits = 0

8 Reserved NA 0

7 Reserved NA 0

6 Reserved NA 0

5 HSTL R/W 1 = Specified pads must be set to 1.5V

0 = Specified pads must be set to 2.5V

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Document 8002-DS03-R Page 13

Advance Data Sheet ■ BCM8002

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PLLOCK - When active, the shared PLL is locked to the reference clock. When inactive, the shared PLL is not locked.

PMA(2) - When active, PMA(2) selects PMA2’s register set to be accessed for REGAD=11h-1Fh. During a write operation

more than one PMA may be selected at a time. During a read operation, only one PMA should be selected at a time, other-

wise unknown data could be read. When all PMA(n) are inactive, then the BCM8002 quad level registers are selected.

PMA(1) - When active, PMA(1) selects PMA1’s register set to be accessed for REGAD=11h-1Fh. During a write operation

more than one PMA may be selected at a time. During a read operation, only one PMA should be selected at a time, other-

wise unknown data could be read. When all PMA(n) are inactive, then the BCM8002 quad level registers are selected.

HSTL - When active, pads TXn, FERRn, FRSTn, TXn_CLK, RXn, COM_DETn, RXn_CLK0, RXn_CLK1 are HSTL pads and

VDDQ must be set to 1.5V with VTT and VREF = VDDQ / 2.

When inactive, pads TXn, FERRn, FRSTn, TXn_CLK, RXn, COM_DETn, RXn_CLK0, RXn_CLK1 are SSTL_2 pads and

VDDQ must be set to 2.5V with VTT and VREF = VDDQ / 2.

Note: No damage will occur from the part resetting to SSTL when configured externally for HSTL.

ICTRL - When active, pads EN_CDET, LCK_REFb and EWRAP are disabled and the internal bits, CDETEN, WRAPEN &

LCKREF in each of the Transceiver Configuration Registers, are used to configure each transceiver.

When inactive, the internal bits, CDETEN, WRAPEN & LCKREF in each of the Transceiver Configuration Registers, are dis-

abled and pads EN_CDET, LCK_REFb and EWRAP are used to configure each transceiver.

VCOBYP - When active, the REFCLK± input is used as the internal channel bit rate clock. When inactive, normal operation,

the shared PLL generates the internal channel bit rate clock.

REFDIV - When active, the reference clock divided by 2 is sent to the shared PLL’s phase detector (used for a 125 MHz

REFCLK±). When inactive, the reference clock divided by 1 is sent to the shared PLL’s phase detector (used for a 62.5 MHz

REFCLK ±).

4 ICTRL R/W 1= Specified pads are disabled and specified internal bits are used

0 = Internal bits are disabled and specified pads are used

3 Reserved NA 0

2 VCOBYP R/W 1 = REFCLK± input is used as the internal channel bit rate clock

0 = Shared PLL generates the internal channel bit rate clock

1 Reserved (was

VCODIV)

R/W (Needs a “1” written in Revs A0 - A3) 0

0 REFDIV R/W 1 = Reference clock divided by 2 is sent to the PLL’s phase detector

0 = Reference clock divided by 1 is sent to the PLL’s phase detector

Table 8: Configuration Register (Address=10h) (Continued)

BIT NAME R/W DESCRIPTION DEFAULT

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■ BCM8002 Advance Data Sheet

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PMA-LEVEL REGISTERS

To access a PMA’s registers, the corresponding PMA select bit in the Quad Level Configuration Register (Address=10h)

must be set.

When writing to reserved bits, always write a 0 value, and when reading from these bits, ignore the output value. Never write

any value to an undefined register address.

PMA CONFIGURATION REGISTER

ALOCK - When active, the receiver automatically locks to the reference clock when there is no signal on the RDSP/N inputs,

and switches back to locking and tracking the receive data when there is a signal on the RDSP/N inputs. When inactive,

automatic switch between locking to the reference clock and the receive data is disabled.

RCKSEL - When active, RCKSEL selects RX_CLK0 to clock out, at the code group rate, the RXn<9:0> data. One code

group per rising edge of RXn_CLK0 is clocked out on RX<9:0>. RXn_CLK1 is driven low.

When inactive, RXn_CLK0 and RXn_CLK1 are used to clock out, at half the code group rate, the RXn<9:0> data. One code

Table 9: PMAn Configuration Register (Address=11h)

BIT NAME R/W DESCRIPTION DEFAULT

15:12 Reserved NA 0

11 ALOCK R/W 1 = Receiver automatically locks to the reference clock

0 = Automatic switch is disabled

10 RCKSEL R/W 1 = RCKSEL selects RX_CLK0 to clock rx parallel data out

0 = RXn_CLK0 and RXn_CLK1 are used to clock rx parallel data out

9 TCKSEL R/W 1 = TCKSEL selects TX(1)_CLK to clock in the TXn<9:0> data

0 = TXn_CLK is used to clock in the TXn<9:0> data

8 PWRAP R/W 1 = Parallel loopback mode is selected when WRAPEN is active

0 = Serial loopback mode is selected when WRAPEN is active

7 ZSEL R/W 1 = Transmit serial ports have a 75 ohm single-ended impedance

0 = Transmit serial ports have a 50 ohm single-ended impedance

6 RESERVED R/W Reserved 0

5 EDEN R/W 1 = Enables internal transmitter encoder and receiver decoder

0 = Bypasses internal transmitter encoder and receiver decoder

4 CDETEN R/W 1 = Enables comma detection

0 = Disables comma detection

3 WRAPEN R/W 1 = Enables selected wrap (loopback) mode (serial or parallel)

0 = Enables normal transmit and receive mode

2 LCKREF R/W 1 = Receiver PLL locks to the internal global transmit clock

0 = Receive PLL phase locks to the incoming receive data stream

1 PWRDWN R/W 1 = Selected PMA is put into the power-down state

0 = Selected PMA is in its normal operational mode

0 RESET R/W 1= Transmitter and receiver are completely powered down

0 = Transmitter and receiver are operational

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Document 8002-DS03-R Page 15

Advance Data Sheet ■ BCM8002

05/22/01

group per each rising edge of RXn_CLK0 and RXn_CLK1 is clocked out on RXn<9:0>.

TCKSEL - When active, TCKSEL selects TX1_CLK to clock in the TXn<9:0> data on all four channels. When inactive,

TXn_CLK is used to clock in the TXn<9:0> data.

PWRAP - When active, the parallel loopback mode is selected when WRAPEN is active. Parallel loopback takes the output

of the receive fifo into the input of the transmit fifo of the corresponding transmitter.

When inactive, the serial loopback mode is selected when WRAPEN is active. Serial loopback takes the input to the transmit

buffer as the output of the receive buffer. Both transmit and receive buffers are turned off.

ZSEL - When active, the transmit serial ports have a 75 ohm single-ended impedance. When inactive, the transmit serial

ports have a 50 ohm single-ended impedance.

EDEN - When active, the internal 8B/10B encoder for the transmitter and decoder for the receiver is enabled. When inactive,

the internal 8B/10B encoder for the transmitter and the internal 8B/10B decoder for the receiver are bypassed.

CDETEN - When active, along with the ICTRL bit in the Global Configuration register active, enables comma detection.

When inactive, along with ICTRL bit in the Global Configuration register active, disables comma detection.

WRAPEN - When active, along with the ICTRL bit in the Global Configuration register active, the selected wrap (loopback)

mode (serial or parallel) is enabled. When inactive, along with ICTRL bit in the Global Configuration register active, normal

transmit and receive mode is enabled.

LCKREF - When active, along with the ICTRL bit in the Global Configuration register active, the receiver PLL locks to the

internal global transmit clock. When inactive, along with ICTRL bit in the Global Configuration register active, the receive

PLL attempts to phase lock to the incoming receive data stream on the RDn+/- pins.

PWRDWN - When active, the selected PMA is put into the power-down state. All analog blocks are powered down, all clocks

are off. The register values remain unchanged. When inactive, the selected PMA is in its normal operational mode.

RESET - When active the transmitter and receiver are completely powered down. When inactive the transmitter and receiver

are operational.

PMA STATUS REGISTER

TFERR - When active, there was an over run or under run in the transmit FIFO. When inactive, there are no error conditions

from the transmit fifo.

SIGDET - When active, indicates there is a signal on the RDSP/N inputs. When inactive, indicates there is no signal on the

RDSP/N inputs.

RXLOCK - When active, the receive PLL is locked to either the internal TX clock (see ALOCK and LCK_REF bit descriptions)

or to the incoming RX serial data stream. When inactive, the receive PLL is not locked.

Table 10: PMAn Status Register (Address=12h, Read Only)

BIT NAME R/W DESCRIPTION DEFAULT

15:3 Reserved NA 0

2 TFERR R 1 = An over-run or under-run occurred in the transmit FIFO

0 = There are no error conditions from the transmit FIFO

1 SIGDET R 1 = Indicates there is a signal on the RDSP/N inputs

0 = Indicates there is no signal on the RDSP/N inputs

0 RXLOCK R 1 = Receive PLL is locked to the TX reference or RX data

0 = Receive PLL is not locked

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■ BCM8002 Advance Data Sheet

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RECEIVER EQUALIZER CONTROL REGISTER 1

EQEN - When active, the receive FIR tap automatically adapts to the incoming signal on RDSP/N. When inactive, the receive

FIR tap is set by the value in the RTAP bits.

RTAP[5] - Sets the amount of receive equalization.

RTAP[4] - Sets the amount of receive equalization.

RTAP[3] - Sets the amount of receive equalization.

RTAP[2] - Sets the amount of receive equalization.

RTAP[1] - Sets the amount of receive equalization.

RTAP[0] - Sets the amount of receive equalization.

Table 11: Receiver Equalizer Control Register (Address=19h)

BIT NAME R/W DESCRIPTION DEFAULT

15 Reserved NA 0

14 EQEN R/W 1 = Receive FIR tap automatically adapts to incoming signal

0 = Receive FIR tap is set by the value in the RTAP bits

13 RTAP[5] R/W Sets the amount of receive equalization. 1

12 RTAP[4] R/W Sets the amount of receive equalization. 0

11 RTAP[3] R/W Sets the amount of receive equalization. 0

10 RTAP[2] R/W Sets the amount of receive equalization. 1

9 RTAP[1] R/W Sets the amount of receive equalization. 0

8 RTAP[0] R/W Sets the amount of receive equalization. 1

7:0 Reserved NA 0Fh

Advance Data Sheet ■ BCM8002

05/22/01

Broadcom Corporation

Document 8002-DS03-R Page 17

Section 6: Timing Diagrams

Figure 3: TBI Comma Resynchronization Timing Diagram (in phase)

Comma, K28.5 code-group 1code-group -3 code-group -2 code-group -1code-group -5 code-group -4

RD+/-

RX_CLK1

RX_CLK0

Comma, K28. 5 code-group 1code-group -2 code-group -1 code-group 2 code-group 3

Trclat = 20-bits

code-group -3

Trclat = 20-bits

COM_DET

■ BCM8002 Advance Data Sheet

05/22/01

Broadcom Corporation

Page 18 Document 8002-DS03-R

Figure 4: TBI Comma Resynchronization Timing Diagram (2-bits early)

RD+/-

RX_CLK1

RX_CLK0

Trclat = 22-bits

Trclat = 20-bits

Corrupted data

Comma, K28. 5 code-group 1code-group -3 code-group -2 code-group -1code-group -5 code-group -4

code-group 1code-group -2 code-group 2 code-group 3code-group -3 code-group -1 Comma, K28. 5

over lap

COM_DET

Broadcom Corporation

Document 8002-DS03-R Page 19

Advance Data Sheet ■ BCM8002

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Section 7: Electrical Specifications

GENERAL SPECIFICATIONS

Table 12: Absolute Maximum Ratingsa

a. These specifications indicate levels where permanent damage to the device may occur. Functional operation is not

guaranteed under these conditions. Operations at absolute maximum conditions for extended periods may adversely affect

long-term reliability of the device.

Symbol Parameter Min Typ Max Units

VDD Supply Voltage GND-0.3 3.3 V

VIInput Voltage, all signal inputs GND-0.3 VDD+0.3 V

IIInput Current, all signal inputs

(SSTL/HSTL depends on VTT)

10 mA

TSTG Storage temperature -40 125 oC

VESD Electrostatic Discharge 2000 V

Table 13: Recommended Operating Conditions

Symbo

lParameter Conditions Min Typ Max Units

VDD Power supply voltage ±5% 2.38 2.5 2.62 V

IDD Power Supply Current 1100 mA

PDPower Dissipation Pd(max) @ VDD=Max, Pd(typ) @ VDD=Typ 2.5 W

FREF REFCLK± Frequency 62.5 - 125 MHz

REFCLK± Accuracy -100 100 ppm

RBIAS RBIAS Value 1% resistor to ground 1.24K Ω

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■ BCM8002 Advance Data Sheet

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PMA INTERFACE SPECIFICATIONS

Figure 5: Input / Output Valid Levels for AC Measurements

Table 14: PMA Interface DC Specifications

Symbol Parameter Conditions Min Typ Max Units

PINS: TX[9:0], TX_CLK, FRST (SSTL_2 compliant inputs, have 50 Ohm terminators to VTT)

VIH Input High Voltage Vref+0.18 VDDQ+0.3 V

VIL Input Low Voltage -0.3 Vref-0.18 V

IIH Input High Current IOVDD = Max, Vin = IOVDD ±1µA

IIL Input Low Current IOVDD = Max, Vin = 0V ±1µA

CIN Input Capacitance 1.4 pf

PINS: EN_CDET, EWRAP, LCK_REFb

VIH Input High Voltage 2.0 VDD+0.5 V

VIL Input Low Voltage -0.3 0.8 V

IIH Input High Current VDD = Max, Vin = VDD ±1µA

IIL Input Low Current VDD = Max, Vin = 0V ±1µA

CIN Input Capacitance 1.5 pf

PINS: RX[9:0], RX_CLK0, RX_CLK1, COM_DET, FERR (SSTL_2 compliant outputs)

VOH Output High Voltage Ioh = -7.6mA, VDDQ = min 2.0 V

VOL Output Low Voltage Iol = 7.6mA, VDDQ = max 0.4 V

TRRise Time 1.5 ns

TFFall Time 1.5 ns

* For information on interfacing with LVTTL, please refer to the Application Note.

Inputs

Vih

Vil

Vo h

Vo l

Tr Tf

Outputs

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Document 8002-DS03-R Page 21

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Figure 6: Transmit Interface Timing Diagram, SDR

Table 15: PMA Transmit AC Specifications, SDR

Symbol Parameter Conditions Min Typ Max Units

TPERIOD TX_CLK period 8.0 ns

TSETUP Data setup to rising

TX_CLK

500 ps

THOLD Data hold from rising

TX_CLK

500 ps

TDUTY TX_CLK duty cycle 45 65 %

TTRLAT TX to TD± latency 7 8.5 bits

Tperiod

Tsetup

Thold

VALID

DATA 2

VALID

DATA 0

VALID

DATA 1

TX_CLK

TX[9:0]

a b c d e i f g h ja b c d e i f g h j

TD+/- a b c d e i f g h j

Ttrlat

DATA 0 DATA 1

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■ BCM8002 Advance Data Sheet

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Figure 7: Receiver Interface Timing Diagram SDR

Table 16: PMA Receive Bus AC Specification, SDR

Symbol Parameter Conditions Min Typ Max Units

For PMAn Reg(11h) bit 10 “RCKSEL” = 1

TFREQ RXn_CLK frequency 125 MHz

TDRIFT RXn_CLK drift rate Time to drift from 126MHz to 127MHz or

120MHz to 119MHz or 63.5MHz to

64.5MHz or 60MHz to 59MHz after lock

was established.

0.2 µs/

MHz

TPERIOD RXn[9:0] setup before

rising RXn_CLK

1200 ps

THOLD RXn[9:0] hold after

RXn_CLK rising

800 ps

TDUTY RXn_CLK duty cycle 45 65 %

TRCLAT RD± to RX latency 14 16 bits

COMMA

code-group

VALID

DATA 2

VALID

DATA 1

RX_CLK1

RX_CLK0

RX[9:0]

COM_DET

Tsetup

Thold

“0”

(May Toggle)

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Document 8002-DS03-R Page 23

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Figure 8: Receiver Interface Timing Diagram DDR

COMMA

code-group

VALID

DATA 2

VALID

DATA 1

RX_CLK1

RX_CLK0

RX[9:0]

COM_DET

Tsetup

Thold

Tsetup

Thold

Ta-b

Tsetup

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■ BCM8002 Advance Data Sheet

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PMD INTERFACE SPECIFICATIONS

TRANSMITTER ELECTRICAL SPECIFICATIONS

Figure 9: Balanced Transmitter Test Load

Table 17: PMA Receive Bus AC Specification, DDR

Symbol Parameter Conditions Min Typ Max Units

For PMAn Reg(11h) bit 10 “RCKSEL” = 0

TFREQ RXn_CLK frequency 62.5 MHz

TDRIFT RXn_CLK drift rate Time to drift from 126MHz to 127MHz

or 120MHz to 119MHz or 63.5MHz to

64.5MHz or 60MHz to 59MHz after lock

was established.

0.2 µs/

MHz

TSETUP RXn[9:0] setup before

rising or falling RXn_CLK

1200 ps

THOLD RXn[9:0] hold after

RXn_CLK rising or falling

800 ps

TDUTY RXn_CLK duty cycle 45 65 %

TA-B RXn_CLK skew Channel Rate = 1.25GBd 7.5 8.5 ns

TD+

TP2

TP1

TD-

Ω ±

1% / 50

Ω ±

1% / 50

Ω ±

Transmit Network

68nFd

Broadcom Corporation

Document 8002-DS03-R Page 25

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Figure 10: Transmit Eye Diagrams at TP1 / TP2

Table 18: Transmitter Characteristics at TP1 / TP2

Symbol Parameter Conditions Min Typ Max Units

CKTOL1 Clock Tolerance -100 +100 ppm

FSIG1 Nominal Signalling

Speed

1.25 GBd

VOD1 Differential Output Am-

plitude

1000 mVppd

VOO1 Differential Output Off

Voltage

PMDn powered-down or EWRAP = 1, etc. 170 mVppd

TRF1 Rise / Fall Time 20% - 80% 85 100 ps

TDS11 Differential Skew T(50% rising / falling) of TD+ - T(50% fall-

ing / rising) of TD-

25 ps

TOVS1 Overshoot amount over the average amplitude of the

driving “1” or “0” value.

10 %

TUDS1 Undershoot amount under the average amplitude of

the driving “1” or “0” value.

20 %

1.1

1.0

0.8

0.5

0.2

0.0

-0.1

0.0 0.14 0.34 0.860.66 1.0

1000

550

-1000

0.0 0.14 0.34 0.860.66 1.0

Differential Ampl itude (mVppd)

Normalized Time (Unit Interval)

Normalized Amplitude

Normalized Eye Diagram Absolute Eye Diagram

Normalized Time (Unit Interval)

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■ BCM8002 Advance Data Sheet

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Figure 11: TD± Transmit Signal Timing Diagram

RECEIVER ELECTRICAL SPECIFICATIONS

Figure 12: Receiver Test Diagram

TJIT1 peak-to-peak Jitter Total jitter = random jitter + deterministic

jitter

peak-to-peak = ±7σ (14σ)

0.15

120

UIa

a. UI (Unit Interval) = 1 / Fsig.

Table 18: Transmitter Characteristics at TP1 / TP2

Symbol Parameter Conditions Min Typ Max Units

Tovs

Tuds

Tds Tds

TD+/-

50%

Vod

RD+

TP4

TP3

RD-

Receive Network

Broadcom Corporation

Document 8002-DS03-R Page 27

Advance Data Sheet ■ BCM8002

05/22/01

Figure 13: Receive Eye Diagram Mask at TP3

Table 19: Receiver Characteristics at TP4

Symbol Parameter Conditions Min Typ Max Units

CKTOL4 Clock Tolerance -100 +100 ppm

FSIG4 Nominal Signalling

Speed

1.25 GBd

VIS4 Differential Input Sensi-

tivity

200 2000 mVppd

ZI4F Input Impedance, 50Ω

mode Through Connectiona

At Terminationb

100

120

107

Ω

ZI4S Input Impedance, 75Ω

mode

Through Connection

At Termination

120

140

150

180

160

Ω

TDS4 Differential Skew T(50% rising / falling) of TD+ to T(50%

falling / rising) of TD-

0.21 UIc

1000

200

-200

-1000

0.0 0.3 0.5 0.7 1.0

Differential Amplitude (mVppd)

Normalized Time (Unit Interval)

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■ BCM8002 Advance Data Sheet

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Figure 14: RD± Receiver Signal Timing Diagram

TJIT4 peak-to-peak Jitter Tol-

erance

Total jitter tolerance = random jitter + de-

terministic jitter: peak-to-peak = ± 7σ

(14σ)

0.749 UI

a. TDR rise time = 85ps, exception window = 700ps. Within the exception window no single impedance excursion shall exceed

the “through connection” impedance tolerance for a period of twice the TDR rise time.

b. The input impedance at TP3 shall be recorded 4.0ns following the reference location determined by an open connector

between TP3 and TP4.

c. UI (Unit Interval) = 1 / Fsig.

Table 19: Receiver Characteristics at TP4

Symbol Parameter Conditions Min Typ Max Units

Tds Tds

RD±50% Vis

Broadcom Corporation

Document 8002-DS03-R Page 29

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■ BCM8002 Advance Data Sheet

05/22/01

Broadcom Corporation

800

2-DS

-R

Section 8: Ballout Assignment

BALLOUT BY BALL NUMBER

Table 20: Ballout by Ball Number

Ball Signal Name

A1 EWRAP1

A2 TMS

A3 TDI

A4 TCK

A5 RESET

A6 TXCKO

A7 DVDD

A8 DVSS

A9 VTT

A10 TX1_8

A11 TX1_9

A12 FRST1

A13 VTT

A14 DVSS

A15 DVSS

A16 DVSS

B1 CVDD

B2 CVDD

B3 CVDD

B4 AVSS

B5 LCK_REFB1

B6 TDO

B7 DVDD

B8 DVSS

B9 VTT

B10 TX1_4

B11 TX1_6

B12 TX1_7

B13 VTT

B14 DVSS

B15 DVSS

B16 DVSS

C1 RESERVED

C2 RESERVED

C3 AVSS

C4 AVSS

C5 TRSTB

C6 EN_CDET1

C7 DVDD

C8 DVSS

C9 DVSS

C10 TX1_5

C11 TX1_3

C12 TX1_2

C13 DVSS

C14 DVSS

C15 VDDQ

C16 VDDQ

D1 AVDD

D2 AVDD

D3 AVSS

D4 AVSS

D5 DVSS

D6 DVSS

D7 DVDD

D8 DVSS

D9 TX1_CLK

D10 TX1_0

D11 TX1_1

D12 VREFL

D13 DVSS

D14 DVSS

D15 COM_DET1

D16 RX1_9

E1 RDN1

E2 RDP1

E3 CVDD

E4 AVSS

E5 DVSS

E6 DVSS

E7 DVSS

E8 DVSS

E9 DVSS

E10 DVSS

E11 DVSS

E12 DVSS

Ball Signal Name

E13 FERR1

E14 RX1_7

E15 RX1_8

E16 RX1_6

F1 AVSS

F2 AVSS

F3 CVDD

F4 REFCLKN

F5 DVSS

F6 DVSS

F7 DVSS

F8 DVSS

F9 DVSS

F10 DVSS

F11 DVSS

F12 DVSS

F13 RX1_5

F14 RX1_4

F15 RX1_2

F16 RX1_1

G1 TDN1

G2 TDP1

G3 CVDD

G4 REFCLKP

G5 DVSS

G6 DVSS

G7 DVSS

G8 DVSS

G9 DVSS

G10 DVSS

G11 DVSS

G12 DVSS

G13 RX1_3

G14 RX1_0

G15 RX1_CLK0

G16 RX1_CLK1

H1 AVDD

H2 AVDD

Ball Signal Name

Advance Data Sheet ■ BCM8002

05/22/01

Broadcom Corporation

800

2-DS

-R Pa

H3 RESERVED

H4 AVDD

H5 DVSS

H6 DVSS

H7 DVSS

H8 DVSS

H9 DVSS

H10 DVSS

H11 DVSS

H12 DVSS

H13 VDDQ

H14 VDDQ

H15 DVSS

H16 DVSS

J1 AVDD

J2 AVDD

J3 RESERVED

J4 RESERVED

J5 DVSS

J6 DVSS

J7 DVSS

J8 DVSS

J9 DVSS

J10 DVSS

J11 DVSS

J12 DVSS

J13 DVSS

J14 DVSS

J15 VDDQ

J16 VDDQ

K1 TDN2

K2 TDP2

K3 AVDD

K4 RBIAS

K5 DVSS

K6 DVSS

K7 DVSS

K8 DVSS

K9 DVSS

K10 DVSS

K11 DVSS

K12 DVSS

K13 RX2_3

K14 RX2_0

K15 RX2_CLK0

K16 RX2_CLK1

Ball Signal Name

L1 AVSS

L2 AVSS

L3 CVDD

L4 AVSS

L5 DVSS

L6 DVSS

L7 DVSS

L8 DVSS

L9 DVSS

L10 DVSS

L11 DVSS

L12 DVSS

L13 RX2_4

L14 RX2_5

L15 RX2_2

L16 RX2_1

M1 RDN2

M2 RDP2

M3 CVDD

M4 AVSS

M5 DVSS

M6 DVSS

M7 DVSS

M8 DVSS

M9 DVSS

M10 DVSS

M11 DVSS

M12 DVSS

M13 FERR2

M14 RX2_9

M15 RX2_8

M16 RX2_6

N1 AVDD

N2 AVDD

N3 AVSS

N4 AVSS

N5 DVSS

N6 DVSS

N7 DVDD

N8 DVSS

N9 TX2_CLK

N10 TX2_0

N11 TX2_1

N12 VREFR

N13 DVSS

N14 DVSS

Ball Signal Name

N15 COM_DET2

N16 RX2_7

P1 RESERVED

P2 RESERVED

P3 AVSS

P4 AVSS

P5 PHYAD4

P6 EN_CDET2

P7 DVDD

P8 DVSS

P9 DVSS

P10 TX2_5

P11 TX2_3

P12 TX2_2

P13 DVSS

P14 DVSS

P15 VDDQ

P16 VDDQ

R1 CVDD

R2 CVDD

R3 CVDD

R4 AVSS

R5 PHYAD3

R6 PHYAD1

R7 DVDD

R8 DVSS

R9 VTT

R10 TX2_4

R11 TX2_6

R12 TX2_7

R13 VTT

R14 DVSS

R15 DVSS

R16 DVSS

T1 EWRAP2

T2 LCK_REFB2

T3 PHYAD2

T4 PHYAD0

T5 MDIO

T6 MDC

T7 DVDD

T8 DVSS

T9 VTT

T10 TX2_8

T11 TX2_9

T12 FRST2

Ball Signal Name

■ BCM8002 Advance Data Sheet

05/22/01

Broadcom Corporation

2 D

800

2-DS

-R

BALLOUT BY SIGNAL NAME

Table 21: Ballout by Signal Name

T13 VTT

T14 DVSS

T15 DVSS

T16 DVSS

Ball Signal Name

Signal Name Ball

AVDD D1

AVDD D2

AVDD H1

AVDD H2

AVDD H4

AVDD J1

AVDD J2

AVDD K3

AVDD N1

AVDD N2

AVSS B4

AVSS C3

AVSS C4

AVSS D3

AVSS D4

AVSS E4

AVSS F1

AVSS F2

AVSS L1

AVSS L2

AVSS L4

AVSS M4

AVSS N3

AVSS N4

AVSS P3

AVSS P4

AVSS R4

COM_DET1 D15

COM_DET2 N15

CVDD B1

CVDD B2

CVDD B3

CVDD E3

CVDD F3

CVDD G3

CVDD L3

CVDD M3

CVDD R1

CVDD R2

CVDD R3

DVDD A7

DVDD B7

DVDD C7

DVDD D7

DVDD N7

DVDD P7

DVDD R7

DVDD T7

DVSS A14

DVSS A15

DVSS A16

DVSS B14

DVSS B15

DVSS B16

DVSS B8

DVSS C13

Signal Name Ball

DVSS C14

DVSS C8

DVSS C9

DVSS D13

DVSS D14

DVSS D5

DVSS D6

DVSS D8

DVSS E5

DVSS E6

DVSS E7

DVSS E8

DVSS E9

DVSS E10

DVSS E11

DVSS E12

DVSS F5

DVSS F6

DVSS F7

DVSS F8

DVSS F9

DVSS F10

DVSS F11

DVSS F12

DVSS G5

DVSS G6

DVSS G7

DVSS G8

Signal Name Ball

Advance Data Sheet ■ BCM8002

05/22/01

Broadcom Corporation

800

2-DS

-R Pa

DVSS G9

DVSS G10

DVSS G11

DVSS G12

DVSS H5

DVSS H6

DVSS H7

DVSS H8

DVSS H9

DVSS H10

DVSS H11

DVSS H12

DVSS H15

DVSS H16

DVSS J5

DVSS J6

DVSS J7

DVSS J8

DVSS J9

DVSS J10

DVSS J11

DVSS J12

DVSS J13

DVSS J14

DVSS K5

DVSS K6

DVSS K7

DVSS K8

DVSS K9

DVSS K10

DVSS K11

DVSS K12

DVSS L5

DVSS L6

DVSS L7

DVSS L8

DVSS L9

Signal Name Ball

DVSS L10

DVSS L11

DVSS L12

DVSS M5

DVSS M6

DVSS M7

DVSS M8

DVSS M9

DVSS M10

DVSS M11

DVSS M12

DVSS N13

DVSS N14

DVSS N5

DVSS N6

DVSS N8

DVSS P13

DVSS P14

DVSS P8

DVSS P9

DVSS R14

DVSS R15

DVSS R16

DVSS R8

DVSS T14

DVSS T15

DVSS T16

DVSS T8

EN_CDET1 C6

EN_CDET2 P6

EWRAP1 A1

EWRAP2 T1

FERR1 E13

FERR2 M13

FRST1 A12

FRST2 T12

LCK_REFB1 B5

Signal Name Ball

LCK_REFB2 T2

MDC T6

MDIO T5

PHYAD0 T4

PHYAD1 R6

PHYAD2 T3

PHYAD3 R5

PHYAD4 P5

RBIAS K4

RDN1 E1

RDN2 M1

RDP1 E2

RDP2 M2

REFCLKN F4

REFCLKP G4

RESERVED C1

RESERVED C2

RESERVED H3

RESERVED J3

RESERVED J4

RESERVED P1

RESERVED P2

RESET A5

RX1_0 G14

RX1_1 F16

RX1_2 F15

RX1_3 G13

RX1_4 F14

RX1_5 F13

RX1_6 E16

RX1_7 E14

RX1_8 E15

RX1_9 D16

RX1_CLK0 G15

RX1_CLK1 G16

RX2_0 K14

RX2_1 L16

Signal Name Ball

■ BCM8002 Advance Data Sheet

05/22/01

Broadcom Corporation

4 D

800

2-DS

-R

RX2_2 L15

RX2_3 K13

RX2_4 L13

RX2_5 L14

RX2_6 M16

RX2_7 N16

RX2_8 M15

RX2_9 M14

RX2_CLK0 K15

RX2_CLK1 K16

TCK A4

TDI A3

TDN1 G1

TDN2 K1

TDO B6

TDP1 G2

TDP2 K2

TMS A2

TRSTB C5

TX1_0 D10

TX1_1 D11

TX1_2 C12

TX1_3 C11

TX1_4 B10

TX1_5 C10

TX1_6 B11

TX1_7 B12

TX1_8 A10

TX1_9 A11

TX1_CLK D9

TX2_0 N10

TX2_1 N11

TX2_2 P12

TX2_3 P11

TX2_4 R10

TX2_5 P10

TX2_6 R11

Signal Name Ball

TX2_7 R12

TX2_8 T10

TX2_9 T11

TX2_CLK N9

TXCKO A6

VDDQ C15

VDDQ C16

VDDQ H13

VDDQ H14

VDDQ J15

VDDQ J16

VDDQ P15

VDDQ P16

VREFL D12

VREFR N12

VTT A13

VTT A9

VTT B13

VTT B9

VTT R13

VTT R9

VTT T13

VTT T9

Signal Name Ball

Broadcom Corporation

Document 8002-DS03-R Page 35

Advance Data Sheet ■ BCM8002

05/22/01

Section 9: Mechanical Information

Figure 15: 256-Pin fpBGA

Broadcom Corporation

Page 36 Document 8002-DS03-R

■ BCM8002 Advance Data Sheet

05/22/01

Section 10: Thermal

THERMAL INFORMATION

This section includes basic thermal information pertaining to the BCM8002 and the 256 ball fpBGA package.

Table 22: Basic Thermal Data

PACKAGE AMBIENT TEMPERATURE RANGE θja (still air) θjb θjc

256 17x17 mm fpBGA 0° to 70° C19.02 °C/W 6.02 °C/W 5.84 °C/W

Table 23: Theta-JA vs. Airflow (@2.8 W)

256 fpBGA Package

AIR FLOW (feet per minute)

0100 200 400 600

Theta-JA (deg C/W) 19.02 16.70 15.85 14.84 14.16

Broadcom Corporation

Document 8002-DS03-R Page 37

Advance Data Sheet ■ BCM8002

05/22/01

Section 11: Ordering Information

DEVICE INFORMATION

PART NUMBER PIN PACKAGE AMBIENT TEMPERATURE RANGE

BCM8002KPB 256 17x17mm fpBGA 0° to 70° C

Document 8002-DS03-R

Broadcom Corporation

16215 Alton Parkway

P.O. Box 57013

Irvine, California 92619-7013

Phone: 949-450-8700

Fax: 949-450-8710

Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.

Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation

does not assume any liability arising out of the application or use of this information, nor the application or use of any product or

circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

■ BCM8002 Advance Data Sheet

05/22/01