128K x 36 3.3V Synchronous ZBTTM SRAM 2.5V I/O, Burst Counter Pipelined Outputs Features IDT71V2546S/XS Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V2546 contains data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V2546 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V2546 has an on-chip burst counter. In the burst mode, the IDT71V2546 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V2546 SRAM utilize IDT's latest high-performance CMOS process and is packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA). 128K x 36 memory configurations Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (5%), 2.5V I/O Supply (VDDQ) Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP) and 119 ball grid array (BGA) Description The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Pin Description Summary A0-A16 Ad d re ss Inp uts Inp ut Synchro no us CE1, CE2, CE2 Chip Enab le s Inp ut Synchro no us OE Outp ut Enab le Inp ut Asynchro no us R/W Re ad /Write Sig nal Inp ut Synchro no us CEN Clo ck Enab le Inp ut Synchro no us BW1, BW2, BW3, BW4 Ind ivid ual Byte Write Se le cts Inp ut Synchro no us CLK Clo ck Inp ut N/A ADV/LD Ad vance b urst ad d re ss / Lo ad ne w ad d re ss Inp ut Synchro no us LBO Line ar / Inte rle ave d Burst Ord e r Inp ut Static ZZ S le e p Mo d e Inp ut Synchro no us I/O0-I/O31, I/OP1-I/OP4 Data Inp ut / Outp ut I/O Synchro no us VDD, VDDQ Co re Po we r, I/O Po we r Sup p ly Static VSS Gro und Sup p ly Static 5294 tb l 01 1 (c)2011 Integrated Device Technology, Inc. APRIL 2011 DSC-5294/07 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol Pin Function I/O Active Description A0-A16 Ad d re ss Inp uts I N/A Synchro no us Ad d re ss inp uts. The ad d re ss re g iste r is trig g e re d b y a co mb inatio n o f the rising e d g e o f CLK, ADV/LD lo w, CEN lo w, and true chip e nab le s. ADV/LD Ad vance / Lo ad I N/A ADV/LD is a synchro no us inp ut that is use d to lo ad the inte rnal re g iste rs with ne w ad d re ss and co ntro l whe n it is samp le d lo w at the rising e d g e o f clo ck with the chip se le cte d . Whe n ADV/LD is lo w with the chip d e se le cte d , any b urst in p ro g re ss is te rminate d . Whe n ADV/LD is samp le d hig h the n the inte rnal b urst co unte r is ad vance d fo r any b urst that was in p ro g re ss. The e xte rnal ad d re sse s are ig no re d whe n ADV/LD is samp le d hig h. R/W Re ad / Write I N/A R/W sig nal is a synchro no us inp ut that id e ntifie s whe the r the curre nt lo ad cycle initiate d is a Re ad o r Write acce ss to the me mo ry array. The d ata b us activity fo r the curre nt cycle take s p lace two clo ck cycle s late r. CEN Clo ck Enab le I LOW Synchro no us Clo ck Enab le Inp ut. Whe n CEN is samp le d hig h, all o the r synchro no us inp uts, includ ing clo ck are ig no re d and o utp uts re main unchang e d . The e ffe ct o f CEN samp le d hig h o n the d e vice o utp uts is as if the lo w to hig h clo ck transitio n d id no t o ccur. Fo r no rmal o p e ratio n, CEN must b e samp le d lo w at rising e d g e o f c lo c k . BW1-BW4 Ind ivid ual Byte Write Enab le s I LOW Synchro no us b yte write e nab le s. Each 9-b it b yte has its o wn active lo w b yte write e nab le . On lo ad write cycle s (Whe n R/W and ADV/LD are samp le d lo w) the ap p ro p riate b yte write sig nal (BW1-BW4) must b e valid . The b yte write sig nal must also b e valid o n e ach cycle o f a b urst write . Byte Write sig nals are ig no re d whe n R/W is samp le d hig h. The ap p ro p riate b yte (s) o f d ata are writte n into the d e vice two cycle s late r. BW1-BW4 can all b e tie d lo w if always d o ing write to the e ntire 36-b it wo rd . CE1, CE2 Chip Enab le s I LOW Synchro no us active lo w chip e nab le . CE1 and CE2 are use d with CE2 to e nab le the IDT71V2546. (CE1 o r CE2 samp le d hig h o r CE2 samp le d lo w) and ADV/LD lo w at the rising e d g e o f clo ck, initiate s a d e se le ct cycle . The ZBTTM has a two cycle d e se le ct, i.e ., the d ata b us will tri-state two clo ck cycle s afte r d e se le ct is initiate d . CE2 Chip Enab le I HIGH Synchro no us active hig h chip e nab le . CE2 is use d with CE1 and CE2 to e nab le the chip . CE2 has inve rte d p o larity b ut o the rwise id e ntical to CE1 and CE2. CLK Clo ck I N/A This is the clo ck inp ut to the IDT71V2546. Exce p t fo r OE, all timing re fe re nce s fo r the d e vice are mad e with re sp e ct to the rising e d g e o f CLK. I/O0-I/O31 I/OP1-I/OP4 Data Inp ut/Outp ut I/O N/A Synchro no us d ata inp ut/o utp ut (I/O) p ins. Bo th the d ata inp ut p ath and d ata o utp ut p ath are re g iste re d and trig g e re d b y the rising e d g e o f CLK. LBO Line ar Burst Ord e r I LOW Burst o rd e r se le ctio n inp ut. Whe n LBO is hig h the Inte rle ave d b urst se q ue nce is se le cte d . Whe n LBO is lo w the Line ar b urst se q ue nce is se le cte d . LBO is a static inp ut and it must no t chang e d uring d e vice o p e ratio n. OE Outp ut Enab le I LOW Asynchro no us o utp ut e nab le . OE must b e lo w to re ad d ata fro m the IDT71V2546. Whe n OE is hig h the I/O p ins are in a hig h-imp e d ance state . OE d o e s no t ne e d to b e active ly co ntro lle d fo r re ad and write cycle s. In no rmal o p e ratio n, OE can b e tie d lo w. ZZ S le e p Mo d e I HIGH Synchro no us sle e p mo d e inp ut. ZZ HIGH will g ate the CLK inte rnally and p o we r d o wn the IDT71V2546 to its lo we st p o we r co nsump tio n le ve l. Data re te ntio n is g uarante e d in Sle e p Mo d e . This p in has an inte rnal p ulld o wn. VDD Po we r Sup p ly N/A N/A 3.3V co re p o we r sup p ly. VDDQ Po we r Sup p ly N/A N/A 2.5V I/O Sup p ly. VSS Gro und N/A N/A Gro und . 5294 tb l 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Functional Block Diagram LBO 128Kx36 BIT MEMORY ARRAY Address A [0:16] D Q Address D Q Control CE1, CE2, CE2 R/W Input Register CEN ADV/LD BWx D DI Q DO Control Logic Clk Mux Sel D Clk Clock Output Register Q Gate OE 5294 drw 01a Data I/O [0:31], I/O P[1:4] Recommended DC Operating Conditions Symbol Min. Typ. Max. Unit VDD Co re Sup p ly Vo ltag e 3.135 3.3 3.465 V VDDQ I/O Sup p ly Vo ltag e 2.375 2.5 2.625 V VSS Sup p ly Vo ltag e 0 0 0 V 1.7 ____ VDD +0.3 1.7 ____ VIH VIH VIL Parameter Inp ut Hig h Vo ltag e - Inp uts Inp ut Hig h Vo ltag e - I/O Inp ut Lo w Vo ltag e (1) -0.3 ____ (2) VDDQ +0.3 0.7 NOTES: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle. V V V 5294 tb l 03 6.42 3 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Grade Temperature(1) VSS VDD VDDQ Co mme rcial 0 C to +70 C 0V 3.3V 5% 2.5V 5% Ind ustrial -40 C to +85 C 0V 3.3V 5% 2.5V 5% 5294 tb l 05 NOTE: 1. TA is the "instant on" case temperature. CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD NC(2) NC(2) A8 A9 A6 A7 CE1 Pin Configuration -- 128K x 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD(1) VDD VDD(1) VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 2 79 3 78 77 4 5 6 76 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 64 17 18 19 63 62 20 61 21 60 22 59 23 24 58 57 25 56 26 55 27 54 53 28 29 52 51 30 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VDD(1) VDD VSS/ZZ(3) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 , LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 5294 drw 02 Top View 100 TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is VIH. 2. Pins 83 and 84 are reserved for future 8M and 16M respectively. 3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is VIL; on the latest die revision this pin supports ZZ (sleep mode). 6.42 4 IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) 100 TQFP Capacitance(1) (TA = +25 C, f = 1.0MHz) Commercial & Industrial Values Unit Te rminal Vo ltag e with Re sp e ct to GND -0.5 to +4.6 V Te rminal Vo ltag e with Re sp e ct to GND -0.5 to VDD V VTERM(4,6) Te rminal Vo ltag e with Re sp e ct to GND -0.5 to VDD +0.5 V VTERM(5,6) Te rminal Vo ltag e with Re sp e ct to GND -0.5 to VDDQ +0.5 V Symbol VTERM (2) VTERM(3,6) Rating Symbol Commercial Op e rating Te mp e rature -0 to +70 o C Industrial Op e rating Te mp e rature -40 to +85 o C -55 to +125 o C Te mp e rature Und e r Bias CIN Inp ut Cap acitance CI/O I/O Cap acitance Conditions Max. Unit VIN = 3d V 5 pF VOUT = 3d V 7 pF 5294 tb l 07 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 119 BGA Capacitance(1) (TA = +25 C, f = 1.0MHz) TA(7) TBIAS Parameter(1) Symbol Parameter(1) CIN Inp ut Cap acitance CI/O I/O Cap acitance Conditions Max. Unit VIN = 3d V 7 pF VOUT = 3d V 7 pF 5294 tb l 07a -55 to +125 o TSTG Sto rag e Te mp e rature C PT Po we r Dissip atio n 2.0 W IOUT DC Outp ut Curre nt 50 mA NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 5294 tb l 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. TA is the "instant on" case temperature. 6.42 5 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Configuration -- 128K x 36, 119 BGA 1 2 3 4 5 6 7 A VDDQ A6 A4 NC(2) A8 A16 VDDQ B NC CE 2 A3 ADV/LD A9 CE2 NC C NC A7 A2 VDD A12 A15 NC D I/O16 I/OP3 VSS NC VSS I/OP2 I/O15 E I/O17 I/O18 VSS CE1 VSS I/O13 I/O14 F VDDQ I/O19 VSS OE VSS I/O12 VDDQ G I/O20 I/O21 BW3 NC(2) BW 2 I/O11 I/O10 H I/O22 I/O23 VSS R/W VSS I/O9 I/O8 J VDDQ VDD VDD(1) VDD VDD(1) VDD VDDQ K I/O24 I/O26 VSS CLK VSS I/O6 I/O7 L I/O25 I/O27 BW4 NC BW1 I/O4 I/O5 M VDDQ I/O28 VSS CEN VSS I/O3 VDDQ N I/O29 I/O30 VSS A1 VSS I/O2 I/O1 P I/O31 I/OP4 VSS A0 VSS I/OP1 I/O0 R NC A5 LBO VDD A13 NC T NC NC A10 A11 A14 NC NC/ZZ(3) U VDDQ NC NC NC NC NC VDD(1) VDDQ 5294 drw 13a Top View NOTES: 1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is VIH. 2. G4 and A4 are reserved for future 8M and 16M respectively. 3. Pin T7 supports ZZ (sleep mode) on the latest die revision. 6.42 6 , IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table(1) CEN R/W Chip(5) Enable ADV/LD BWx ADDRESS USED PREVIOUS CYCLE CURRENT CYCLE I/O(6) (2 cycles later) L L S e le c t L Valid Exte rnal X LOAD WRITE D(7) L H S e le c t L X Exte rnal X LOAD READ Q(7) L X X H Valid Inte rnal LOAD WRITE / BURST WRITE BURST WRITE (Ad vance b urst co unte r)(2) D(7) L X X H X Inte rnal LOAD READ / BURST READ BURST READ (Ad vance b urst co unte r)(2) Q(7) L X De se le ct L X X X DESELECT o r STOP(3) HiZ L X X H X X DESELECT / NOOP NOOP HiZ H X X X X X X SUSPEND(4) Pre vio us Value 5294 tb l 08 NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/ Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false. 6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. 7. Q - Data read from the device, D - data written to the device. Partial Truth Table for Writes(1) R/W BW1 BW2 BW3 BW4 READ H X X X X WRITE ALL BYTES L L L L L L L H H H OPERATION WRITE BYTE 1 (I/O[0:7], I/OP1)(2) (2) WRITE BYTE 2 (I/O[8:15], I/OP2) L H L H H (2) WRITE BYTE 3 (I/O[16:23], I/OP3) L H H L H WRITE BYTE 4 (I/O[24:31], I/OP4)(2) L H H H L NO WRITE L H H H H 5294 tb l 09 NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Multiple bytes may be selected during the same cycle. 6.42 7 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Ad d re ss 0 0 0 1 1 0 1 1 Se co nd Ad d re ss 0 1 0 0 1 1 1 0 Third Ad d re ss 1 0 1 1 0 0 0 1 Fo urth Ad d re ss(1) 1 1 1 0 0 1 0 0 5294 tb l 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Ad d re ss 0 0 0 1 1 0 1 1 Se co nd Ad d re ss 0 1 1 0 1 1 0 0 Third Ad d re ss 1 0 1 1 0 0 0 1 Fo urth Ad d re ss(1) 1 1 0 0 0 1 1 0 5294 tb l 11 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram(1) CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 A29 A30 A31 A32 A33 A34 A35 A36 A37 C29 C30 C31 C32 C33 C34 C35 C36 C37 D/Q27 D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35 CLOCK (2) ADDRESS (A0 - A16) (2) CONTROL (R/W, ADV/LD, BWx) (2) DATA I/O [0:31], I/O P[1:4] , 5294 drw 03 NOTES: 1. This assumes CEN, CE1, CE2, CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. 6.42 8 IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2) Cycle Address R/W ADV/LD CE(1) CEN BWx OE I/O Comments n A0 H L L L X X X Lo ad re ad n+1 X X H X L X X X Burst re ad n+2 A1 H L L L X L Q0 Lo ad re ad n+3 X X L H L X L Q0+1 n+4 X X H X L X L Q1 NOOP n+5 A2 H L L L X X Z Lo ad re ad n+6 X X H X L X X Z Burst re ad n+7 X X L H L X L Q2 De se le ct o r STOP n+8 A3 L L L L L L Q2+1 Lo ad write n+9 X X H X L L X Z Burst write n+10 A4 L L L L L X D3 Lo ad write n+11 X X L H L X X D3+1 n+12 X X H X L X X D4 NOOP n+13 A5 L L L L L X Z Lo ad write n+14 A6 H L L L X X Z Lo ad re ad n+15 A7 L L L L L X D5 Lo ad write n+16 X X H X L L L Q6 Burst write n+17 A8 H L L L X X D7 Lo ad re ad n+18 X X H X L X X D7+1 Burst re ad n+19 A9 L L L L L L Q8 Lo ad write De se le ct o r STOP De se le ct o r STOP 5294 tb l 12 NOTES: 1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 2. H = High; L = Low; X = Don't Care; Z = High Impedance. Read Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 H L L L X X X Ad d re ss and Co ntro l me e t se tup n+1 X X X X L X X X Clo ck Se tup Valid n+2 X X X X X X L Q0 Co nte nts o f Ad d re ss A0 Re ad Out NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 9 5294 tb l 13 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Burst Read Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 H L L L X X X Ad d re ss and Co ntro l me e t se tup n+1 X X H X L X X X Clo ck Se tup Valid , Ad vance Co unte r n+2 X X H X L X L Q0 Ad d re ss A0 Re ad Out, Inc. Co unt n+3 X X H X L X L Q0+1 Ad d re ss A0+1 Re ad Out, Inc. Co unt n+4 X X H X L X L Q0+2 Ad d re ss A0+2 Re ad Out, Inc. Co unt n+5 A1 H L L L X L Q0+3 Ad d re ss A0+3 Re ad Out, Lo ad A1 n+6 X X H X L X L Q0 Ad d re ss A0 Re ad Out, Inc. Co unt n+7 X X H X L X L Q1 Ad d re ss A1 Re ad Out, Inc. Co unt n+8 A2 H L L L X L Q1+1 Ad d re ss A1+1 Re ad Out, Lo ad A2 5294 tb l 14 NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance.. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 L L L L L X X Ad d re ss and Co ntro l me e t se tup n+1 X X X X L X X X Clo ck Se tup Valid n+2 X X X X L X X D0 Write to Ad d re ss A0 5294 tb l 15 NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Burst Write Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 L L L L L X X Ad d re ss and Co ntro l me e t se tup n+1 X X H X L L X X Clo ck Se tup Valid , Inc. Co unt n+2 X X H X L L X D0 Ad d re ss A0 Write , Inc. Co unt n+3 X X H X L L X D0+1 Ad d re ss A0+1 Write , Inc. Co unt n+4 X X H X L L X D0+2 Ad d re ss A0+2 Write , Inc. Co unt n+5 A1 L L L L L X D0+3 Ad d re ss A0+3 Write , Lo ad A1 n+6 X X H X L L X D0 Ad d re ss A0 Write , Inc. Co unt n+7 X X H X L L X D1 Ad d re ss A1 Write , Inc. Co unt n+8 A2 L L L L L X D1+1 Ad d re ss A1+1 Write , Lo ad A2 NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 10 5294 tb l 16 IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 H L L L X X X Ad d re ss and Co ntro l me e t se tup n+1 X X X X H X X X Clo ck n+1 Ig no re d n+2 A1 H L L L X X X Clo ck Valid n+3 X X X X H X L Q0 Clo ck Ig no re d . Data Q0 is o n the b us. n+4 X X X X H X L Q0 Clo ck Ig no re d . Data Q0 is o n the b us. n+5 A2 H L L L X L Q0 Ad d re ss A0 Re ad o ut (b us trans.) n+6 A3 H L L L X L Q1 Ad d re ss A1 Re ad o ut (b us trans.) n+7 A4 H L L L X L Q2 Ad d re ss A2 Re ad o ut (b us trans.) 5294 tb l 17 NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation with Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 L L L L L X X Ad d re ss and Co ntro l me e t se tup . n+1 X X X X H X X X Clo ck n+1 Ig no re d . n+2 A1 L L L L L X X Clo ck Valid . n+3 X X X X H X X X Clo ck Ig no re d . n+4 X X X X H X X X Clo ck Ig no re d . n+5 A2 L L L L L X D0 Write Data D0 n+6 A3 L L L L L X D1 Write Data D1 n+7 A4 L L L L L X D2 Write Data D2 NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 11 5294 tb l 18 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Chip Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O(3) Comments n X X L H L X X ? De se le cte d . n+1 X X L H L X X ? De se le cte d . n+2 A0 H L L L X X Z Ad d re ss and Co ntro l me e t se tup n+3 X X L H L X X Z De se le cte d o r STOP. n+4 A1 H L L L X L Q0 Ad d re ss A0 Re ad o ut. Lo ad A1. n+5 X X L H L X X Z De se le cte d o r STOP. n+6 X X L H L X L Q1 Ad d re ss A1 Re ad o ut. De se le cte d . n+7 A2 H L L L X X Z Ad d re ss and co ntro l me e t se tup . n+8 X X L H L X X Z De se le cte d o r STOP. n+9 X X L H L X L Q2 Ad d re ss A2 Re ad o ut. De se le cte d . 5294 tb l 19 NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. Write Operation with Chip Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O(3) Comments n X X L H L X X ? De se le cte d . n+1 X X L H L X X ? De se le cte d . n+2 A0 L L L L L X Z Ad d re ss and Co ntro l me e t se tup n+3 X X L H L X X Z De se le cte d o r STOP. n+4 A1 L L L L L X D0 Ad d re ss D0 Write in. Lo ad A1. n+5 X X L H L X X Z De se le cte d o r STOP. n+6 X X L H L X X D1 Ad d re ss D1 Write in. De se le cte d . n+7 A2 L L L L L X Z Ad d re ss and co ntro l me e t se tup . n+8 X X L H L X X Z De se le cte d o r STOP. n+9 X X L H L X X D2 Ad d re ss D2 Write in. De se le cte d . NOTES: 1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. 6.42 12 5294 tb l 20 IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V5%) Symbol Parameter Test Conditions M i n. Max. Unit |ILI| Inp ut Le akag e Curre nt VDD = Max., VIN = 0V to VDD ___ 5 A |ILI| LBO, JTAG and ZZ Inp ut Le akag e Curre nt(1) VDD = Max., VIN = 0V to VDD ___ 30 A 5 A V |ILO| Outp ut Le akag e Curre nt VOUT = 0V to VDDQ, De vice De se le cte d ___ VOL Outp ut Lo w Vo ltag e IOL = +6mA, VDD = Min. ___ 0.4 VOH Outp ut Hig h Vo ltag e IOH = -6mA, VDD = Min. 2.0 ___ V 5294 tb l 21 NOTE: 1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(1) (VDD = 3.3V5%) 150MHz 133MHz 100MHz Unit Symbol Parameter Test Conditions Com'l Ind'l Com'l Ind'l Com'l Ind'l IDD Op e rating Po we r Sup p ly Curre nt De vice Se le cte d , Outp uts Op e n, ADV/LD = X, VDD = Max., VIN > VIH o r < VIL, f = fMAX(2) 325 335 300 310 250 260 mA ISB1 CMOS Stand b y Po we r Sup p ly Curre nt De vice De se le cte d , Outp uts Op e n, VDD = Max., VIN > VHD o r < VLD, f = 0(2,3) 40 45 40 45 40 45 mA ISB2 Clo ck Running Po we r Sup p ly Curre nt De vice De se le cte d , Outp uts Op e n, VDD = Max., VIN > VHD o r < VLD, f = fMAX(2.3) 120 130 110 120 100 110 mA ISB3 Id le Po we r Sup p ly Curre nt De vice Se le cte d , Outp uts Op e n, CEN > VIH, VDD = Max., VIN > VHD o r < VLD, f = fMAX(2,3) 40 45 40 45 40 45 mA NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V. AC Test Loads AC Test Conditions VDDQ/2 (VDDQ = 2.5V) 50 I/O 5294 tb l 22 Z0 = 50 , 5294 drw 04 Figure 1. AC Test Load Inp ut Pulse Le ve ls Inp ut Rise /Fall Time s 0 to 2.5V 2ns Inp ut Timing Re fe re nce Le ve ls (VDDQ/2) 6 Outp ut Timing Re fe re nce Le ve ls (VDDQ/2) 5 AC Te st Lo ad 4 Se e Fig ure 1 5294 tb l 23 t CD 3 (Ty pi cal , 2 ns) 1 20 30 50 80 100 Capaci t ance (pF ) 200 5294 dr w05 Figure 2. Lumped Capacitive Load, Typical Derating 6.42 13 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V5%, Commercial and Industrial Temperature Ranges) 150MHz Symbol Parameter 133MHz 100MHz Min. Max. Min. Max. Min. Max. Unit tCYC Clo ck Cycle Time 6.7 ____ 7.5 ____ 10 ____ ns tF(1) Clo ck Fre q ue nce ____ 150 ____ 133 ____ 100 MHz tCH(2) Clo ck Hig h Pulse Wid th 2.0 ____ 2.2 ____ 3.2 ____ ns tCL(2) Clo ck Lo w Pulse Wid th 2.0 ____ 2.2 ____ 3.2 ____ ns Output Parameters tCD Clo ck Hig h to Valid Data ____ 3.8 ____ 4.2 ____ 5 ns tCDC Clo ck Hig h to Data Chang e 1.5 ____ 1.5 ____ 1.5 ____ ns tCLZ(3,4,5) Clo ck Hig h to Outp ut Active 1.5 ____ 1.5 ____ 1.5 ____ ns tCHZ(3,4,5) Clo ck Hig h to Data Hig h-Z 1.5 3 1.5 3 1.5 3.3 ns tOE Outp ut Enab le Acce ss Time ____ 3.8 ____ 4.2 ____ 5 ns tOLZ(3,4) Outp ut Enab le Lo w to Data Active 0 ____ 0 ____ 0 ____ ns tOHZ(3,4) Outp ut Enab le Hig h to Data Hig h-Z ____ 3.8 ____ 4.2 ____ 5 ns Set Up Times tSE Clo ck Enab le Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tSA Ad d re ss Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tSD Data In Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tSW Re ad /Write (R/W) Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tSADV Ad vance /Lo ad (ADV/LD) Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns 1.7 ____ 2.0 ____ ns tSC Chip Enab le /Se le ct Se tup Time 1.5 ____ tSB Byte Write Enab le (BWx) Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns tHE Clo ck Enab le Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHA Ad d re ss Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns 0.5 ____ ns Hold Times tHD Data In Ho ld Time 0.5 ____ tHW Re ad /Write (R/W) Ho ld Time 0.5 ____ tHADV Ad vance /Lo ad (ADV/LD) Ho ld Time 0.5 ____ 0.5 ____ tHC Chip Enab le /Se le ct Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHB Byte Write Enab le (BWx) Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns 5294 tb l 24 NOTES: 1. tF = 1/tCYC. 2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ. 3. Transition is measured 200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V). 6.42 14 (2) 6.42 15 A1 tSADV tHA tHW tHE tCLZ tHC Pipeline Read tSC A2 tSA tSW tSE tCD Pipeline Read Q(A1) tHADV tCH tCDC tCL Q(A2) O1(A2) , O2(A2) Q(A 2+1) Q(A2+2) (CEN high, eliminates current L-H clock edge) Burst Pipeline Read tCD Q(A2+2) tCDC Q(A2+3) tCHZ Q(A2) 5294 drw 06 (Burst Wraps around to initial state) NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. DATAOUT OE BW1 - BW4 CE1, CE2 ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle(1,2,3,4) (2) 6.42 16 A1 tSADV tHW tHE tHB tHC Pipeline Write tSB tSC tHA A2 tSA tSW tSE tHD Pipeline Write D(A1) tSD tHADV tCH D(A2) tCL D(A2+1) Burst Pipeline Write (CEN high, eliminates current L-H clock edge) tSD D(A2+2) tHD D(A2) 5294 drw 07 D(A2+3) (Burst Wraps around to initial state) NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAIN OE BW1 - BW4 CE1, CE2 ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycles(1,2,3,4,5) 6.42 17 A1 tSADV tHW tHE tCD tHB tHC Read tSB tSC tHA A2 tSA tSW tSE A3 Q(A1) tCHZ Write tHADV tCH tCLZ Read D(A2) tSD tHD A4 tCL Q(A3) tCDC Write A5 D(A4) A6 Read D(A5) A7 Q(A6) A8 5294 drw 08 Q(A7) A9 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Combined Read and Write Cycles (1,2,3) 6.42 18 A1 tSE tSADV tHE tHW tHC tCD tCLZ tHB B(A2) tSB tSC tHA A2 tSA tSW tCH tHADV Q(A1) tCL tCHZ tCDC Q(A1) A3 D(A2) tSD tHD A4 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 5294 drw 09 Q(A3) A5 IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of CEN Operation(1,2,3,4) , (2) 6.42 19 A1 tSADV tHW tHE tSC tCLZ tCD tHC tHA A2 tSA tSW tSE Q(A1) tHADV tCH tCDC tCHZ tHB Q(A2) tSB A3 tCL D(A3) tSD tHD A4 Q(A4) A5 5294 drw 10 , NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2 ADDRESS R/W ADV/LD CEN CLK IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of CS Operation(1,2,3,4) IDT71V2546, 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation(1) OE tOE tOHZ tOLZ DATAOUT Valid 5294 drw 11 NOTE: 1. A read operation is assumed to be in progress. Ordering Information XXXX Device Type X XX XX XX Power Speed Package X X X Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I Commercial (0C to +70C) Industrial (-40C to +85C) G Green PF BG 100-pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 150 133 100 Clock Frequency in Megahertz S Standard Power Blank X First generation or current die step Current generation die step optional 71V2546 128Kx36 Pipelined ZBT SRAM with 2.5V I/O 5294 drw 12 6.42 20 IDT71V2546 128K x 36, 3.3V Synchronous ZBTTM SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 12/31/99 03/04/00 Pg. 1,14,15,22 05/02/00 Pg. 5,6 Pg. 5,6,7 Pg. 6 Pg. 21 Pg. 23 05/26/00 07/26/00 Pg. 5-8 Pg. 8 Pg. 23 10/25/00 05/20/02 09/30/04 02/23/07 05/27/10 04/11/11 Pg. 8 Pg. 1-8,15,22,23,27 Pg. 7 Pg. 27 Pg. 24 Pg. 1-21 Pg. 13 Pg. 20 Created preliminary datasheet from 71V2556 and 71V2558 datasheets. Changed tCDC, tCLZ, and tCHZ minimums from 1.0ns to 1.5ns. Add 150 MHz speed grade offering Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Clarify note on TQFP and BGA pin configurations; corrected typo in pinout Add BGA capacitance table Add 100 pin TQFP Package Diagram Outline Add new package offering, 13 x 15mm 165 fBGA Correct 119 BGA Package Diagram Outline Add ZZ, sleep mode reference note to BG119, PK100 and BQ165 pinouts Update BQ165 pinout Update BG119 Package Diagram Outline dimensions Remove Preliminary status from datasheet Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST Added JTAG "SA" version functionality and updated ZZ pin descriptions and notes Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18). Added X step die generation to data sheet ordering information. Added "Restricted hazardous substance device" to the ordering information. Removed 71V2548 (EOL), fBGA 165 pin, and JTAG information. Added 150MHz data for Industrial information. Added Tape and Reel to Ordering information and updated description of Restricted hazardous substance device to Green. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: sramhelp@idt.com 800-345-7015 or 408-284-4555 IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc. ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. 6.42 21