APRIL 2011
DSC-5294/07
1
©2011 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
Features
◆◆
◆◆
◆128K x 36 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates the
need to control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP) and 119 ball grid array (BGA)
IDT71V2546S/XS
128K x 36
3.3V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546 contains data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546 to be
suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546 has an on-chip burst counter. In the burst mode, the
IDT71V2546 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546 SRAM utilize IDT's latest high-performance CMOS
process and is packaged in a JEDEC standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).
A
0
A-
61
stupnIsserddA tupnIsuonorhcnyS
EC
1
EC,
2
,EC
2
selbanEpihC tupnIsuonorhcnyS
EO elbanEtuptuO tupnIsuonorhcnysA
/R WlangiSetirW/daeR tupnIsuonorhcnyS
NEC elbanEkc
olC tupnIsuonorhcnyS
WB
1
,WB
2
,WB
3
,WB
4
stceleSetirWetyBlaudividnI tupnIsuonorhcnyS
KLCkcolC tupnIA/N
/VDA DL sserddawendaoL/sserddatsrubecnavdA tupnIsu
onorhcnyS
OBL redrOtsruBdevaelretnI/raeniL tupnIcitatS
ZZedoMpeelS tupnIsuonorhcnyS
O/I
0
O/I-
13
O/I,
1P
O/I-
4P
tuptuO/tupnIataD O/IsuonorhcnyS
V
DD
V,
QDD
rewoPO/I,rewoPeroC ylppuScitatS
V
SS
dnuorG ylppuScitatS
10lbt4925
6.42
2
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
lobmySnoitcnuFniPO/IevitcAnoitpircseD
A
0
A-
61
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/VDA DL daoL/ecnavdAIA/N/VDA DL tinehwlortnocdnasserddawenhtiwsretsig
erlanretniehtdaolotdesusitahttupnisuonorhcnysasi /VDAnehW.detcelespihcehthtiwkcolcfoegdegnisirehttawol
delpmassi DL pihcehthtiwwolsi
/VDAnehW.detanimretsissergorpnitsrubyna,detcelesed DL retnuoctsrublanretnieh
tnehthgihdelpmassi /VDAnehwderongierasesserddalanretxeehT.ssergorpnisawtahttsrubynarofdecnavdasi DL delp
massi
.hgih
/R WetirW/daeRIA/N/RWetirWrodaeRasidetaitinielcycdaoltnerrucehtrehtehwseifitneditahttupnisuonor
hcnysasilangis .retalselcyckcolcowtecalpsekatelcyctnerrucehtrofytivitcasubatadehT.yarrayromemehtotssec
ca
NEC elbanEkcolCIWOLnehW.tupnIelbanEkcolCsuonorhcnyS NEC kcolcgnidulcni,stupnisuonorhcnysrehtolla,hgihdelp
massi fotceffeehT.degnahcnuniamerstuptuodnaderongiera NEC ehtfisasistuptuoecivedehtnohgihdelpmas
,noitare
polamronroF.ruccotondidnoitisnartkcolchgihotwol NEC foegdegnisirtawoldelpmasebtsum
.kcolc
WB
1
-WB
4
etyBlaudividnI selbanEetirW IWOL selcycetirwdaolnO.elbaneetirwetybwolevitcanwostisahetybtib-9hcaE.selbaneetirwetybsuonorhcnyS /RnehW( W/VDAdna DL (langisetirwetybetairporppaeht)woldelpmasera WB
1
-WB
4
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yb Wsi
.retalselcycowtecivedehtotninettirweraatadfo)s(etybetairporppaehT.hgihdelpmas WB
1
-WB
4
ebllanac
.drowtib-63eritneehtotetirwgniodsyawlafiwoldeit
EC
1
,EC
2
selbanEpihCIWOL.elbanepihcwolevitcasuonorhcnyS EC
1
dna EC
2
htiwdesueraEC
2
(.6452V17TDIehtelbaneot EC
1
ro EC
2
ECrohgihdelpmas
2
/VDAdna)woldelpmas DL ehT.elcyctcelesedasetaitini,kcolcfoegdegnisirehttawol
TBZ
MT
.detaitinisitcelesedretfaselcyckcolcowtetats-irtlliwsubatadeht,.e.i,tcelesedelcycowtasah
EC
2
elbanEpihCIHGIHEC.elbanepihchgihevitcasuonorhcnyS
2
htiwdesusi EC
1
dna EC
2
EC.pihcehtelbaneot
2
detrevnisah
otlacitnediesiwrehtotubytiralop EC
1
dna EC
2
.
KLCkcolCIA/NroftpecxE.6452V17TDIehtottupnikcolcehtsisihT EO htiwedameraecivedehtrofsecnerefergnimitlla,
.KL
Cfoegdegnisirehtottcepser
O/I
0
O/I-
13
O/I
1P
O/I-
4P
tuptuO/tupnIataDO/IA/N dnaderetsigererahtaptuptuoataddnahtaptupniatadehthtoB.snip)O/I(tuptuo/tupniatadsuonorhcnyS .KLCfoegdegnisirehtybdereggirt
OBL redrOtsruBraeniLIWOLnehW.tupninoitcelesredrotsruB OBL nehW.detce
lessiecneuqestsrubdevaelretnIehthgihsi OBL wolsi
.detcelessiecneuqestsrubraeniLeht OBL .noitarepoecivedgni
rudegnahctontsumtidnatupnicitatsasi
EO elbanEtuptuOIWOL.elbanetuptuosuonorhcnysA EO nehW.6452V17TDIehtmorfataddaerotwolebtsum EO snipO/Iehthgihsi
.etatsecnadepmi-hgihaniera EO lamronnI.selcycetirwdnadaerrofdellortn
ocylevitcaebotdeentonseod
,noitarepo EO .woldeitebnac
ZZedoMpeelSIHGIH stiot6452V17TDIehtnwodrewopdnayllanret
niKLCehtetaglliwHGIHZZ.tupniedompeelssuonorhcnyS lanretninasahnipsihT.edoMpeelSnideetnaraugsinoitneter
ataD.levelnoitpmusnocrewoptsewol .nwodllup
V
DD
ylppuSrewoPA/NA/N.ylppusrewoperocV3.3
V
QDD
ylppuSrewoPA/NA/N.ylppuSO/IV5.2
V
SS
dnuorGA/NA/N.dnuorG
20lbt4925
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
Input Register
5294 drw 01a
Clock
Data I/O [0:31],
I/O P[1:4]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 128Kx36 BIT
MEMORY ARRAY
Recommended DC Operating
Conditions
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
lobmySretemaraP.niM.pyT.xaMtinU
V
DD
egatloVylppuSeroC531.33.3564.3V
V
QDD
egatloVylppuSO/I573.25.2526.2V
V
SS
egatloVylppuS000V
V
HI
stupnI-egatloVhgiHtupnI7.1
____
V
DD
3.0+V
V
HI
egatloVhgiHtupnI-O/I7.1
____
V
QDD
3.0+
)2(
V
V
LI
egatloVwoLtupnI3.0-
)1(
____
7.0V
30lbt4925
6.42
4
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Pin Configuration — 128K x 36
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
Top View
100 TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5294 drw 02
V
DD(1)
I/O
15
I/O
P3
V
DD(1)
I/O
P4
A
15
A
16
I/O
P1
V
DD(1)
I/O
P2
V
SS/ZZ(3)
,
NC
NC
NC
edarGerutarepmeT
)1(
V
SS
V
DD
V
QDD
laicremmoCC°07+otC°0V0%5±V3.3%5±V5.2
lairtsudnIC°58+otC°04-V0%5±V3.3%5±V5.2
50lbt4925
NOTE:
1. TA is the "instant on" case temperature.
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Absolute Maximum Ratings(1)
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
lobmySgnitaR &laicremmoC seulaVlairtsudnI tinU
V
MRET
)2(
htiwegatloVlanimreT DNGottcepseR 6.4+ot5.0-V
V
MRET
)6,3(
htiwegatloVlanimreT DNGottcepseR Vot5.0-
DD
V
V
MRET
)6,4(
htiwegatloVlanimreT DNGottcepseR Vot5.0-
DD
5.0+V
V
MRET
)6,5(
htiwegatloVlanimreT DNGottcepseR Vot5.0-
QDD
5.0+V
T
A
)7(
laicremmoC erutarepmeTgnitarepO 07+ot0-
o
C
lairtsudnI erutarepmeTgnitarepO 58+ot04-
o
C
T
SAIB
erutarepmeT saiBrednU 521+ot55-
o
C
T
GTS
egarotS erutarepmeT 521+ot55-
o
C
P
T
noitapissiDrewoP0.2W
I
TUO
tnerruCtuptuOCD05Am
60lbt4925
lobmySretemaraP
)1(
snoitidnoC.xaMtinU
C
NI
ecnaticapaCtupnIV
NI
Vd3=5Fp
C
O/I
ecnaticapaCO/IV
TUO
Vd3=7Fp
70lbt4925
100 TQFP Capacitance(1)
(TA = +25° C, f = 1.0MHz)
lobmySretemaraP
)1(
snoitidnoC.xaMtinU
C
NI
ecnaticapaCtupnIV
NI
Vd3=7Fp
C
O/I
ecnaticapaCO/IV
TUO
Vd3=7Fp
a70lbt4925
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
6
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
1234567
AV
DDQ
A
6
A
4
A
8
A
16
V
DDQ
BNC CE
2
A
3
ADV/LD A
9
CE
2
NC
CA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
R/WV
SS
I/O
9
I/O
8
JV
DDQ
V
DD
V
DD
V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
CEN V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
RNC A
5
LBO V
DD
A
13
TNC NC A
10
A
11
A
14
NC NC/ZZ
(3)
UV
DDQ
NC V
DDQ
5294 drw 13a
V
DD(1)
NC
NC(2)
CE
1
NC(2)
V
DD(1)
V
DD(1)
,
NC
NC NC NC NC
Pin Configuration — 128K x 36, 119 BGA
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
7
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
NEC /R WpihC
)5(
elbanE /VDA DL WB xSSERDDA DESU ELCYCSUOIVERPELCYCTNERRUCO/I
)6(
)retalselcyc2(
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)7(
LH tceleSLX lanretxEX DAERDAOLQ
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LX X H dilaVlanretnI/ETIRWDAOL ETIRWTSRUB ETIRWTSRUB )retnuoctsrubecnavdA(
)2(
D
)7(
LX X H X lanretnI/DAERDAOL DAERTSRUB DAERTSRUB )retnuoctsrubecnavdA(
)2(
Q
)7(
LX tceleseDLXX X POTSroTCELESED
)3(
ZiH
LX X H X X POON/TCELESEDPOONZiH
HX X X X X X DNEPSUS
)4(
eulaVsuoiverP
80lbt4925
NOITAREPO/RWWB
1
WB
2
WB
3
WB
4
DAER HXXXX
SETYBLLAETIRW LLLLL
O/I,]7:0[O/I(1ETYBETIRW
1P
)
)2(
LLHHH
O/I,]51:8[O/I(2ETYBETIRW
2P
)
)2(
LHLHH
O/I,]32:61[O/I(3ETYBETIRW
3P
)
)2(
LHHLH
O/I,]13:42[O/I(4ETYBETIRW
4P
)
)2(
LHHHL
ETIRWON LHHHH
90lbt4925
6.42
8
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Functional Timing Diagram(1)
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
n+29
A29
C29
D/Q27
ADDRESS(2)
(A0 - A16)
CONTROL(2)
(R/W, ADV/LD, BWx)
DATA(2)
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
5294 drw 03
,
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS01101100
sserddAdrihT 10110001
sserddAhtruoF
)1(
11000110
11lbt4925
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS 01001110
sserddAdrihT 10110001
sserddAhtruoF
)1(
11100100
01lbt4925
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
9
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation(1)
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
elcyCsserddA/RW/VDA DL EC
)1(
NECWBxEO O/IstnemmoC
nA
0
H L LLXXX daerdaoL
1+n X X H XLXXX daertsruB
2+nA
1
HL LLXLQ
0
daerdaoL
3+nXXLHLXLQ
1+0
POTSrotceleseD
4+n X X H XLXLQ
1
POON
5+nA
2
HL LLXXZ daerdaoL
6+nXXHXLXXZ daertsruB
7+nXXLHLXLQ
2
POTSrotceleseD
8+nA
3
L L LLLLQ
1+2
etirwdaoL
9+nXXHXLLXZ etirwtsruB
01+nA
4
L L LLLXD
3
etirwdaoL
11+nXXLHLXXD
1+3
POTSrotceleseD
21+nXXHXLXXD
4
POON
31+nA
5
L L LLLXZ etirwdaoL
41+nA
6
HL LLXXZ daerdaoL
51+nA
7
L L LLLXD
5
etirwdaoL
61+n X X H XLLLQ
6
etirwtsruB
71+nA
8
HL LLXXD
7
daerdaoL
81+nXXHXLXXD
1+7
daertsruB
91+nA
9
L L LLLLQ
8
etirwdaoL
21lbt4925
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/IstnemmoC
nA
0
H L LLXXX putesteemlortnoCdnasserddA
1+n X X X XLXXX dilaVputeSkcolC
2+n X X X XXXLQ
0
AsserddAfostnetnoC
0
tuOdaeR
31lbt4925
6.42
10
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Write Operation(1)
Burst Read Operation(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/IstnemmoC
nA
0
H L LLXXX putesteemlortnoCdnasserddA
1+n X X H XLXXX retnuoCecnavdA,dilaVputeSkcolC
2+n X X H XLXLQ
0
AsserddA
0
tnuoC.cnI,tuOdaeR
3+n X X H XLXLQ
1+0
AsserddA
1+0
tnuoC.cnI,tuOdaeR
4+n X X H XLXLQ
2+0
AsserddA
2+0
tnuoC.cnI,tuOdaeR
5+nA
1
HL LLXLQ
3+0
AsserddA
3+0
AdaoL,tuOdaeR
1
6+n X X H XLXLQ
0
AsserddA
0
tnuoC.cnI,tuOdaeR
7+n X X H XLXLQ
1
AsserddA
1
tnuoC.cnI,tuOdaeR
8+nA
2
HL LLXLQ
1+1
AsserddA
1+1
AdaoL,tuOdaeR
2
41lbt4925
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/IstnemmoC
nA
0
L L LLLXX putesteemlortnoCdnasserddA
1+n X X X XLXXX dilaVputeSkcolC
2+nXXXXLXXD
0
AsserddAotetirW
0
51lbt4925
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/IstnemmoC
nA
0
L L LLLXX putesteemlortnoCdnasserddA
1+nXXHXLLXX tnuoC.cnI,dilaVputeSkcolC
2+nXXHXLLXD
0
sserddAA
0
tnuoC.cnI,etirW
3+nXXHXLLXD
1+0
AsserddA
1+0
tnuoC.cnI,etirW
4+nXXHXLLXD
2+0
AsserddA
2+0
tnuoC.cnI,etirW
5+n1A L L LLLXD
3+0
AsserddA
3+0
daoL,etirWA
1
6+nXXHXLLXD
0
AsserddA
0
tnuoC.cnI,etirW
7+nXXHXLLXD
1
AsserddA
1
tnuoC.cnI,etirW
8+nA
2
L L LLLXD
1+1
AsserddA
1+1
AdaoL,etirW
2
61lbt4925
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
11
Read Operation with Clock Enable Used(1)
Write Operation with Clock Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/IstnemmoC
nA
0
H L LLXXX putesteemlortnoCdnasserddA
1+n X X X XHXXX derongI1+nkcolC
2+nA
1
H L LLXXX dilaVkcolC
3+nXXXXHXLQ
0
QataD.derongIkcolC
0
.subehtnosi
4+nXXXXHXLQ
0
QataD.derongIkcolC
0
.subehtnosi
5+nA
2
HL LLXLQ
0
AsserddA
0
).snartsub(tuodaeR
6+nA
3
HL LLXLQ
1
AsserddA
1
).snartsub(tuodaeR
7+nA
4
HL LLXLQ
2
AsserddA
2
).snartsub(tuodaeR
71lbt4925
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/IstnemmoC
nA
0
L L LLLXX .putesteemlortnoCdnasserddA
1+n X X X XHXXX .derongI1+nkcolC
2+nA
1
L L LLLXX .dilaVkcolC
3+n X X X XHXXX .derongIkcolC
4+n X X X XHXXX .derongIkcolC
5+nA
2
L L LLLXD
0
DataDetirW
0
6+nA
3
L L LLLXD
1
DataDetirW
1
7+nA
4
L L LLLXD
2
DataDetirW
2
81lbt4925
6.42
12
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used(1)
Write Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/I
)3(
stnemmoC
nXXLHLXX? .detceleseD
1+nXXLHLXX? .detceleseD
2+nA
0
HL LLXXZ putesteemlortnoCdnasserddA
3+nXXLHLXXZ .POTSrodetceleseD
4+nA
1
HL LLXLQ
0
AsserddA
0
AdaoL.tuodaeR
1
.
5+nXXLHLXXZ .POTSrodetceleseD
6+nXXLHLXLQ
1
AsserddA
1
.detceleseD.tuodaeR
7+nA
2
HL LLXXZ .putesteemlortnocdnasserddA
8+nXXLHLXXZ .POTSrodetceleseD
9+nXXLHLXLQ
2
AsserddA
2
.detceleseD.tuodaeR
91lbt4925
elcyCsserddA/RW/VDA DL EC
)2(
NECWBxEO O/I
)3(
stnemmoC
nXXLHLXX? .detceleseD
1+nXXLHLXX? .detceleseD
2+nA
0
L L LLLXZ putesteemlortnoCdnasserddA
3+nXXLHLXXZ .POTSrodetceleseD
4+nA
1
L L LLLXD
0
DsserddA
0
AdaoL.nietirW
1
.
5+nXXLHLXXZ .POTSrodetceleseD
6+nXXLHLXXD
1
DsserddA
1
.detceleseD.nietirW
7+nA
2
L L LLLXZ .putesteemlortnocdnasserddA
8+nXXLHLXXZ .POTSrodetceleseD
9+nXXLHLXXD
2
DsserddA
2
.detceleseD.nietirW
02lbt4925
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
(VDDQ = 2.5V)
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(1) (VDD = 3.3V±5%)
Figure 1. AC Test Load
AC Test Loads
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
= 50Ω
5294 drw 04
,
lobmySretemaraPsnoitidnoCtseT.niM.xaMtinU
I|
LI
|tnerruCegakaeLtupnIV
DD
V,.xaM=
NI
VotV0=
DD
___
5Aµ
I|
IL
|ZZdnaGATJ,OBLtnerruCegakaeLtupnI
)1(
V
DD
V,.xaM=
NI
VotV0=
DD
___
03Aµ
I|
OL
|tnerruCegakaeLtuptuOV
TUO
VotV0=
QDD
detceleseDeciveD,
___
5Aµ
V
LO
egatloVwoLtuptuOI
LO
V,Am6+=
DD
.niM=
___
4.0V
V
HO
egatloVhgiHtuptuOI
HO
V,Am6-=
DD
.niM=0.2
___
V
1
2lbt4925
sleveLesluPtupnI
semiTllaF/esiRtupnI
sleveLecnerefeRgnimiTtupnI
sleveLecnerefeRgnimiTtuptuO
daoLtseTCA
V5.
2ot0
sn2
V(
QDD
)2/
V(
QDD
)2/
1erugiFeeS
32lbt4925
1
2
3
4
20 30 50 100 200
ΔtCD
(Ty pical ,
ns )
Capaci t ance (pF )
80
5
6
5294 dr w05
lobmySretemaraPsnoitidnoCtseT
zHM051zHM331zHM001 tinU
l'moCl'dnIl'moCl'dnIl'moCl'dnI
I
DD
rewoPgnitarepO tnerruCylppuS ,nepOstuptuO,detceleSeciveD /VDA DL V,X=
DD
,.xaM=
V
NI
> V
HI
ro<V
LI
f=f,
XAM
)2(
523533003013052062Am
I
1BS
rewoPybdnatSSOMC tnerruCylppuS ,nepOstuptuO,detceleseDeciveD
V
DD
V,.xaM=
NI
> V
DH
ro<V
DL
,
0=f
)3,2(
045404540454Am
I
2BS
rewoPgninnuRkcolC tnerruCylppuS ,nepOstuptuO,detceleseDeciveD
V
DD
V,.xaM=
NI
> V
DH
V<ro
DL
,
f=f
XAM
)3.2(
021031011021001011Am
I
3BS
rewoPeldI tnerruCylppuS ,nepOstuptuO,detceleSeciveD NEC >V
HI
V,
DD
,.xaM=
V
NI
> V
DH
ro<V
DL
f=f,
XAM
)3,2(
045404540454Am
22lbt4925
6.42
14
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
zHM051zHM331zHM001
lobmySretemaraP.niM.xaM.niM.xaM.niM.xaMtinU
t
CYC
emiTelcyCkcolC7.6
____
5.7
____
01
____
sn
t
F
)1(
ecneuqerFkcolC
____
051
____
331
____
001zHM
t
HC
)2(
htdiWesluPhgiHkcolC0.2
____
2.2
____
2.3
____
sn
t
LC
)2(
htdiWesluPwoLkcolC0.2
____
2.2
____
2.3
____
sn
sretemaraPtuptuO
t
DC
ataDdilaVothgiHkcolC
____
8.3
____
2.4
____
5sn
t
CDC
egnahCataDothgiHkcolC5.1
____
5.1
____
5.1
____
sn
t
ZLC
)5,4,3(
evitcAtuptuOothgiHkcolC5.1
____
5.1
____
5.1
____
sn
t
ZHC
)5,4,3(
Z-hgiHataDothgiHkcolC5.135.13 5.13.3sn
t
EO
emiTsseccAelbanEtuptuO
____
8.3
____
2.4
____
5sn
t
ZLO
)4,3(
evitcAataDotwoLelbanEtuptuO0
____
0
____
0
____
sn
t
ZHO
)4,3(
Z-hgiHataDothgiHelbanEtuptuO
____
8.3
____
2.4
____
5sn
semiTpUteS
t
ES
emiTputeSelbanEkcolC5.1
____
7.1
____
0.2
____
sn
t
AS
emiTputeSsserddA5.1
____
7.1
____
0.2
____
sn
t
DS
emiTputeSnIataD5.1
____
7.1
____
0.2
____
sn
t
WS
/R(etirW/daeR WemiTputeS)5.1
____
7.1
____
0.2
____
sn
t
VDAS
/VDA(daoL/ecnavdA DL emiTputeS)5.1
____
7.1
____
0.2
____
sn
t
CS
emiTputeStceleS/elbanEpihC5.1
____
7.1
____
0.2
____
sn
t
BS
(elbanEetirWetyB WB emiTputeS)x5.1
____
7.1
____
0.2
____
sn
semiTdloH
t
EH
emiTdloHelbanEkcolC5.0
____
5.0
____
5.0
____
sn
t
AH
emiTdloHsserddA5.0
____
5.0
____
5.0
____
sn
t
DH
emiTdloHnIataD5.0
____
5.0
____
5.0
____
sn
t
WH
/R(etirW/daeR WemiTdloH)5.0
____
5.0
____
5.0
____
sn
t
VDAH
/VDA(daoL/ecnavdA DL emiTdloH)5.0
____
5.0
____
5.0
____
sn
t
CH
emiTdloHtceleS/elbanEpihC5.0
____
5.0
____
5.0
____
sn
t
BH
(elbanEetirWetyB WB emiTdloH)x5.0
____
5.0
____
5.0
____
sn
42lbt4925
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
ADV/LD
(CEN high, eliminates
current L-H clock edge)
O2(A2)
t
CD
t
HADV
Pipeline
Read
(Burst Wraps around
to initial state)
t
CDC
t
CLZ
t
CHZ
t
CD
t
CDC
R/W
CLK
CEN
ADDRESS
OE
DATA
OUT
t
HE
t
SE
A1 A2
O1(A2)
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Read
Pipeline
Read
BW
1
- BW
4
5294 drw 06
CE
1,
CE
2(2)
Q(A
2+3
)Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)Q(A
2+1
)
Q(A
2
)
Q(A
1
)
,
6.42
16
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of Write Cycles(1,2,3,4,5)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
OE
DATA
IN
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Write
Pipeline
Write
Pipeline
Write
t
HB
t
SB
(Burst Wraps around
to initial state)
t
HD
t
SD
(CEN high, eliminates
current L-H clock edge)
(2)
D(
A2+2
)D(
A2+3
)
D(A
1
)D(A
2
)D(A
2
)
5294 drw 07
BW1 - BW4
CE1, CE2
D(A
2+1
)
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
17
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
, CE
2(2)
BW
1
- BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)Q(A
6
)Q(A
7
)
t
CD
Read
t
CHZ
5294 drw 08
Write
t
CLZ
D(A
2
)D(A
4
)
t
CDC
D(A
5
)
Write
t
CH
t
CL
t
CYC
t
HW
t
SW
t
HA
t
SA
A
4
A
3
t
HC
t
SC
t
SD
t
HD
t
HADV
t
SADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
t
HB
t
SB
OE
Read
Read
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles (1,2,3)
6.42
18
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of CEN Operation(1,2,3,4)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
BW1 - BW4
OE
DATA
OUT
Q(A
3
)
t
CD
t
CLZ
t
CHZ
t
CH
t
CL
t
CYC
t
HC
t
SC
D(A
2
)
t
SD
t
HD
t
CDC
A
4
A
5
t
HADV
tSADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
Q(A
1
)
5294 drw 09
Q(A
1
)
B(A
2
)
CE
1
, CE
2(2)
,
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
19
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATA
OUT
Q(A
1
)
t
CD
t
CLZ
t
CHZ
t
CDC
t
CH
t
CL
t
HC
t
SC
t
SD
t
HD
A
5
A
3
t
SB
DATA
IN
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
CEN
t
HADV
t
SADV
5294 drw 10
Q(A
2
)Q(A
4
)
D(A
3
)
BW1 - BW4
CE1, CE2
(2)
,
6.42
20
IDT71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA
OUT
t
OHZ
t
OLZ
t
OE
Valid
5294 drw 11
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
Power
XX
Speed
XX
Package
PF
BG
XXXX
150
133
100 Clock Frequency in Megahertz
5294 drw 12
Device
Type
71V2546 128Kx36 Pipelined ZBT SRAM with 2.5V I/O
X
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
XX
S Standard Power
X
Blank
X
First generation or current die step
Current generation die step optional
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
GGreen
X
X
6.42
IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
21
IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created preliminary datasheet from 71V2556 and 71V2558 datasheets. Changed tCDC, tCLZ,
and tCHZ minimums from 1.0ns to 1.5ns.
03/04/00 Pg. 1,14,15,22 Add 150 MHz speed grade offering
05/02/00 Pg. 5,6 Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings tables
Pg. 5,6,7 Clarify note on TQFP and BGA pin configurations; corrected typo in pinout
Pg. 6 Add BGA capacitance table
Pg. 21 Add 100 pin TQFP Package Diagram Outline
05/26/00 Pg. 23 Add new package offering, 13 x 15mm 165 fBGA
Correct 119 BGA Package Diagram Outline
07/26/00 Pg. 5-8 Add ZZ, sleep mode reference note to BG119, PK100 and BQ165 pinouts
Pg. 8 Update BQ165 pinout
Pg. 23 Update BG119 Package Diagram Outline dimensions
10/25/00 Remove Preliminary status from datasheet
Pg. 8 Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST
05/20/02 Pg. 1-8,15,22,23,27 Added JTAG "SA" version functionality and updated ZZ pin descriptions and notes
09/30/04 Pg. 7 Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
02/23/07 Pg. 27 Added X step die generation to data sheet ordering information.
05/27/10 Pg. 24 Added "Restricted hazardous substance device" to the ordering information.
04/11/11 Pg. 1-21 Removed 71V2548 (EOL), fBGA 165 pin, and JTAG information.
Pg. 13 Added 150MHz data for Industrial information.
Pg. 20 Added Tape and Reel to Ordering information and updated description of Restricted hazardous
substance device to Green.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 800-345-7015 or
www.idt.com 408-284-4555
