SCALE™-2 2SC0108T2A0-17
Prelim i nary Dat a Shee t
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changes to (–20°C - 70°C) and the absolute maximum output power rating changes to 1.2W .
The delay time is measured between 50% of the input signal and 10% voltage swing of the
corresp onding output. The delay time is independent of the output loading.
Output rise and fall times are measured between 10% and 90% of the nominal output swing. The
values are given for the driver side of the gate resistors without load. The time constant of the
output load in conjunction wit h the pr esent gate resistors leads to a n a d d itional delay at the load side
of the gate resistors.
The minimum response time given is valid for the circuit given in the description and application
manual (Fig. 6) with the values of table 1 ( Cax=0pF, Rthx=43kΩ).
The blocking time sets a minimum time span between the end of any fault state and the start of
normal operation (remove fault from pin SOx). The value of the blocking time can be adjusted at pin
TB. The specified blocking time is valid if TB is connected to GND.
This specification guarante e s that the dr ive information will be tr ansferred re liably even at a high DC-
link voltage and with ultra-fast sw itching operations.
Undervoltage monitoring of the primary-side supply voltage (VCC to GND). If the voltage drops
below this limit, a fault is transmitted to both SOx outputs and the IGBTs are switched off.
Undervo ltage monitoring of the se condary-side supply voltage (VISOx to VEx and VEx to COMx which
correspond with the approximate turn-on and turn-off gate-
emitter voltages). If the corresponding
voltage drops below this limit, the IGBT is switched off and a fault is transmitted to the
corresp onding SOx output.
Transmission delay of fault state from the secondary side to the corresponding primary status
output.
HiPot testing (= dielectric testing) must generally be restricted to suitable components. This gate
driver is suited for HiP ot te st ing. Nevert heles s, it is str ongly re comme nded t o limit the testing time to
1s slots as stipulated by EN 50178. Excessive HiPot testing a t voltages much higher than 1200VAC(eff)
may lead to insulation degradation. No degradation has been observed over 1min. testing at
5000VAC(eff). Every production sample s
hipped to customers has undergone 100% testing at the
given value for 1s.
The resulting gate resistance is the sum of the external and the internal gate resistance.
17 )
18 )
Partial discharge m easurement is performe d in accorda nce with IEC 60270 and iso lation coordination
specified in EN 50178. The p artial discharge extinction volta g e between primary and either secondary
side is coordinated for safe isolat ion to EN 50178.
Jitter measurements are performed with input signals INx switching between 0V an
GND, with a corresponding rise time and fall time of 15ns.
A version with extended operating temperature range of –40°C…85°C (2SC0108T2B0-
be supplied.
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