CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 Not Recommended for New Designs PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER FEATURES 1 * * * * * * * * * LQFP PACKAGE Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs VCC range 2.5 V 5% Typical Signaling Rate Capability of Up to 1.1 GHz Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs Full Rail-to-Rail Common-Mode Input Range Receiver Input Threshold 100 mV Available in 32-Pin LQFP Package Fail-Safe I/O-Pins for VDD = 0 V (Power Down) DESCRIPTION The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50- transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled. The CDCLVD110 is characterized for operation from -40C to 85C. Not Recommended for New Designs. Use CDCLVD110A as a Replacement. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2008, Texas Instruments Incorporated CDCLVD110 SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 www.ti.com FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION CK 1 I Control register input clock, features a 120-k pullup resistor SI 2 I Control register serial input/CLK Select, features a 120-k pulldown resistor CLK0 3 I True differential input, LVDS CLK0 4 I Complementary differential input, LVDS VBB 5 O Reference voltage output CLK1 6 I True differential input, LVDS CLK1 7 I Complementary differential input, LVDS EN 8 I Control enable (for programmability), features a 120-k pulldown resistor, input VSS 9, 25 Device ground 16, 32 Supply voltage VDD Q [9:0] 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 O Clock outputs, these outputs provide low-skew copies of CLKIN Q[9:0] 10, 12, 14, 17, 19, 21,23, 26, 28, 30 O Complementary clock outputs, these outputs provide low-skew copies of CLKIN ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT -0.3 to 2.8 V Input voltage -0.2 to (VDD + 0.2) V VI Output voltage -0.2 to (VDD + 0.2) V VDD Supply voltage VI VO Qn, Qn, IOSD Driver short circuit current Continuous Electrostatic discharge (HBM 1.5 k, 100 pF), ESD (1) >2000 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VDD Supply voltage VIC Receiver common-mode input voltage TA Operating free-air temperature MIN NOM MAX UNIT 2.375 2.5 2.625 V 0.5|VID| VDD - 0.5|VID| V -40 85 C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 100 250 450 600 mV 50 mV -40C to 85C 0.95 1.2 1.45 V 350 mV DRIVER |VOD| Differential output voltage VOD VOD magnitude change VOS Offset voltage VOS VOS magnitude change IOS Output short circuit current VBB Reference output voltage VDD = 2.5 V, IBB = -100 A CO Output capacitance VO = VDD or GND VO = 0 V -20 |VOD| = 0 V 20 1.15 1.25 1.35 3 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 mA V pF 3 CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECEIVER VIDH Input threshold high VIDL Input threshold low |VID| Input differential voltage IIH Input current, CLK0/CLK0, CLK1/CLK1 IIL CI Input capacitance 100 mV -100 mV 200 mV VI = VDD -5 VI = 0 V A 5 VI = VDD or GND 3 pF SUPPLY CURRENT IDD Supply current IDDZ Full loaded All outputs enabled and loaded, RL = 100 , f = 0 Hz No load Outputs enabled, no output load, f = 0 Hz 35 3-State All outputs 3-state by control logic, f = 0 Hz 35 130 mA JITTER CHARACTERISTICS characterized with CDCLVD110 performance EVM, VDD = 3.3 V, OUTPUTS NOT UNDER TEST are terminated to 50 PARAMETER tjitterLVDS Additive phase jitter from input to LVDS output Q3 and Q3 TEST CONDITIONS MIN TYP 12 kHz to 5 MHz, fout = 30.72 MHz 650 12 kHz to 20 MHz, fout = 125 MHz 299 MAX UNIT fs rms LVDS -- SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 2.5 V 5% FROM (INPUT) TO (OUTPUT) CLK0, CLK0 CLK1, CLK1 PARAMETER tPLH tPHL Propagation delay low-to-high Propagation delay high-to-low MIN TYP MAX Qn, Qn 2 3 ns CLK0, CLK0 CLK1, CLK1 Qn, Qn 2 3 ns CLK0, CLK0 CLK1, CLK1 Qn, Qn tduty Duty cycle tsk(o) Output skew Any Qn, Qn tsk(p) Pulse skew Any Qn, Qn 50 ps Any Qn, Qn 600 ps Any Qn, Qn 350 ps Any Qn, Qn 350 ps tsk(pp) Part-to-part skew tr Output rise time, 20% to 80%, RL = 100 , CL = 5 pF tf Output fall time, 20% to 80%, RL = 100 , CL = 5 pF fclk CLK0, CLK0 CLK1, CLK1 Max input frequency Any Qn, Qn 45% UNIT 55% 30 900 ps 1100 MHz CONTROL REGISTER CHARACTERISTICS over recommended operating free-air temperature range, VDD = 2.5 V 5% (unless otherwise noted) PARAMETER TEST CONDITIONS fMAX Maximum frequency of shift register tsu Setup time, clock to SI th tremoval tw Clock pulse width, minimum VIH Logic input high VDD = 2.5 V VIL Logic input low VDD = 2.5 V 4 MIN TYP 100 150 MAX UNIT MHz 2 ns Hold time, clock to SI 1.5 ns Removal time, enable to clock 1.5 ns Submit Documentation Feedback 3 ns 2 V 0.8 V Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 CONTROL REGISTER CHARACTERISTICS (continued) over recommended operating free-air temperature range, VDD = 2.5 V 5% (unless otherwise noted) PARAMETER TEST CONDITIONS Input current, CK pin IIH Input current, CK pin VI = GND Input current, SI and EN pins TYP MAX -5 5 10 -30 -10 30 -5 5 VI = VDD Input current, SI and EN pins IIL MIN UNIT A A SPECIFICATION OF CONTROL REGISTER The CDCLVD110 is provided with an 11-bit, serial-in shift register and an 11-bit control register. The control Register enables/disables each output clock and selects either CLK0 or CLK1 as the input clock. The CDCLVD110 has two modes of operation: Programmable Mode (EN=1) The shift register utilizes a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11 clock pulses, the twelfth clock pulse loads the control register. The first bit (bit 0) on SI enables the Q9, Q9 output pair, and the tenth bit (bit 9) enables the Q0, Q0 pair. The eleventh bit (bit 10) on SI selects either CLK0 or CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. To restart the control register configuration, a reset of the state machine must be done with a clock pulse on CK (shift register clock input) and EN set to low. The control register can be configured only once after each reset. Standard Mode (EN=0) In this mode, the CDCLVD110 is not programmable and all the clock outputs are enabled. The clock input (CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register. STATE-MACHINE INPUTS EN SI CK OUTPUT L L X All outputs enabled, CLK0 selected, control register disabled, default state L H X All outputs enabled, CLK1 selected, control register disabled H L First stage stores L, other stage stores data of previous stage H H First stage stores H, other stage stores data of previous stage L X Reset of state machine, shift and control registers CONTROL REGISTER BIT 10 BITS [0-9] QN[0-9] L H CLK0 H H CLK1 X L Outputs disabled SERIAL INPUT (SI) SEQUENCE BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CLK_SEL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 TRUTH TABLE FOR CONTROL LOGIC CK EN SI CLK0 CLK0 CLK1 CLK1 L L L L L L L H X L H L X L L Open Open L L H X L L H X L L H X All outputs enabled Q(0-9) Q(0-9) X L H X H L X X L H X L H L H X H L H L X Open Open L H X = Don't care Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 5 CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 APPLICATION INFORMATION Fall-Safe Information For VDD = 0 V (power-down mode) the CDCLVD110 has fail-safe input and output pins. In power-on mode, fail-safe biasing at input pins can be accomplished with a 10-k pullup resistor from CLK0/CLK1 to VDD and a 10-k pulldown resistor from CLK0/CLK1 to GND. LVDS Receiver Input Termination The LVDS receiver inputs need to have 100- termination resistors placed as close as possible across the input pins. Control Inputs Termination No external termination is required. The CK control input has an internal 120-k. pullup resistor while SI- and EN-control inputs each have an internal 120-k pulldown resistor. If the control pins are left open per the default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled. 6 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION A. Output skew, tsk(o), is calculated as the greater of: - The difference between the fastest and the slowest tPLHn (n = 1, 2,...10) - The difference between the fastest and the slowest tPHLn (n = 1, 2,...10) B. Part-to-part skew, tsk(pp), is calculated as the greater of: - The difference between the fastest and the slowest tPLHn (n = 1, 2,...10) across multiple devices - The difference between the fastest and the slowest tPHLn (n = 1, 2,...10) across multiple devices C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tPHL) and the low-to-high (tPLH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tPHL - tPLH |. Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew. Figure 1. Waveforms for Calculation of tsk(o) and tsk(pp) Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 7 CDCLVD110 www.ti.com SCAS684C - SEPTEMBER 2002 - REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION (continued) Figure 2. Test Criteria for fclk, Duty Cycle, tr, tf, VOD 8 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCLVD110VF NRND LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110VFG4 NRND LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110VFR NRND LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110VFRG4 NRND LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCLVD110VFR Package Package Pins Type Drawing LQFP VF 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.9 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD110VFR LQFP VF 32 1000 341.0 159.0 123.5 Pack Materials-Page 2 MECHANICAL DATA MTQF002B - JANUARY 1995 - REVISED MAY 2000 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,05 MIN 0,25 0- 7 1,45 1,35 Seating Plane 0,75 0,45 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 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