1
FEATURES
LQFP PACKAGE
DESCRIPTION
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008www.ti.com
Not Recommended for New DesignsPROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
•Low-Output Skew <30 ps (Typical) forClock-Distribution Applications•Distributes One Differential Clock Input to10 LVDS Differential Clock Outputs•V
CC
range 2.5 V ± 5%•Typical Signaling Rate Capability of Up to1.1 GHz•Configurable Register (SI/CK) IndividuallyEnables Disables Outputs, Selectable CLK0,CLK0 or CLK1, CLK1 Inputs•Full Rail-to-Rail Common-Mode Input Range•Receiver Input Threshold ± 100 mV•Available in 32-Pin LQFP Package•Fail-Safe I/O-Pins for V
DD
= 0 V (Power Down)
The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 isspecifically designed for driving 50- Ωtransmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output canbe individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once theshift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, theoutputs are not programmable and all outputs are enabled.
The CDCLVD110 is characterized for operation from – 40 °C to 85 °C.
Not Recommended for New Designs. Use CDCLVD110A as a Replacement.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
CK 1 I Control register input clock, features a 120-k Ωpullup resistorSI 2 I Control register serial input/CLK Select, features a 120-k Ωpulldown resistorCLK0 3 I True differential input, LVDSCLK0 4 I Complementary differential input, LVDSV
BB
5 O Reference voltage outputCLK1 6 I True differential input, LVDSCLK1 7 I Complementary differential input, LVDSEN 8 I Control enable (for programmability), features a 120-k Ωpulldown resistor, inputV
SS
9, 25 Device groundV
DD
16, 32 Supply voltage11, 13, 15, 18, 20, 22,Q [9:0] O Clock outputs, these outputs provide low-skew copies of CLKIN24, 27, 29, 3110, 12, 14, 17, 19,Q[9:0] O Complementary clock outputs, these outputs provide low-skew copies of CLKIN21,23, 26, 28, 30
VALUE UNIT
V
DD
Supply voltage – 0.3 to 2.8 VV
I
Input voltage – 0.2 to (V
DD
+ 0.2) VV
O
VI Output voltage – 0.2 to (V
DD
+ 0.2) VQn, Qn, I
OSD
Driver short circuit current ContinuousElectrostatic discharge (HBM 1.5 k Ω, 100 pF), ESD >2000 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
V
DD
Supply voltage 2.375 2.5 2.625 VV
IC
Receiver common-mode input voltage 0.5|V
ID
| V
DD
– 0.5|V
ID
| VT
A
Operating free-air temperature – 40 85 °C
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
|V
OD
| Differential output voltage R
L
= 100 Ω250 450 600 mV
ΔV
OD
V
OD
magnitude change 50 mVV
OS
Offset voltage – 40 °C to 85 °C 0.95 1.2 1.45 V
ΔV
OS
V
OS
magnitude change 350 mVV
O
= 0 V – 20I
OS
Output short circuit current mA|V
OD
| = 0 V 20V
BB
Reference output voltage V
DD
= 2.5 V, I
BB
= – 100 µA 1.15 1.25 1.35 VC
O
Output capacitance V
O
= V
DD
or GND 3 pF
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :CDCLVD110
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JITTER CHARACTERISTICS
LVDS — SWITCHING CHARACTERISTICS
CONTROL REGISTER CHARACTERISTICS
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RECEIVER
V
IDH
Input threshold high 100 mVV
IDL
Input threshold low – 100 mV|V
ID
| Input differential voltage 200 mVI
IH
V
I
= V
DDInput current, CLK0/ CLK0, CLK1/ CLK1 – 5 5 µAI
IL
V
I
= 0 VC
I
Input capacitance V
I
= V
DD
or GND 3 pF
SUPPLY CURRENT
Full loaded All outputs enabled and loaded, R
L
= 100 Ω, f = 0 Hz 130I
DD
Supply current No load Outputs enabled, no output load, f = 0 Hz 35 mAI
DDZ
3-State All outputs 3-state by control logic, f = 0 Hz 35
characterized with CDCLVD110 performance EVM, V
DD
= 3.3 V, OUTPUTS NOT UNDER TEST are terminated to 50 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
12 kHz to 5 MHz, f
out
= 30.72 MHz 650Additive phase jitter from input tot
jitterLVDS
fs rmsLVDS output Q3 and Q3
12 kHz to 20 MHz, f
out
= 125 MHz 299
over recommended operating free-air temperature range, V
DD
= 2.5 V ± 5%
FROM TOPARAMETER MIN TYP MAX UNIT(INPUT) (OUTPUT)
CLK0, CLK0t
PLH
Propagation delay low-to-high Qn, Qn 2 3 nsCLK1, CLK1Propagation delay high-to-low CLK0, CLK0t
PHL
Qn, Qn 2 3 nsCLK1, CLK1CLK0, CLK0t
duty
Duty cycle Qn, Qn 45% 55%CLK1, CLK1t
sk(o)
Output skew Any Qn, Qn 30 pst
sk(p)
Pulse skew Any Qn, Qn 50 pst
sk(pp)
Part-to-part skew Any Qn, Qn 600 pst
r
Output rise time, 20% to 80%, R
L
= 100 Ω, C
L
= 5 pF Any Qn, Qn 350 pst
f
Output fall time, 20% to 80%, R
L
= 100 Ω, C
L
= 5 pF Any Qn, Qn 350 psCLK0, CLK0f
clk
Max input frequency Any Qn, Qn 900 1100 MHzCLK1, CLK1
over recommended operating free-air temperature range, V
DD
= 2.5 V ± 5% (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
MAX
Maximum frequency of shift register 100 150 MHzt
su
Setup time, clock to SI 2 nst
h
Hold time, clock to SI 1.5 nst
removal
Removal time, enable to clock 1.5 nst
w
Clock pulse width, minimum 3 nsV
IH
Logic input high V
DD
= 2.5 V 2 VV
IL
Logic input low V
DD
= 2.5 V 0.8 V
4Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCLVD110
www.ti.com
SPECIFICATION OF CONTROL REGISTER
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
CONTROL REGISTER CHARACTERISTICS (continued)over recommended operating free-air temperature range, V
DD
= 2.5 V ± 5% (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input current, CK pin – 5 5I
IH
V
I
= V
DD
µAInput current, SI and EN pins 10 – 30Input current, CK pin – 10 30I
IL
V
I
= GND µAInput current, SI and EN pins – 5 5
The CDCLVD110 is provided with an 11-bit, serial-in shift register and an 11-bit control register. The controlRegister enables/disables each output clock and selects either CLK0 or CLK1 as the input clock. TheCDCLVD110 has two modes of operation:Programmable Mode (EN=1)The shift register utilizes a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11clock pulses, the twelfth clock pulse loads the control register. The first bit (bit 0) on SI enables the Q9, Q9output pair, and the tenth bit (bit 9) enables the Q0, Q0 pair. The eleventh bit (bit 10) on SI selects eitherCLK0 or CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. Torestart the control register configuration, a reset of the state machine must be done with a clock pulse on CK(shift register clock input) and EN set to low. The control register can be configured only once after eachreset.
Standard Mode (EN=0)In this mode, the CDCLVD110 is not programmable and all the clock outputs are enabled. The clock input(CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register.STATE-MACHINE INPUTS
EN SI CK OUTPUT
L L X All outputs enabled, CLK0 selected, control register disabled, default stateL H X All outputs enabled, CLK1 selected, control register disabledH L ↑First stage stores L, other stage stores data of previous stageH H First stage stores H, other stage stores data of previous stageL X Reset of state machine, shift and control registers
CONTROL REGISTER
BIT 10 BITS [0-9] Q
N
[0-9]
L H CLK0H H CLK1X L Outputs disabled
SERIAL INPUT (SI) SEQUENCE
BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CLK_SEL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
TRUTH TABLE FOR CONTROL LOGIC
CK EN SI CLK0 CLK0 CLK1 CLK1 Q(0-9) Q(0-9)
L L L L H X X L HL L L H L X X H LL L L Open Open X X L HL L H X X L H L HL L H X X H L H LL L H X X Open Open L HAll outputs enabled X = Don't care
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :CDCLVD110
www.ti.com
APPLICATION INFORMATION
Fall-Safe Information
LVDS Receiver Input Termination
Control Inputs Termination
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
For V
DD
= 0 V (power-down mode) the CDCLVD110 has fail-safe input and output pins. In power-on mode,fail-safe biasing at input pins can be accomplished with a 10-k Ωpullup resistor from CLK0/CLK1 to VDD and a10-k Ωpulldown resistor from CLK0/ CLK1 to GND.
The LVDS receiver inputs need to have 100- Ωtermination resistors placed as close as possible across the inputpins.
No external termination is required. The CK control input has an internal 120-k. pullup resistor while SI- andEN-control inputs each have an internal 120-k Ωpulldown resistor. If the control pins are left open per the default,all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled.
6Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCLVD110
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PARAMETER MEASUREMENT INFORMATION
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
A. Output skew, t
sk(o)
, is calculated as the greater of:– The difference between the fastest and the slowest t
PLHn
(n = 1, 2,...10)– The difference between the fastest and the slowest t
PHLn
(n = 1, 2,...10)B. Part-to-part skew, t
sk(pp)
, is calculated as the greater of:– The difference between the fastest and the slowest t
PLHn
(n = 1, 2,...10) across multiple devices– The difference between the fastest and the slowest t
PHLn
(n = 1, 2,...10) across multiple devicesC. Pulse skew, t
sk(p)
, is calculated as the magnitude of the absolute time difference between the high-to-low (t
PHL
) andthe low-to-high (t
PLH
) propagation delays when a single switching input causes one or more outputs to switch,t
sk(p)
= | t
PHL
– t
PLH
|. Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew.
Figure 1. Waveforms for Calculation of t
sk(o)
and t
sk(pp)
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s) :CDCLVD110
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDCLVD110VF NRND LQFP VF 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCLVD110VFG4 NRND LQFP VF 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCLVD110VFR NRND LQFP VF 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCLVD110VFRG4 NRND LQFP VF 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Aug-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCLVD110VFR LQFP VF 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCLVD110VFR LQFP VF 32 1000 341.0 159.0 123.5
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF002B – JANUARY 1995 – REVISED MAY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VF (S-PQFP-G32) PLASTIC QUAD FLATPACK
4040172/D 04/00
Gage Plane
Seating Plane
1,60 MAX
1,45
1,35
8,80
9,20 SQ
0,05 MIN
0,45
0,75
0,25
0,13 NOM
5,60 TYP
1
32
7,20
6,80
24
25
SQ
8
9
17
16
0,25
0,45
0,10
0°–7°
M
0,20
0,80
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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