DS75108N - National Semiconductor

TL/F/9446

DS55107/DS75107/DS75108/DS75208 Dual Line Receivers

January 1996

DS55107/DS75107/DS75108/DS75208

Dual Line Receivers

General Description

The products described herein are TTL compatible dual

high speed circuits intended for sensing in a broad range of

system applications. While the primary usage will be for line

receivers of MOS sensing, any of the products may effec-

tively be used as voltage comparators, level translators,

window detectors, transducer preamplifiers, and in other

sensing applications. As digital line receivers the products

are applicable with the SN55109/SN75109 and mA75110/

DS75110 companion drivers, or may be used in other bal-

anced or unbalanced party-line data transmission systems.

The improved input sensitivity and delay specifications of

the DS75208 make it ideal for sensing high performance

MOS memories as well as high sensitivity line receivers and

voltage comparators.

Input protection diodes are incorporated in series with the

collectors of the differential input stage. These diodes are

useful in certain applications that have multiple VCCasup-

plies or VCCasupplies that are turned off.

Features

YDiode protected input stage for power ‘‘OFF’’ condition

Y17 ns typ high speed

YTTL compatible

Yg10 mV or g25 mV input sensitivity

Yg3V input common-mode range

YHigh input impedance with normal VCC,orV

CC e0V

YStrobes for channel selection

YDual circuits

YSensitivity gntd. over full common-mode range

YLogic input clamp diodesÐmeets both ‘‘A’’ and ‘‘B’’

version specifications

Yg5V standard supply voltages

Connection Diagram

Dual-In-Line Package

TL/F/9446– 1

Top View

Order Number DS75107M, DS75107N, DS75107AM, DS75107AN,

DS75108M, DS75108N or DS75208N

See NS Package Number M14A or N14A

For Complete Military 883 Specifications, see RETS Datasheet.

Order Number DS55107AJ/883

See NS Package Number J14A

Selection Guide

Temperature

b55§CsTAsa125§C0

70§C

Package

Cavity Dip Cavity or Molded Dip

Input Sensitivity

g25 mV g25 mV g10 mV

Output Logic

TTL Active Pull-Up DS55107 DS75107

TTL Open Collector DS75108 DS75208

C1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A. http://www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage, VCCa7V

Supply Voltage, VCCbb7V

Differential Input Voltage g6V

Common Mode Input Voltage g5V

Strobe Input Voltage 5.5V

Storage Temperature Range b65§Ctoa

150§C

Maximum Power Dissipation*at 25§C

Cavity Package 1308 mW

Molded Package 1207 mW

Lead Temperature (Soldering, 4 sec) 260§C

*Derate cavity package 8.7 mW/§C above 25§C; derate molded package 9.7

mW/§C above 25§C.

Operating Conditions

DS55107 DS75107,

DS75108, DS75208

Min Nom Max Min Nom Max

Supply Voltage VCCa4.5V 5V 5.5V 4.75V 5V 5.25V

Supply Voltage VCCbb4.5V b5V b5.5V b4.75V b5V b5.25V

Operating Temperature Range b55§Ctoa

125§C0

Cto

70§C

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’

they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2. Unless otherwise specified min/max limits apply across the b55§Ctoa

125§C temperature range for the DS55107 and across the 0§Ctoa

70§C range for

the DS75107, DS75108 and DS75208. All typical values are for TAe25§C and VCC e5V.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown

as max or min on absolute value basis.

DS55107/DS75107, DS75108

Electrical Characteristics TMIN sTAsTMAX (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

IIH High Level Input Current VCCaeMax, VCCbeMax, 30 75 mA

into A1, B1, A2 or B2 VID e0.5V, VIC eb

3V to 3V

IIL Low Level Input Current VCCaeMax, VCCbeMax, b10 mA

into A1, B1, A2 or B2 VID eb

2V, VIC eb

3V to 3V

IIH High Level Input Current VCCaeMax, VIH(S) e2.4V 40 mA

into G1 or G2 VCCbeMax VIH(S) Max VCCa1mA

IL Low Level Input Current VCCaeMax, VCCbeMax, b1.6 mA

into G1 or G2 VIL(S) e0.4V

IIH High Level Input Current into S VCCaeMax, VIH(S) e2.4V 80 mA

VCCbeMax VIH(S) eMax VCCa2mA

IL Low Level Input Current into S VCCaeMax, VCCbeMax, b3.2 mA

VIL(S) e0.4V

VOH High Level Output Voltage VCCaeMin, VCCbeMin,

ILOAD eb

400 mA, VID e25 mV, 2.4 V

VIC eb

3V to 3V, (Note 3)

VOL Low Level Output Voltage VCCaeMin, VCCbeMin,

ISINK e16 mA, VID eb

25 mV, 0.4 V

VIC eb

3V to 3V

IOH High Level Output Current VCCaeMin, VCCbeMin 250 mA

VOH eMax VCCa, (Note 4)

IOS Short Circuit Output Current VCCaeMax, VCCbeMax, b18 b70 mA

(Notes 2 and 3)

ICCHaHigh Logic Level Supply VCCaeMax, VCCbeMax, 18 30 mA

Current from VCC VID e25 mV, TAe25§C

ICCHbHigh Logic Level Supply VCCaeMax, VCCbeMax, b8.4 b15 mA

Current from VCC VID e25 mV, TAe25§C

VIInput Clamp Voltage on G or S VCCaeMin, VCCbeMin, b1b1.5 V

IIN eb

12 mA, TAe25§C

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Switching Characteristics VCCae5V, VCCbeb

5V, TAe25§C

Symbol Parameter Conditions Min Typ Max Units

tPLH(D) Propagation Delay Time, Low to RLe390X,C

Le50 pF, (Note 3) 17 25 ns

High Level, from Differential (Note 1) (Note 4) 19 25 ns

Inputs A and B to Output

tPHL(D) Propagation Delay Time, High to RLe390X,C

Le50 pF, (Note 3) 17 25 ns

Low Level, from Differential (Note 1) (Note 4) 19 25 ns

Inputs A and B to Output

tPLH(S) Propagation Delay Time, Low to RLe390X,C

Le50 pF (Note 3) 10 15 ns

High Level, from Strobe Input G (Note 4) 13 20 ns

or S to Output

tPHL(S) Propagation Delay Time, High to RLe390X,C

Le50 pF (Note 3) 8 15 ns

Low Level, from Strobe Input G (Note 4) 13 20 ns

or S to Output

Note 1: Differential input is a100 mV to b100 mV pulse. Delays read from 0 mV on input to 1.5V on output.

Note 2: Only one output at a time should be shorted.

Note 3: DS55107/DS75107 only.

Note 4: DS75108 only.

DS75208

Electrical Characteristics 0§CsTAsa70§C

Symbol Parameter Conditions Min Typ Max Units

IIH High Level Input Current VCCaeMax, VCCbeMax, 30 75 mA

into A1, B1, A2 or B2 VID e0.5V, VIC eb

3V to 3V

IIL Low Level Input Current VCCaeMax, VCCbeMax, b10 mA

into A1, B1, A2 or B2 VID eb

2V, VIC eb

3V to 3V

IIH High Level Input Current VCCaeMax, VIH(S) e2.4V 40 mA

into G1 or G2 VCCbeMax VIH(S) eMax VCCa1mA

IL Low Level Input Current VCCaeMax, VCCbeMax, b1.6 mA

into G1 or G2 VIL(S) e0.4V

IIH High Level Input Current into S VCCaeMax, VIH(S) e2.4V 80 mA

VCCbeMax VIH(S) eMax VCCa2mA

IL Low Level Input Current into S VCCaeMax, VCCbeMax, b3.2 mA

VIL(S) e0.4V

VOL Low Level Output Voltage VCCaeMin, VCCbeMin,

ISINK e16 mA, VID eb

10 mV, 0.4 V

VIC eb

3V to 3V

IOH High Level Output Current VCCaeMin, VCCbeMin, 250 mA

VOH eMax VCCa

ICCHaHigh Logic Level Supply VCCaeMax, VCCbeMax, 18 30 mA

Current from VCCaVID e10 mV, TAe25§C

ICCHbHigh Logic Level Supply VCCaeMax, VCCbeMax, b8.4 b15 mA

Current from VCCbVID e10 mV, TAe25§C

VIInput Clamp Voltage on G or S VCCaeMin, VCCbeMin, b1b1.5 V

IIN eb

12 mA, TAe25§C

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Switching Characteristics VCCae5V, VCCbeb

5V, TAe25§C

Symbol Parameter Conditions Min Typ Max Units

tPLH(D) Propagation Delay Time, Low-to- RLe470X,C

Le15 pF, (Note 1)

High Level, from Differential 35 ns

Inputs A and B to Output

tPHL(D) Propagation Delay Time, High-to- RLe470X,C

Le15 pF, (Note 1)

Low Level, from Differential 20 ns

Inputs A and B to Output

tPLH(S) Propagation Delay Time, Low-to- RLe470X,C

Le15 pF

High Level, from Strobe Input G 17 ns

or S to Output

tPHL(S) Propagation Delay Time, High-to- RLe470X,C

Le15 pF

Low Level, from Strobe Input G 17 ns

or S to Output

Note 1: Differential input is a10 mV to b30 mV pulse. Delays read from 0 mV on input to 1.5V on output.

Voltage Waveforms

TL/F/9446– 12

Typical Applications

Basic Balanced-Line Transmission System

TL/F/9446– 2

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Typical Applications (Continued)

Data-Bus or Party-Line System

TL/F/9446– 3

APPLICATION

The DS55107, DS75107 dual line circuits are designed spe-

cifically for use in high speed data transmission systems

that utilize balanced, terminated transmission lines such as

twisted-pair lines. The system operates in the balanced

mode, so that noise induced on one line is also induced on

the other. The noise appears common mode at the receiver

input terminals where it is rejected. The ground connection

between the line driver and receiver is not part of the signal

circuit so that system performance is not affected by circu-

lating ground currents.

The unique driver output circuit allows terminated transmis-

sion lines to be driven at normal line impedances. High

speed system operation is ensured since line reflections are

virtually eliminated when terminated lines are used. Cross-

talk is minimized by low signal amplitudes and low line im-

pedances.

The typical data delay in a system is approximately (30 a

1.3L) ns, where L is the distance in feet separating the driv-

er and receiver. This delay includes one gate delay in both

the driver and receiver.

Data is impressed on the balanced-line system by unbalanc-

ing the line voltages with the driver output current. The driv-

en line is selected by appropriate driver input logic levels.

The voltage difference is approximately:

VDIFF j(/2 IO(on) cRT(1)

High series line resistance will cause degradation of the sig-

nal. The receivers, however, will detect signals as low as

25 mV (or less). For normal line resistances, data may be

recovered from lines of several thousand feet in length.

Line termination resistors (RT) are required only at the ex-

treme ends of the line. For short lines, termination resistors

at the receiver only may prove adequate. The signal ampli-

tude will then be approximately:

VDIFF jIO(on) cRT(2)

The strobe feature of the receivers and the inhibit feature of

the drivers allow the DS55107, DS75107 dual line circuits to

be used in data-bus or party-line systems. In these applica-

tions, several drivers and receivers may share a common

transmission line. An enabled driver transmits data to all

enabled receivers on the line while other drivers and receiv-

ers are disabled. Data is thus time multiplexed on the trans-

mission line. The DS55107, DS75107 device specifications

allow widely varying thermal and electrical environments at

the various driver and receiver locations. The data-bus sys-

tem offers maximum performance at minimum cost.

The DS55107, DS75107 dual line circuits may also be used

in unbalanced or single line systems. Although these sys-

tems do not offer the same performance as balanced sys-

tems for long lines, they are adequate for very short lines

where environment noise is not severe.

The receiver threshold level is established by applying a DC

reference voltage to one receiver input terminal. The signal

from the transmission line is applied to the remaining input.

The reference voltage should be optimized so that signal

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Typical Applications (Continued)

swing is symmetrical about it for maximum noise margin.

The reference voltage should be in the range of b3.0V to

a3.0V. It can be provided by a voltage supply or by a volt-

age divider from an available supply voltage.

Unbalanced or Single-Line Systems

TL/F/9446– 4

Precautions in the Use of DS1603, DS3603, DS55107,

DS75107, DS75108 and DS75208 Dual Line Receivers

The following precaution should be observed when using or

testing DS55107, DS75107 line circuits.

When only one receiver in a package is being used, at least

one of the differential inputs of the unused receiver should

be terminated at some voltage between b3.0V and a3.0V,

preferably at ground. Failure to do so will cause improper

operation of the unit being used because of common bias

circuitry for the current sources of the two receivers.

The DS55107, DS75107 and DS75108 line receivers fea-

ture a common mode input voltage range of g3.0V. This

satisfies the requirements for all but the noisiest system ap-

plications. For these severe noise environments, the com-

mon mode range can be extended by the use of external

input attenuators. Common mode input voltages can in this

way be reduced to g3.0V at the receiver input terminals.

Differential data signals will be reduced proportionately. In-

put sensitivity, input impedance and delay times will be ad-

versely affected.

The DS75108 line receivers feature an open-collector-out-

put circuit that can be connected in the DOT-OR logic con-

figuration with other DS75108 outputs. This allows a level of

logic to be implemented without addtional logic delay.

Increasing Common Mode Input

Voltage Range of Receiver

TL/F/9446– 5

DS75108 Wired-OR Output Connections

TL/F/9446– 6

Circuit Differences Between ‘‘A’’ and Standard Devices

The difference between the ‘‘A’’ and standard devices is

shown in the following schematics of the input stage.

‘‘A’’ Devices

TL/F/9446– 7

Standard Devices

TL/F/9446– 8

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Typical Applications (Continued)

The input protection diodes are useful in certain party-line

systems which may have multiple Vapower supplies and,

in which case, may be operated with some of the Vasup-

plies turned off. In such a system, if a supply is turned off

and allowed to go to ground, the equivalent input circuit

connected to that supply would be as follows:

‘‘A’’ Devices

TL/F/9446– 9

Standard Devices

TL/F/9446– 10

This would be a problem in specific systems which might

possibly have the transmission lines biased to some poten-

tial greater than 1.4V. Since this is not a widespread appli-

cation problem, both the ‘‘A’’ and standard devices will be

available. The ratings and characteristic specifications of

the ‘‘A’’ devices are the same as those of the standard

devices.

The DS55107A feature the ‘‘A’’ device input stage.

Schematic Diagrams

DS55107/DS75107, DS75108, DS75208

TL/F/9446– 11

Note 1: (/2 of the dual circuit is shown.

Note 2: *Indicates connections common to second half of dual circuit.

Note 3: Components shown with dash lines are applicable to the DS55107, DS75207 and DS75107 only.

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Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number DS55107J, DS75107J or DS75208J

NS Package Number J14A

Molded Dual-In-Line Package (M)

Order Number DS75107M, DS75107AM or DS75108M

NS Package Number M14A

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DS55107/DS75107/DS75108/DS75208 Dual Line Receivers

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number DS75107N, DS75107AN, DS75108N or DS75208N

NS Package Number N14A

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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