This doc ument descr ibes par t-number -spec ific change s to rec ommended op erating condition s
and revised electrical specifications, as applicable, from those described in the general
MPC7455 RISC Microprocessor Hardware Specifications (Order No. MPC7455EC/D). The
devices described in this specification are no longer in production and this document is
provided for ref erence onl y. F or recomme nded upgra des or rep lacement d evices, co ntact you r
Motorola sales office.
Specifications provided in this document supersede those in the MPC7455 RISC
Microprocessor Hardware Specifications, Rev. 1 or later, for the part numbers listed in
Table A only. Specifications not addressed herein are unchanged. Because this document is
frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola
sales office for the latest version.
Note that headings a nd table n umbers in th is document a re not cons ecutivel y number ed. They
are intended to correspond to the heading or table affected in the general hardware
specification.
Part numbers addressed in this document are listed in Table A.
Advance Information
MPC7455RXLCPNS/D
Rev. 0, 1/2003
MPC7455 Part Number
Specificat ion for the
XPC74x5RXnnnLC Series
Motorola Part
Numbers Affect ed:
XPC7455RX600LC
XPC7455RX733LC
XPC7455RX800LC
XPC7455RX867LC
XPC7455RX933LC
PPC7455RX1000LC
XPC7445RX600LC
XPC7445RX733LC
XPC7445RX800LC
XPC7445RX867LC
XPC7445RX933LC
PPC7445RX1000LC
2MPC7455 Part Number Specification for the MOTOROLA
XPC74x5RXnnnLC Series
Table A. Part Numbers Addressed by this Data Sheet
Motorola
Part Number
Operating Conditions
Significant Differences from
Hardware Specification
CPU
Frequency
(MHz) VDD TJ
(°C)
XPC7455RX600LC 600 1.6 V ± 50 mV 0 to 105 Modified core voltage, core and VCO frequency,
and power specifications; modified PLL_CFG
settings. This document describes all
XPC74x5RXnnnLC devices. R ev. 0 of the
MPC7455 RISC Microprocess or Hardware
Specifications originally described these devices
but later revi sions of t hat documen t describe on ly
later devic es .
XPC7455RX733LC 733
XPC7455RX800LC 800
XPC7455RX867LC 867
XPC7455RX933LC 933
PPC7455RX1000LC 1000
XPC7445RX600LC 600
XPC7445RX733LC 733
XPC7445RX800LC 800
XPC7445RX867LC 867
XPC7445RX933LC 933
PPC7445RX1000LC 1000
Note: The X prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a
qualifi ed tec hn ology to simulate norm al pr oduction. These parts have only prel im ina ry rel ia bil ity and c hara cte riz ati on
data . Before pilot pro duction proto types may b e shipped, wr itten authori zation from t he customer must be on file in th e
applicable sales office acknowledging the qualification status and the fact that product changes may still occur while
shipping pilot production prototypes.
MOTOROLA MPC7455 Part Number Specification for the 3
XPC74x5RXnnnLC Series
Features
1.1 Features
This section summarizes changes to the features of the MPC7455 described in the MPC7455 RISC
Microprocessor Hardware Specifications.
• Power management
— 1.6-V processor core
1.4 General Parameters
• Core power supply: 1.6 V ± 50 mV DC nominal
1.5.1 DC Electrical Characteristics
Table 4 provides the recommended operating conditions for the MPC7455 part numbers described herein.
Table 4. Recommended Operating Conditions
Characteristic Symbol Recommended
Value Unit
Core supply voltage VDD 1.6 V ± 50 mV V
PLL supply voltage AVDD 1.6 V ± 50 mV V
Note: These are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
4MPC7455 Part Number Specification for the MOTOROLA
XPC74x5RXnnnLC Series
General Parameters General Parameters
Table 7 provides the power consumption for the MPC7455 part numbers described herein.
Table 7. Power Consumption for MPC7455
Processor (CPU) Frequency Unit Notes
600 MHz 733 MHz 800 MHz 867 MHz 933 MHz 1 GHz
Full-Power Mode
Typical 13.0 15.6 17.0 18.5 19.9 21.3 W 1, 3
Maximum 17.5 22.0 24.0 26.0 28.0 30.0 W 1, 2
Doze Mode
Typical ——————W1, 3, 4
Nap Mode
Typical 1.4 1.7 1.8 1.9 2.0 2.2 W 1, 3
Sleep Mode
Ty pical 0.85 0.90 0.90 0.95 1.00 1.00 W 1, 3
Deep Sleep Mode (PLL Disabled)
Ty pical 500 500 510 570 610 640 mW 1, 3
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power
(OVDD and GVDD) or PL L sup ply pow er (AVDD). OVDD and GVDD pow er is sy stem d epend ent, bu t is ty pical ly <5%
of VDD power. Worst case power consumption for AVDD < 3 mW.
2. Maximum p ower is me asured at nominal VDD (see Table 4) while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, with or without AltiVec, maximally busy.
3. Ty pical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C in a
system while running a typical code sequence.
4. Doze mode is not a user-definable state; it is an intermediate state between Full-Power and either Nap or Sleep
mode. As a result, power consumption for this mode is not tested.
MOTOROLA MPC7455 Part Number Specification for the 5
XPC74x5RXnnnLC Series
General Para meters
Table 8 provides the clock AC timing specificatons for the MPC7455 part numbers described herein.
Table 12 provides the L3 bus interface AC timing specifications for MSUG2 for the MPC7455 part numbers
described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes600 MHz 733 MHz 800 MHz 867 MHz 933 MHz 1 GHz
Min Max Min Max Min Max Min Max Min Max Min Max
Processor
frequency fcore 500 600 500 733 500 800 500 867 500 933 500 1000 MHz 1
VCO frequency fVCO 1000 1200 1000 1466 1000 1600 1000 1734 1000 1866 1000 2000 MHz 1
Notes:
1. Caution: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequenc y, CPU (core) freq ue ncy, and PLL (VCO) frequ enc y do not exc ee d thei r resp ec tiv e ma xim um or min im um
operating frequencies (see Table 4 in the MPC7455 RISC Microprocessor Hardware Specifications). Refer to the
PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4] settings.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades
Unit NotesL2CR[12] = 0 and L3CR[12 ] = 08L2CR[12] = 1 and L3CR[12] = 18
Min Max Min Max
L3_CLK rise and fall
time tL3CR,
tL3CF
— 1.0 — 1.0 ns 1
Setup times:
Data and parity tL3DVEH,
tL3DVEL
– 0.1 — – 0.1 — ns 2, 3, 4
Input hold times:
Data and parity tL3DXEH,
tL3DXEL
tL3_ECHO_CLK/4
+ 0.6 —t
L3_ECHO_CLK/4
+ 0.6 —ns2, 4
Valid times:
Data and parity tL3CHDV,
tL3CLDV
—(– t
L3_CLK/4)
+ 0.4 —(– t
L3_CLK/4)
+ 0.8 ns 5, 6, 7
Valid times:
All other outputs tL3CHOV —t
L3_CLK/4 + 1.0 — tL3_CLK/4 + 1.2 ns 5, 7
Output hold times:
Data and parity tL3CHDX,
tL3CLDX,
tL3_CLK/4 – 0.4 — tL3_CLK/4 – 0.2 — ns 5, 6, 7
Output hold times:
All other outputs tL3CHOX tL3_CLK/4 – 0.5 — tL3_CLK/4 – 0.3 — ns 5, 7
L3_CLK to high
impedance:
Data and parity
tL3CLDZ —t
L3_CLK/2 — tL3_CLK/2 ns
6MPC7455 Part Number Specification for the MOTOROLA
XPC74x5RXnnnLC Series
General Parameters General Parameters
L3_CLK to high
impedance:
All other outputs
tL3CHOZ —t
L3_CLK/4 + 2.0 — tL3_CLK/4 + 2.0 ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage
of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 R ISC Mic roprocessor
Hardware Specifications). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the MPC7455
RISC Microp roc essor H ard ware Spec if ic atio ns. For consistency with other input setup time specifications, this will
be treated as negati ve input setup time.
4. tL3_ECHO_CLK/4 is one -fourth th e perio d of L3_ECH O_CL Kn. This par ameter i ndica tes tha t the MPC7 455 ca n latch
an input signal that is valid for only a short time before and a short time after the midpoint between the rising and
falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the
falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All
output timings a ssum e a pure ly res istive 5 0-Ω lo ad (see Figure 8 i n the M PC7455 R ISC Micropro cessor Ha rdware
Specifications).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the MPC7455 RISC
Microprocessor Hardware Specifications. For consistency with other output valid time specifications, this will be
treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output
valid and output hold t im es suc h that the speci fie d o u tpu t s ign al w i ll be v al id for a pproximately one L 3_C L K pe riod
sta rting three-fo urths of a cl ock prior to th e edge on w hich the SRAM wil l sample it and ending one-fourth of a clock
period after the edge it will be sampled.
8. These co nfigura tion bi t s allow the AC tim ing of t he L3 in terface to be al tered vi a softwa re. T hey mu st be bo th set or
both cleared; other configurations will increase tL3CSKW1, which may cause unreliable L3 operation.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades
Unit NotesL2CR[12] = 0 and L3CR[12 ] = 08L2CR[12] = 1 and L3CR[12] = 18
Min Max Min Max
MOTOROLA MPC7455 Part Number Specification for the 7
XPC74x5RXnnnLC Series
General Para meters
Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7455
part numbers described herein.
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades
Unit NotesL2CR[12]=0 and L3CR[12]=0 6L2CR[12]=1 and L3CR[12]=1 6
Min Max Min Max
L3_CLK rise and fall
time tL3CR,
tL3CF
— 1.0 — 1.0 ns 1, 5
Setup times:
Data and parity tL3DVEH 1.5—1.5—ns2, 5
Input hold times:
Data and parity tL3DXEH — 0.5 — 0.5 ns 2, 5
Valid times:
Data and parity tL3CHDV —t
L3_CLK/4 + 1.0 — tL3_CLK/4 + 1.2 ns 3, 4, 5
Valid times:
All other outputs tL3CHOV —t
L3_CLK/4 + 1.0 — tL3_CLK/4 + 1.2 ns 4
Output hol d times:
Data and parity tL3CHDX tL3_CLK/4 – 0.4 — tL3_CLK/4 – 0.2 — ns 3, 4, 5
Output hol d times:
All other outputs tL3CHOX tL3_CLK/4 – 0.4 — tL3_CLK/4 – 0.2 — ns 4, 5
L3_CLK to high
impedance:
Data and parity
tL3CHDZ —2.0—2.0ns5
L3_CLK to high
impedance:
All other outputs
tL3CHOZ —2.0—2.0ns5
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor Hardware
Specifications). Input ti mings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of
the signal in question. The output timings are meas ured at the pins. All output timings assume a purely resistive
50-Ω load (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).
4. tL3_CLK/4 is on e-fo urth the peri od of L 3_C L Kn. T his parameter in dic ate s that the specified output signal is ac tua lly
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output
valid a nd outp ut hold times such t hat the s pecif ied out put signal will be valid f or approx imat ely on e L3_CLK p erio d
starting three-fourths of a clock prior to the edge on which the SRAM will sample it an d ending one-fourth of a
cloc k period afte r the edge it will be sampled.
5. Timing behavior and characterization are currently being evaluated.
6. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set
or both cleared; other configurations will increase tL3CSKW1 and tL3CSKW2, which may caus e unreliable L3
operation.
8MPC7455 Part Number Specification for the MOTOROLA
XPC74x5RXnnnLC Series
General Parameters General Parameters
1.9.1 PLL Configuration
The MPC7455 PLL is configured by the PLL_CFG[0:4] signals; note that PLL_CFG[4] was formerly called
PLL_EXT in earlier documentation. For a given SYSCLK (bus) frequency, the PLL configuration signals
set the i nternal CPU and VCO fre quency of operat ion. PLL_CFG[4] will normally be pulled low but can be
asserted for extended modes of operation. The PLL configuration for the MPC7455 is shown in Table 17
for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK
frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz column in Table 8.
Note that th e settings for Rev. C d evices are different than those for subs equent devi ces.
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1 GHz Parts
PLL_CFG
[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz Bus
50 MHz Bus
66.6 MHz Bus
75 MHz Bus
83 MHz Bus
100 MHz Bus
133 MHz
00000 0.5x 2x
01000 2x 2x
01100 2.5x 2x
10000 3x 2x
11100 3.5x 2x
10100 4x 2x 533
(1066)
01110 4.5x 2x 600
(1200)
10110 5x 2x 500
(1000) 667
(1333)
10010 5.5x 2x 550
(1100) 733
(1466)
11010 6x 2x 600
(1200) 800
(1600)
01010 6.5x 2x 540
(1080) 650
(1300) 866
(1730)
00100 7x 2x 525
(1050) 580
(1160) 700
(1400) 933
(1866)
00010 7.5x 2x 500
(1000) 563
(1125) 623
(1245) 750
(1500) 1000
(2000)
11000 8x 2x 533
(1066) 600
(1200) 664
(1328) 800
(1600)
01111 9x 2x 600
(1200) 675
(1350) 747
(1494) 900
(1800)
MOTOROLA MPC7455 Part Number Specification for the 9
XPC74x5RXnnnLC Series
General Para meters
10101 10x 2x 500
(1000) 667
(1333) 750
(1500) 830
(1660) 1000
(2000)
10011 11x 2x 550
(1100) 733
(1466) 825
(1650) 913
(1826)
10111 12x 2x 600
(1200) 800
(1600) 900
(1800) 996
(1992)
01011 13x 2x 650
(1300) 865
(1730) 975
(1950)
11001 14x 2x 700
(1400) 933
(1866)
00011 15x 2x 500
(1000) 750
(1500) 1000
(2000)
11011 16x 2x 533
(1066) 800
(1600)
00110 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly
11110 PLL off PLL off, no core clocking occurs
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1 GHz Parts (continued)
PLL_CFG
[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz Bus
50 MHz Bus
66.6 MHz Bus
75 MHz Bus
83 MHz Bus
100 MHz Bus
133 MHz
10 MPC7455 Part Number Specification for the MOTOROLA
XPC74x5RXnnnLC Series
Ordering Information Ordering Information
1.11 Ordering Information
1.11.1 Part Numbers Addressed by this Specification
Table 21 provides the ordering information for the MPC7455 parts described in this document.
Table 21. Part Marking Nomenclature
XPC 74x5RX nnn x x
Product
Code Part
Identifier Package Processor
Frequency 1Application Modifier Revision Level
XPC 27455
7445 RX = CBGA 600
733
800
867
933
L: 1.6 V ± 50 mV
0 to 105°CC: 2.1; PVR = 8001 0201
PPC 31000
Notes:
1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by other
specifications may support other maximum core frequencies.
2. The X prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a
qualified technology to simulate normal production. These parts have only preliminary reliability and
charac teri zation data. Before pi lot production proto typ es may be s hip ped , written authorization from the cus tom er
must be on file in the applicable sales office acknowledging the qualification status and the fact that product
changes may still occur while shipping pilot production prototypes.
3. The P prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes
may be shipped, written authoriz ation from the customer must be on file in the applicable sales office
acknowledging the qualification status and the fact that product changes may still occur while shipping pilot
production prototypes.
MOTOROLA MPC7455 Part Number Specification for the 11
XPC74x5RXnnnLC Series
Document Revision History
1.11.3 Part Marking
Parts are marked as the example shown in Figure 29.
Figure 29. Motorola Part Marking for BGA Device
Document Revision History
Table B provides a revi sion history for this part number specification.
Table B. Document Revision History
Rev. No. Substa ntive Change(s)
0 Initial rele as e.
BGA
XPC7455
RX800LC
MMMMMM
ATWLYYWWA
7450
BGA
XPC7445
RX8000LC
MMMMMM
ATWLYYWWA
7440
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
MPC7455RXLCPNS/D
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