SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), Flat
(W), and DIP (J,N) Packages
description
The ’AC74 are dual positive-edge-triggered
D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
The SN54AC74 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AC74 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
†H†
H H ↑HHL
H H ↑LLH
H H L X Q0Q0
†This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AC74 . . . FK PACKAGE
(TOP VIEW)
SN54AC74 ...J OR W PACKAGE
SN74AC74 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
NC – No internal connection
CC
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK 12
2D 13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package 1.25 W. . . . . . . . . . . . . . . . . . .
DB package 0.5 W. . . . . . . . . . . . . . . . . . .
N package 1.1 W. . . . . . . . . . . . . . . . . . . .
PW package 0.5 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions (see Note 3)
SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 5.5 V 1.65 1.65
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 3 V –12 –12
IOH High-level output current VCC = 4.5 V –24 –24 mA
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
IOL Low-level output current VCC = 4.5 V 24 24 mA
VCC = 5.5 V 24 24
∆t/∆vInput transition rise or fall rate 0 8 0 8 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54AC74 SN74AC74
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
3 V 2.9 4.49 2.9 2.9
IOH = –50 µA4.5 V 4.4 5.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
VOH
IOH = –12 mA 3 V 2.56 2.4 2.46
V
V
OH
IOH =24mA
4.5 V 3.86 3.7 3.76
V
I
OH = –
24
mA
5.5 V 4.86 4.7 4.76
IOH = –50 mA†5.5 V 3.85
IOH = –75 mA†5.5 V 3.85
3 V 0.002 0.1 0.1 0.1
IOL = 50 µA4.5 V 0.001 0.1 0.1 0.1
5.5 V 0.001 0.1 0.1 0.1
VOL
IOL = 12 mA 3 V 0.36 0.5 0.44
V
V
OL
IOL =24mA
4.5 V 0.36 0.5 0.44
V
I
OL =
24
mA
5.5 V 0.36 0.5 0.44
IOL = 50 mA†5.5 V 1.65
IOL = 75 mA†5.5 V 1.65
II
Data pins
VI=V
CC or GND
55V
±0.1 ±1±1
µA
I
IControl pins
V
I =
V
CC
or
GND
5
.
5
V
±0.1 ±1±1µ
A
ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
CiVI = VCC or GND 5 V 3 pF
†Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V
"
0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 0 100 0 100 0 100 MHz
t
Pulse duration
PRE or CLR low 5.5 8 7
ns
t
w
P
u
lse
d
u
ration
CLK 5.5 8 7
ns
t
Set p time data before CLK↑
Data 4 5 4.5
ns
t
su
S
etup t
i
me,
d
ata
b
e
f
ore
CLK↑
PRE or CLR inactive 0 0.5 0
ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
VCC = 5 V
"
0.5 V (unless otherwise noted) (see Figur e 1)
TA = 25°C SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 0 140 0 140 0 140 MHz
t
Pulse duration
PRE or CLR low 4.5 5.5 5
ns
t
w
P
u
lse
d
u
ration
CLK 4.5 5.5 5
ns
t
Set p time data before CLK↑
Data 3 4 3
ns
t
su
S
etup t
i
me,
d
ata
b
e
f
ore
CLK↑
PRE or CLR inactive 0 0.5 0
ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V
"
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C SN54AC74 SN74AC74
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 100 125 70 95 MHz
tPLH
PRE or CLR
QorQ
3.5 8 12 1 13 2.5 13
ns
tPHL
PRE
or
CLR
Q
or
Q
4 10.5 12 1 14 3.5 13.5
ns
tPLH
CLK
QorQ
4.5 8 13.5 1 17.5 4 16
ns
tPHL
CLK
Q
or
Q
3.5 8 14 1 13.5 3.5 14.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V
"
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C SN54AC74 SN74AC74
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 140 160 95 125 MHz
tPLH
PRE or CLR
QorQ
2.5 6 9 1 9.5 2 10
ns
tPHL
PRE
or
CLR
Q
or
Q
3 8 9.5 1 10.5 2.5 10.5
ns
tPLH
CLK
QorQ
3.5 6 10 1 12 3 10.5
ns
tPHL
CLK
Q
or
Q
2.5 6 10 1 10 2.5 10.5
ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 45 pF
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC 50% VCC
50% VCC
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50% VCC 50% VCC
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × VCC
500 Ω
500 Ω Open tPLH/tPHL Open
TEST S1
VCC
0 V
50% VCC 50% VCC
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr
v
2.5 ns, tf
v
2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
