cy ANALOG Fast, Complete 12-Bit Sampling A/D Converter DEVICES with Microprocessor Interface AD1674 REV. B 1.1 Scope. This specification covers the detail requirements for a 12-bit resolution sampling A/D converter with complete microprocessor interface and a high performance reference. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number! -1 AD1674T(X)/883B NOTE 'See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description D ~~ D-28 28-Pin Ceramic DIP 1.3 Absolute Maximum Ratings. (T,=+25C unless otherwise noted) Vec to Digital Common 2.0.2... ee eee eee ee eens +16.5 V Veg to Digital Common ........ 2.020000. c cee eee een eee tence tenes -16.5 V Viocic to Digital Common .... 2.0.0.0... ec ete ee ete e nnn eees +7V Analog Common to Digital Common .... 01... 6 cece cet ent e ene e tne enes +1V Control Inputs (CE, CS, Ag, 12/8, R/C) to Digital Common ............ ~0.5 V to Vuogic +0.5 V Analog Inputs (REF IN, BIP OFF, 10 Vy) to Analog Common ......-.......-..0-- Veg to Voc 20 Viy to Analog Common ... 6... ee eet eeetn ee tee ened Veg to +24 V REF OUT 20 ee eee eee eee tte e nae Indefinite Short to Common Momentary Short to Voc Power Dissipation 2.0... 0... ccc eee ete teen e teen eeeeneene 825 mW Storage Temperature Range ... 0.2.0... cece eect nett eee nens 65C to +150C Lead Temperature (Soldering 10 sec) 2.6... cece ne teen tee ne eertens +300C 1.5 Thermal Characteristics. Thermal Resistance @j, = 25C/W Ora = 60C/W ANALOG-TO-DIGITAL CONVERTERS 6-75 ANALOG-TO-DIGITAL CONVERTERS aAD1674 SPECIFICATIONS Table 1. Design Sub Sub 7 Limit Group | Group Test Symbol | Device | @+25C | 1 2,3 Test Condition" Unit Power Dissipation Pp 1 575 575 575 Three-Stated Outputs mW max Input Resistance Rw -1 3 3 10 V Span kQ min 7 kKQmax 6 6 20 V Span kQnmin ; 14 14 kQmax Internal Reference Output Voltage? | Vper -1 +9.9 +9.9 Bipolar 20 V Span V min 7 +101 +101 2.0 mA External Load V max on Logic Input High Voltage CE, CS, RIC, Ag Vin -l 2.0 2.0 2.0 +V min Logic Input Low Voltage - CE, CS, R/C, Ag Vir -1 0.8 0.8 0.8 +V max Logic Input Current - CE, CS, RIC, Ag lun ~1 10 10 10 Vin = 5.0 V; Viz = 0.0 V | pA max Logic Output High Voltage ~ DB1I-DBO Vou -1 2.4 2.4 2.4 Isource = 500 pA +V min Logic Output Low Voltage OS DB11-DBO, STS Vo. ~1 0.4 0.4 0.4 Ismx = 1.6mA +V max Three-State Output Leakage Outputs Three-Stated 7 DB11-DBO lott -1 10 10 10 Vin = 5.0V +pA max Power Supply Current I ~1 8 8 8 Outputs Three-Stated mA max ~ lee 14 14 14 REF OUT to REF IN leg 18 18 18 through 50 2 Integral Nonlinearity INL -1 1/2 v2 1 Major Transitions +LSB max Unipolar 10 V Span Bipolar 20 V Span Differential Nonlinearity? DNL -1 12 12 12 All Codes Tested Bits min | Unipolar 10 V Span Bipolar 20 V Span Power Supply Rejection* PSR -1 1 1 1 See Note 5 +LSBmax Unipolar 10 V Span 12 2 1/2 See Note 6 1 1 1 See Note 7 Unipolar Offset Error Vose 1 2 2 10 V Span +LSB max Unipolar Offset Drift TCyos -1 1 10 V Span +LSB max Bipolar Offset Error Boor -1 3 3 20 V Span +LSB max Bipolar Offset Drift TCBpog | 1 2 20 V Span +LSB max Full-Scale Calibration Error Ag -1 0.125 0.125 Bipolar 20 V Span +% of FSR max Au ~1 0.125 Unipolar 10 V Span Full-Scale Calibration Drift TCA, ~1 7 Bipolar 20 V Span +LSB max 6-76 ANALOG-TO-DIGITAL CONVERTERS REV. BDesign | Sub Sub Limit Group | Group Test Symbol | Device | @+25C | 4 5,6 Test Condition Unit Signal to Noise and Distortion SAN+D) |] -1 70 70 70 fy = 10 KHz, fsampre = 100 kSPS | dB min Total Harmonic Distortion THD -1 ~82 82 82 | fy = 10 kHz, fgampre = 100 KSPS | dB max Peak Spurious or Harmonic Component -1 82 82 82 fry = 10 KHz, fsampce = 100 kSPS | dB max Intermodulation Distortion IMD -1 80 80 80 Second Order Products dB max ~80 80 80 | Third Order Products Design | Sub Sub Limit Group | Group Test Symbol | Device | @+25C | 9 10, 11 | Test Condition Unit Converter Start Timing : Conversion Time tc -1 8 8 8 To 8-Bits ps max 10 10 10 To 12-Bits ps max ' STS Delay from CE tose 1 200 200 225 Timing per Figure 1 ns max CE Pulse Width tec -1 50 50 50 Timing per Figure 1 ns min CS to CE Setup tssc -1 50 50 50 Timing per Figure 1 ns min CS Low During CE High usc -1 50 50 50 Timing per Figure 1 ns min RIC to CE Setup tsrc -1 50 50 50 Timing per Figure 1 ns min R/C Low During CE High ture -1 50 50 50 Timing per Figure | ns min Ao to CE Setup Usac -1 0 0 0 Timing per Figure 1 ns min A, Valid During CE High tac -1 50 50 50 Timing per Figure 1 ns min Read TimingFull Control Mode Access Time top ~l 150 150 150 Load per Figure 3 and Table 2 ms max Data Valid After CE Low tup -1 25 25 15 Timing per Figure 2 ns min Output Float Delay ta -1 150 150 150 Load per Figure 3 and Table 2 ns max CS to CE Setup tssr -1 50 50 50 Timing per Figure 2 ns min RIC to CE Setup torr -1 0 0 0 Timing per Figure 2 ns min A, to CE Setup tsar -1 50 50 50 Timing per Figure 2 ns min CS Valid After CE Low tusr -1 0 0 0 Timing per Figure 2 ns min R/C High After CE Low ture -1 0 0 0 Timing per Figure 2 ns min Ag Valid After CE Low lyaR -1 50 50 50 Timing per Figure 2 ns min Read TimingStand-Alone Mode Data Access Time topr -1 150 150 150 Timing per Figures 4a and 4b ns max Low R/C Pulse Width ture -1 50 50 50 Timing per Figures 4a and 4b ns min STS Delay from R/C tps -1 200 200 225 Timing per Figures 4a and 4b ns max Data Valid After R/C Low tupr -1t 25 25 25 Timing per Figures 4a and 4b ns min STS Delay After Data Valid tus -1 0.6 0.6 0.6 Timing per Figures 4a and 4b Ss min _ 1.2 1.2 1.2 Timing per Figures 4a and 4b ys max High R/C Pulse Width tyr ~1 150 150 150 Timing per Figures 4a and 4b ns min NOTES "Tuan 10 Taaxs Voo = +1S_V + 10% or +12 V + 5%, Viogic = +5 V + 10%, Vex = 15 V + 10% or ~12 V + 5% unless otherwise specified; 12/8 con- nected to Vi ogic Ap and CS at Logic 0, CE at Logic 1. 10 V Unipolar50 2 resistor Pin 8 to Pin 10, 50 1 resistor Pin 12 to ground. Analog input connected to Pin 13. 20 V Bipolar50 1 resistor Pin 8 to Pin 12, 50 resistor Pin 8 to Pin 10. Analog input connected to Pin 14. See Figures 1, 2, 3 and 4 for timing information. ?The reference should be buffered for operation on +12 V supplies. 3Minimum resolution for which no missing codes are guaranteed. *Change in the full-scale unipolar 10 V span as power supply voltage is varied from min to max specified value. >Test conditions for PSRR: 13.5 V < Voc = 16.5 Vs Viogic = 5 Vs Veg = 15 V3 11.4 V S Vee = 12.6 Vs Veogic = 5 V; Veg = 712 V. 4.5V <= Vposic = 5-5 Vs Veco = 1S Vy Vex = -15V. 716.5 V < Veg < -13.5 V, Vioaic = 5 Vs Veco = 19 V3 -12.6 V S Veg = -11.4 V, Viogic = 5 V3 Vee = 12 Vz. 5fa = 9.08 kHz, fo = 9.58 kHz with feamprg = 100 kHz. REV. B ANALOG-TO-DIGITAL CONVERTERS 6-77 ANALOG-TO-DIGITAL CONVERTERS aAD1674 3.2.1 Functional Block Diagram and Terminal Assignments. 45V SUPPLY AD1674 STATUS Vioaic sts DATA MODE SELECT \ ECT N DB11 (MSB) chip SELECT 3| 6 peB10 B BYTE ADDRESS SHORT CYCLE A, ; pS A READICONVERT fla DBs E CHIP ENABLE LE ol DB7 +12Vi418V SUPPLY ul 6 DBG DIGITAL cc , B F DATA +10V REFERENCE L "ERENCE a pes OUTPUTS ANALOG COMMON T) pea B REFERENCE INPUT ulin DB3 I ~12V/-45V SUPPLY Fl a ut e| 8 DB2 BIPOLAR OFFSET t BIPOFF 8) e pet 10V SPAN INPUT c a DB0 (LSB) } 20V SPAN INPUT DIGITAL COMMON DC 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (57). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 Test Condition (B). +8V 9 VW tL] oare sts [28-4 fa 128 DBt1 oto _{s] cs DB10 28 v4 we |p Fe ooo sa oe is | aC OBa ae How = _{s| CE DB7 rea } t Wi4 +1svo0-_+ 7] Voc DBG6 eHow rt] REF uy pes [21 | 4 {9} ac DB4 ot >{10 REF, DB3 39} t Wi ~150 i343] Vee pB2 pet ote Lhe] BIP OFF DB1 a7 Hq Bavte nc [13 | 10% peo [16 14 ALL RESISTORS 3k, 1/4 WATT 6-78 ANALOG-TO-DIGITAL CONVERTERS REV. BAD1674 CE cE s cs FC RC A Ao sts sts t DB11-DBO psc IMPEDANCE DB11-DB0 HIGH IMPEDANCE tn Figure 1. Converter Start Timing Figure 2. Read Timing Table 2. Load Conditions for Bus Timing Specifications Test Vop Cour Access Time High Z to Logic Low 5V 100 pF Float Time Logic High to High Z OV 10 pF Access Time High Z to Logic High ov 100 pF Float Time Logic Low to High Z 5 Vv 10 pF - RC AC No aan [tbs sTs sTs oor | tuor c |, HIGH-Z_7 HIGH-Z DATA HIGH-Z DATA per1-pBo TEE VALID DBI1-DB0 VALID aN : HL Figure 4a. Stand-Alone Mode Timing Low Pulse for R/C Figure 4b, Stand-Alone Mode Timing High Pulse for R/C Table 3. AD1674 Truth Table CE | CS | R/C | 12/8 | A, | Operation 0 x xX x X | None Xx 1 Xx Xx X | None 1 0 0 Xx 0 Initiate 12-Bit Conversion 1 0 0 x 1 Initiate 8-Bit Conversion 1 0 1 1 X | Enable 12-Bit Parallel Output 1 0 1 0 0 Enable 8 Most Significant Bits 1 0 1 0 1 Enable 4 LSBs and 4 Trailing Zeros REV. B ANALOG-TO-DIGITAL CONVERTERS 6-79 ANALOG-TO-DIGITAL CONVERTERS a