K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM 1M x 32Bit x 4 Banks SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION * * * * rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNGs high performance CMOS * * * * * * * * * * 2.5V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS latency (1, 2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) Special Function Support - Internal TCSR(Temperature Compensated Self Refresh) - PASR(Partial Array Self Refresh) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking. Auto & self refresh 64ms refresh period (4K cycle). Extended Temperature Operation (-25 C ~ 85C). Commercial Temperature Operation (-25 C ~ 70 C). 90Balls Monolithic FBGA(9mm x 13mm) Pb for -FXXX, Pb Free for -HXXX. The K4S28323LE is 134,217,728 bits synchronous high data technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. Max Freq. Interface Package K4S28323LE-F(H)E/N/S/C/L/R60 166MHz(CL=3) 133MHz(CL=3) 90FBGA 105MHz(CL=2) LVCMOS Pb K4S28323LE-F(H)E/N/S/C/L/R1H 105MHz(CL=2) (Pb Free) K4S28323LE-F(H)E/N/S/C/L/R75 K4S28323LE-F(H)E/N/S/C/L/R1L 105MHz(CL=3) *1 - F(H)E/N/S : Normal/Low/Super Low Power, Extended Temp. - F(H)C/L/R : Normal/Low/Super Low Power, Commercial Temp. Note : 1. In case of 40MHz Frequency, CL1 can be supported. FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 1M x 32 1M x 32 Output Buffer 1M x 32 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 1M x 32 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 9 8 7 6 5 4 3 2 90Ball(6x15) CSP 1 1 2 3 7 8 9 B A DQ26 DQ24 V SS VD D DQ23 DQ21 C B DQ28 V DDQ VSSQ V DDQ V SSQ DQ19 D C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ e A D D1 E D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ F E V DDQ DQ31 NC NC DQ16 V SSQ G F V SS DQM3 A3 A2 DQM2 VD D G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 A11 H J K D/2 L M J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS WE DQM0 L V DDQ DQ8 V SS VD D DQ7 V SSQ P M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ R N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 V DDQ VSSQ V DDQ V SSQ DQ4 R DQ13 DQ15 V SS VD D DQ0 DQ2 N E E/2 *2: Top View A A1 Substrate(2Layer) b *1: Bottom View < Top View*2 > #A1 Ball Origin Indicator z Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A 11 Address BA0 ~ BA 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQM 0 ~ DQM 3 Data Input/Output Mask DQ 0 ~ 31 Data Input/Output SAMSUNG Week K4S28323LE - XXXX V DD /VSS Power Supply/Ground V DDQ /VSSQ Data Output Power/Ground [Unit:mm] Symbol Min Typ Max A 1.00 1.10 1.20 A1 0.27 0.32 0.37 E - 9.00 - E1 - 6.40 - D - 13.00 - D1 - 11.20 - e - 0.80 - b 0.40 0.45 0.50 z - - 0.10 May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN , V OUT -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V D D, VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Notes : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85 C for Extended, -25 to 70 C for Commercial) Parameter Symbol Min Typ Max Unit VD D 2.3 2.5 2.7 V 2.3 2.5 2.7 V 1.65 - 2.7 V 1 Supply voltage V DDQ Note Input logic high voltage VI H 0.8 x V DDQ - V DDQ + 0.3 V 2 Input logic low voltage VIL -0.3 0 0.3 V 3 Output logic high voltage VO H V DDQ -0.2 - - V IO H = -0.1mA Output logic low voltage V OL - - 0.2 V I OL = 0.1mA ILI -10 - 10 uA 4 Input leakage current Notes : 1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products. Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V). 2. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 3. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 4. Any input 0V V IN VDDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. Dout is disabled, 0V V OUT V DDQ. CAPACITANCE (VDD = 2,5V, TA = 23C, f = 1MHz, V REF =0.9V 50 mV) Pin Symbol Min Max Unit CCLK - 4.0 pF CIN - 4.0 pF Address(A0 ~ A11, BA 0 ~ BA 1 ) CADD - 4.0 pF D Q0 ~ DQ31 COUT - 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM0 ~ DQM3 Note May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85C for Extended, -25 to 70C for Commercial ) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol ICC1 IC C 2P IC C 2PS ICC2N Precharge Standby Current in non power-down mode ICC2 NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) IC C 3P IC C 3PS ICC3N ICC3 NS Version Test Condition Burst length = 1 tRC tRC (min) IO = 0 mA -60 -75 -1H -1L 90 75 75 70 Unit Note mA 1 CKE VIL (max), tCC = 10ns 0.5 CKE & CLK VIL (max), tCC = 0.5 CKE VIH (min), CS V IH (min), tCC = 10ns Input signals are changed one time during 20ns 15 CKE VIH (min), CLK VIL (max), tCC = Input signals are stable 7 CKE VIL (max), tCC = 10ns 5 CKE & CLK VIL (max), tCC = 5 CKE VIH (min), CS V IH (min), tCC = 10ns Input signals are changed one time during 20ns 25 mA CKE VIH (min), CLK VIL (max), tCC = Input signals are stable 20 mA mA mA mA Operating Current (Burst Mode) ICC4 IO = 0 mA Page burst 4Banks Activated tC C D = 2CLKs 100 75 70 70 mA 1 Refresh Current ICC5 tRC tR C(min) 170 150 140 120 mA 2 Self Refresh Current ICC6 CKE 0.2V -F(H)E/C 1500 -F(H)N/L 600 uA 5 Internal TCSR Max 40 Max 85/70 4 Banks 300 600 2 Banks 260 450 1 Bank 240 350 -F(H)S/R 4 C 3 uA 6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Internal TCSR can be supported. In Commercial Temp : Max 40C/Max 70C, In Extended Temp : Max 40 C/Max 85C 4. K4S28323LE-F(H)E/C** (85/70 C, Full Banks) 5. K4S28323LE-F(H)N/L** (85/70 C, Full Banks) 6. K4S28323LE-F(H)S/R** 7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL =V DDQ /V SSQ) May. 2003 K4S28323LE-F(H)E/N/S/C/L/R AC OPERATING TEST CONDITIONS Mobile-SDRAM (V DD = 2.5V 0.2V, TA = -25 to 85C for Extended, -25 to 70C for Commercial) Parameter Value Unit 0.9 x V DDQ / 0.2 V 0.5 x VDDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time VDDQ Vtt=0.5 x VDDQ 500 50 VOH (DC) = V DDQ -0.2V, IO H = -0.1mA Output VOL (DC) = 0.2V, IOL = 0.1mA Output 500 Z0=50 30pF 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol - 60 - 75 -1H -1L Unit Note Row active to row active delay tRRD (min) 12 15 19 19 ns 1 RAS to CAS delay tRCD (min) 18 19 19 24 ns 1 tRP (min) 18 19 19 24 ns 1 tRAS (min) 42 45 50 60 ns 1 Row precharge time Row active time tRAS (max) Row cycle time t R C(min) Last data in to row precharge tR D L(min) Last data in to Active delay 100 60 64 us ns 1 2 CLK 2,3 tDAL (min) tRDL + tRP - 3 Last data in to new col. address delay tC D L(min) 1 CLK 2 Last data in to burst stop tBDL (min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 4 ea 5 CAS latency=3 Number of valid output data CAS latency=2 CAS latency=1 69 84 2 - 1 - 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum 2RDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge command(tRP). 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter - 60 Symbol Min CAS latency=3 CLK cycle time CAS latency=2 - tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min -1H Max 7.5 1000 - CAS latency=3 CAS latency=2 Max 6.0 tCC CAS latency=1 CLK to valid output delay - 75 9.5 Min -1L Max 9.5 1000 9.5 - Min Unit Note ns 1 ns 1,2 ns 2 Max 9.5 1000 - 12 1000 25 5.4 6 7 7 - 7 7 8 - - - 20 2.5 2.5 2.5 2.5 - 2.5 2.5 2.5 - - - 2.5 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 2.0 2.0 2.5 2.5 ns 3 Input hold time tSH 1.0 1.0 1.5 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 tSHZ 5.4 6 7 7 - 7 7 8 - - - 20 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X L H H H X X H H L BA0,1 L H H X X X Bank Active & Row Addr. H X L L H H X V Read & Column Address Auto Precharge Disable H X L H L H X V Write & Column Address Auto Precharge Disable H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V Auto Precharge Enable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Clock Suspend or Active Power Down L DQM H No Operation Command H H X X H X X X L H H H X A11, A9 ~ A 0 Note 1, 2 3 3 3 3 Row Address L Column Address (A 0 ~ A7) H L Precharge Power Down Mode Exit A10 /AP Column Address (A 0 ~ A7) H X V L X H 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Notes : 1. OP Code : Operand Code A 0 ~ A 11 & BA 0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address BA0 ~ BA1 A11 ~ A10/AP A9 *2 A8 Function "0" Setting for Normal MRS RFU*1 W.B.L Test Mode A7 A6 A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Write Burst Length Mode Select BA1 A9 Length 1 0 1 Reserved 0 Burst 1 1 0 Reserved 1 Single Bit 1 1 1 Reserved BA0 Mode 0 Setting for Normal MRS 0 Reserved * Full Page Length 64Mb : x16(256) / x32(256), 128Mb : x16(512) / x32(256), 256Mb : x16(512) / x32(512), 512Mb : x16(1024) / x32(512) Register Programmed with Extended MRS Address BA1 BA0 Function Mode Select A11 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 RFU *1 A1 A0 PASR Extended MRS for PASR(Partial Array Self Refresh) PASR *3,4 Mode Select BA1 BA0 Mode A2 A1 A0 # of Banks 0 0 Normal MRS 0 0 0 4 Banks(All Banks) 0 1 Reserved 0 0 1 2 Banks(1/2 of All Banks) 1 0 EMRS for Mobile SDRAM 0 1 0 1 Bank(1/4 of All Banks) 1 1 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Reserved Address A11(A12* 1)~A10/AP A9 A8 A7 A6 A5 A4 A3 0 0 0 0 0 0 0 0 Notes 1. RFU(Reserved for future use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 3. In case of 1 Bank Partial Refresh, one bank(BA1=BA0=0) is selected. In case of 2 Banks Partial Refresh, two banks(BA1=0) are selected. 4. Mobile SDRAM supports PASR of 4 Banks(128Mb), 2 Banks(64Mb) and 1Bank(32Mb). May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM Partial Array Self Refresh 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode ; 4 Banks(128Mb), 2 Banks(64Mb), 1 Bank(32Mb). BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 - 4 Banks - 1 Bank - 2 Banks Partial Self Refresh Area Temperature Compensated Self Refresh 1. In order to save power consumption, Mobile-SDRAM has includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : Max 40 C and Max 85C(for Extended), Max 70C(for Commercial). 2. If the EMRS for external TCSR is issued by Mobile SDRAM supports 2 kinds of Internal TCSR range by EMRS setting. Self Refresh Current (Icc 6) Temperature Range Unit -S/R 4 Banks 2 Banks 1 Bank Max 85/70 C 600 450 350 Max 40 C 300 260 240 uA B. Power Up Sequence 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue an extended mode register set command to define PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and EMRS command needs to be issued only when PASR is used. The default state without EMRS command issued is all 4banks refreshed. The device is now ready for the operation selected by EMRS. For operating with PASR, set PASR mode in EMRS setting stage. In order to adjust another mode in the state of PASR mode, additional EMRS set is required but power up sequence is not needed again at this time, In that case, all banks have to be in idle state prior to adjusting EMRS set. May. 2003 K4S28323LE-F(H)E/N/S/C/L/R Mobile-SDRAM C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. BURST LENGTH = 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 May. 2003