1
FEATURES
APPLICATIONS
DESCRIPTION
¼
¼
¼
SIN
SCLK
BCSEL
XLAT
BLANK
GSCLK
SOUT
XERR
VCC
GND
VCC
TLC5943
IC1
OUT0 OUT15
XTEST
¼ ¼
VLED VLED
¼
¼
SIN
SCLK
BCSEL
XLAT
BLANK
GSCLK
RIREF
IREF
SOUT
TLC5943
ICn
OUT0 OUT15
DATA
SCLK
BCSEL
XLAT
BLANK
GSCLK
FLAGS
READ
XERR
READ
¼
VLED VLED
VCC
RIREF
IREF
Controller
XERR
VCC
GND
VCC
XTEST
5
XTESTpinmustbeconnectedtoVCCorGND.
TLC5943
SBVS101 – DECEMBER 2007www.ti.com
16-Channel, 16-Bit PWM LED Driver with7-Bit Global Brightness Control
•Readable Error Information:
23
•16 Channels, Constant Current Sink Output – LED Open Detection (LOD)•50-mA Capability (Constant Current Sink) – Thermal Error Flag (TEF)•16-Bit (65,536 Steps) Grayscale Control with •Noise Reduction:Enhanced Spectrum (ES) PWM
– 4-channel grouped delay to prevent inrush•7-Bit (128 Steps) Global Brightness Control for currentAll Channels with Sink Current
•Operating Temperature: – 40 °C to +85 °C•LED Power-Supply Voltage up to 17 V•V
CC
= 3.0 V to 5.5 V
•Monochrome, Multicolor, Full-Color LED•Constant Current Accuracy:
Displays– Channel-to-Channel = ± 1.5%
•LED Signboards– Device-to-Device = ± 3%
•Display Backlighting•CMOS Level I/O•30-MHz Data Transfer Rate•33-MHz Grayscale Control Clock
The TLC5943 is a 16-channel, constant current sink•Auto Display Repeat driver. Each channel is individually adjustable with65,536 enhanced spectrum pulse-width modulated•Auto Data Refresh
(PWM) steps controlled by grayscale (GS) data. All•Continuous Base LED Open Detection (LOD):
output drivers are adjustable with 128 constant sink– Detect LED opening and LED short to GND
current steps at same value controlled by brightnesscontrol (BC) data. Both GS data and BC data areduring display
writable via a serial interface port. The maximum•Thermal Shutdown (TSD):
current value of all 16 channels can be set by a– Automatic shutdown at high temperature
single external resistor.conditions
– Restart under normal temperature
Typical Application Circuit (Multiple Daisy-Chained TLC5943s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments, Inc.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION, CONTINUED
ABSOLUTE MAXIMUM RATINGS
(1) (2)
TLC5943
SBVS101 – DECEMBER 2007
The TLC5943 has two error detection circuits for LED open detection (LOD) and a thermal error flag (TEF). LODdetects a broken or disconnected LED and shorted LED to GND during the display period. TEF indicates anover-temperature condition; when a TEF is set, all output drivers are turned off. When the TEF is cleared, alloutput drivers are restarted.
blank
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
TRANSPORT MEDIA,PRODUCT PACKAGE-LEAD ORDERING NUMBER QUANTITY
TLC5943PWPR Tape and Reel, 2000TLC5943 HTSSOP-28 PowerPAD™
TLC5943PWP Tube, 50TLC5943RHBR Tape and Reel, 3000TLC5943 5 mm ×5 mm QFN-32
TLC5943RHBT Tape and Reel, 250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Over operating free-air temperature range, unless otherwise noted.
PARAMETER TLC5943 UNIT
V
CC
Supply voltage, V
CC
– 0.3 to +6.0 VI
OUT
Output current (dc): OUT0 to OUT15 60 mAInput voltage range:V
IN
– 0.3 to V
CC
+ 0.3 VSIN, SCLK, XLAT, BLANK, GSCLK, BCSEL, IREFSOUT, XERR – 0.3 to V
CC
+ 0.3 VV
OUT
Output voltage range
OUT0 to OUT15 – 0.3 to +18 VT
J(max)
Maximum operating junction temperature +150 °CT
STG
Storage temperature range – 55 to +150 °CHuman body model (HBM) 2 kVESD rating
Charged device model (CDM) 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.(2) All voltage values are with respect to network ground terminal.
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RECOMMENDED OPERATING CONDITIONS
DISSIPATION RATINGS
TLC5943
SBVS101 – DECEMBER 2007
At T
A
= – 40 °C to +85 °C, unless otherwise noted.
TLC5943
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DC Characteristics: V
CC
= 3 V to 5.5 V
V
CC
Supply voltage 3.0 5.5 VV
O
Voltage applied to output OUT0 to OUT15 17 VV
IH
High-level input voltage 0.7 ×V
CC
V
CC
VV
IL
Low-level input voltage GND 0.3 ×V
CC
VI
OH
High-level output current SOUT – 1 mASOUT 1 mAI
OL
Low-level output current
XERR 5 mAI
OLC
Constant output sink current OUT0 to OUT15 50 mAT
A
Operating free-air temperature – 40 +85 °COperating junctionT
J
– 40 +125 °Ctemperature
AC Characteristics: V
CC
= 3 V to 5.5 V
f
CLK (sclk)
Data shift clock frequency SCLK 30 MHzGrayscale control clockf
CLK (gsclk)
GSCLK 33 MHzfrequencyT
WH0
/ T
WL0
SCLK, GSCLK 10 nsPulse durationT
WH1
XLAT, BLANK 30 nsT
SU0
SIN – SCLK ↑6 nsT
SU1
XLAT ↑– SCLK ↑100 nsT
SU2
BLANK ↓– GSCLK ↑10 nsT
SU3
Setup time BCSEL – SCLK ↑10 nsT
SU4
BCSEL – XLAT ↑30 nsT
SU5
XLAT ↓– SCLK ↑15 nsT
SU6
XLAT ↑– BLANK ↓20 nsT
H0
SIN – SCLK ↑3 nsT
H1
XLAT ↑– SCLK ↑30 nsHold timeT
H2
BCSEL – SCLK ↓10 nsT
H3
BCSEL – XLAT ↑100 ns
OPERATING FACTOR T
A
< +25 °C T
A
= +70 °C T
A
= +85 °CPACKAGE ABOVE T
A
= +25 °C POWER RATING POWER RATING POWER RATING
HTSSOP-28 with
31.67 mW/ °C 3958 mW 2533 mW 2058 mWPowerPAD soldered
(1)
HTSSOP-28 with
16.21 mW/ °C 2026 mW 1296 mW 1053 mWPowerPAD not soldered
(2)
QFN-32
(3)
27.86 mW/ °C 3482 mW 2228 mW 1811 mW
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (availablefor download at www.ti.com ).(2) With PowerPAD not soldered onto copper area on PCB.(3) The package thermal impedance is calculated in accordance with JESD51-5.
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ELECTRICAL CHARACTERISTICS
D(%)= IOUTn -1
(I +I +...+I )
OUT0 OUT1 OUT15
16
´100
.
D(%)=
IdealOutputCurrent
-(IdealOutputCurrent)
(I +I +...I +I )
OUT0 OUT1 OUT14 OUT15
16 ´100
I =41 ´
OUT(IDEAL)
1.20
RIREF
100
(I atV =3.0V)
OUTn CC
(I atV =5.5V) (I atV =3.0V)
OUTn CC OUTn CC
-
5.5V 3V-
D(%/V)= ´
100
3V 1V-
´
(I atV =1V)
OUTn OUTn
(I atV =3V) (I atV =1V)-
OUTn OUTn OUTn OUTn
D(%/V)=
TLC5943
SBVS101 – DECEMBER 2007
At V
CC
= 3.0 V to 5.5 V, and T
A
= – 40 °C to +85 °C. Typical values at V
CC
= 3.3 V and T
A
= +25 °C, unless otherwise noted.
TLC5943
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage I
OH
= – 1 mA at SOUT V
CC
– 0.4 V
CC
V
I
OL
= 1 mA at SOUT 0 0.4 VV
OL
Low-level output voltage
I
OL
= 5 mA at XERR 0.4 V
V
IN
= V
CC
or GND at SIN, SCLK, GSCLK, XLAT,I
IN
Input current – 1 1 µABLANK, BCSEL
SIN/SCLK/GSCLK/XLAT/BCSEL = low, BLANK = high,I
CC1
1 3 mAGSn = FFFFh, BCn = 7Fh, V
OUTn
= 1 V, R
IREF
= 10 k Ω
SIN/SCLK/GSCLK/XLAT/BCSEL = low, BLANK = high,I
CC2
4 8 mAGSn = FFFFh, BCn = 7Fh, V
OUTn
= 1 V, R
IREF
= 2 k Ω
SCLK/GSCLK = 30 MHz, SIN = 15MHz,XLAT/BCSEL/BLANK = low,Supply current (V
CC
)I
CC3
14 30 mAGSn = FFFFh, BCn = 7Fh, Auto Repeat on,V
OUTn
= 1 V, R
IREF
= 2 k Ω
(1)
SCLK/GSCLK = 30 MHz, SIN = 15MHz,XLAT/BCSEL/BLANK = low,I
CC4
27 50 mAGSn = FFFFh, BCn = 7Fh, Auto Repeat on,V
OUTn
= 1 V, R
IREF
= 1 k Ω
(1)
All OUTn = ON, BCn = 7Fh, V
OUTn
= 1 V,I
O(LC)
Constant output current 43 49 55 mAV
OUTfix
= 1 V, R
IREF
= 1 k Ω
BLANK = high, R
IREF
= 1 k Ω, V
OUTn
= 17 V,I
O(LKG1)
Leakage output current 0.1 µAAt OUT0 to OUT15
I
O(LKG2)
Leakage output current No error condition, V
XERR
= 5.5 V, at XERR 1 µA
Constant current error All OUTn = ON, BCn = 7Fh, V
OUTn
= 1 V,ΔI
O(LC)
± 1.5 ± 4 %(pin-to-pin)
(1)
V
OUTfix
= 1 V, R
IREF
= 1 k Ω, at OUT0 to OUT15
Constant current error All OUTn = ON, BCn = 7Fh, V
OUTn
= 1 V,ΔI
O(LC1)
± 3 ± 9 %(device-to-device)
(2)
V
OUTfix
= 1 V, R
IREF
= 1 k Ω
All OUTn = ON, BCn = 7Fh, V
OUTn
= 1 V,ΔI
O(LC2)
Line regulation
(3)
± 1 ± 4 %/VV
OUTfix
= 1 V, R
IREF
= 1 k Ω, at OUT0 to OUT15
All OUTn = ON, DCn = 7Fh, V
OUTn
= 1 V to 3 V,ΔI
O(LC3)
Load regulation
(4)
± 1 ± 3 %/VV
OUTfix
= 1 V, R
IREF
= 1 k Ω, at OUT0 to OUT15
T
(TEF)
Thermal error flag threshold Junction temperature
(5)
+150 +162 +175 °C
T
(HYS)
Thermal error hysteresis Junction temperature
(5)
+5 +10 +20 °C
V
LOD
LED open detection threshold All OUTn = ON 0.2 0.3 0.4 V
V
IREF
Reference voltage output R
IREF
= 1 k Ω1.16 1.20 1.24 V
(1) The deviation of each output from the average of OUT0 – OUT15 constant current. Deviation is calculated by the formula:
(2) The deviation of the OUT0 – OUT15 constant current average from the ideal constant current value.Deviation is calculated by the following formula:
Ideal current is calculated by the formula:
(3) Line regulation is calculated by this equation:
(4) Load regulation is calculated by the equation:
(5) Not tested. Specified by design.
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SWITCHING CHARACTERISTICS
TLC5943
SBVS101 – DECEMBER 2007
At V
CC
= 3.0 V to 5.5 V, T
A
= – 40 °C to +85 °C, C
L
= 15 pF, R
L
= 82 Ω, R
IREF
= 1 k Ω, and V
LED
= 5.0 V. Typical values atV
CC
= 3.3 V and T
A
= +25 °C, unless otherwise noted.
TLC5943
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
R0
SOUT 16Rise time nst
R1
OUTn, BC = 7Fh 10 30t
F0
SOUT 16
nst
F1
Fall time OUTn, BC = 7Fh 10 30t
F2
XERR, C
L
= 100 pF, R
L
= 1 k Ω, V
XERR
= 5 V 100 nst
D0
SCLK ↑to SOUT 25 nst
D1
BLANK ↑to OUT0 sink current off 20 40 nst
D2
GSCLK ↑to OUT0/4/8/12 5 18 40 nsPropagation delay timet
D3
GSCLK ↑to OUT1/5/9/13 20 42 73 nst
D4
GSCLK ↑to OUT2/6/10/14 35 66 106 nst
D5
GSCLK ↑to OUT3/7/11/15 50 90 140 nst
ON_ERR
Output on-time error
(1)
GSn = 0001h, GSCLK = 33 MHz – 20 10 ns
(1) Output on-time error is calculated by the following formula: T
ON_ERR
(ns) = t
OUTON
– T
GSCLK
. t
OUTON
is the actual on-time of the constantcurrent driver. T
GSCLK
is the period of GSCLK.
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FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
SIN
SCLK
BCSEL
XLAT
gsclk33
0
16
16
256
256
256
87
MSBLSB
0 255
MSBLSB
0 255
MSBLSB
SOUT
BrightnessControl(7Bits)/Auto
RepeatEnable(1Bit)ShiftRegister
0 7
MSBLSB
FirstBrightnessControl(7Bits)/Auto
RepeatEnable(1Bit)DataLatch
0 6
MSBLSB
SecondBrightnessControl(7Bits)
DataLatch
FirstGrayscaleDataLatch
(16Bitsx16Channels)
GrayscaleShiftRegister
(16Bitsx16Channels)
LEDOpenDetectionDataLatch
(16LOD)
BLANK
GSCLK
IREF
XTEST
GND
GND
7
16
16
16
OUT0 OUT1 OUT14 OUT15
¼
GSCounter/
AutoRepeat/
Refresh
Reference
Current
Control
LEDOpenDetection
(LOD,16Channels)
ConstantCurrentDriverwith7-Bit
(128Steps)GlobalCurrentControl
OutputSwitchingDelay
(4-ChannelUnit)
16-BitESPWMTimingControl
Thermal
Detection
16
0 255
MSBLSB
SecondGrayscaleDataLatch
(16Bitsx16Channels)
7
1
rptena
XERR
Control
xlatbuf
blankbuf
tderr
gsclk33
gslat2
bclat2
loderr
XERR
xlatbuf
blankbuf
TLC5943
SBVS101 – DECEMBER 2007
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DEVICE INFORMATION
GND
BLANK
XLAT
SCLK
SIN
BCSEL
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
XTEST
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Thermal
Pad
TLC5943
SBVS101 – DECEMBER 2007
PWP PACKAGE
RHB PACKAGE(Top View)
(Top View)
NC = No internal connection.
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TLC5943
SBVS101 – DECEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
NAME PWP RHB I/O DESCRIPTION
SIN 5 2 I Serial data input for grayscale and brightness control data. Schmitt buffer input.Serial data shift clock for GS shift register and BC shift register. Schmitt buffer input. The shiftregister is selected by BCSEL. Data present on the SIN pin are shifted into the shift registerSCLK 4 1 I selected by BCSEL with the rising edge of the SCLK pin. Data in the selected shift register areshifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB data of theselected register appears on SOUT.Data in the Grayscale and Brightness shift register are moved to the respective first data latchXLAT 3 32 I
with a low-to-high transition of this pin.Shift register and data latch select. Schmitt buffer input. When BCSEL is low, Grayscale shiftBCSEL 6 3 I register and first data latch are selected. When BCSEL is high, Brightness Control shift registerand first data latch are selected. BCSEL should not be changed while SCLK is high.Reference clock for Grayscale PWM control. Schmitt buffer input. If BLANK is low, then eachGSCLK 25 24 I
rising edge of GSCLK increments the grayscale counter for PWM control.Blank (all constant current outputs off). Schmitt buffer input. When BLANK is high, all constantcurrent outputs (OUT0 through OUT15) are forced off, the Grayscale counter is reset to '0', andBLANK 2 31 I
the Grayscale PWM timing controller is initialized. When BLANK is low, all constant currentoutputs are controlled by the Grayscale PWM timing controller.Constant current value setting. OUT0 through OUT15 sink constant current is set to desiredIREF 27 26 I/O
value by connecting an external resistor between IREF and GND.Serial data output. This output is connected to Grayscale/Status Information shift register orSOUT 24 23 O
Brightness Control shift register. The connected register is selected by BCSEL.XERR 23 22 O Error output. Open-drain output. XERR goes low when LOD or TEF is detected.OUT0 7 4 O Constant current output.OUT1 8 5 O Constant current outputOUT2 9 6 O Constant current outputOUT3 10 7 O Constant current outputOUT4 11 8 O Constant current outputOUT5 12 9 O Constant current outputOUT6 13 10 O Constant current outputOUT7 14 11 O Constant current outputOUT8 15 14 O Constant current outputOUT9 16 15 O Constant current outputOUT10 17 16 O Constant current outputOUT11 18 17 O Constant current outputOUT12 19 18 O Constant current outputOUT13 20 19 O Constant current outputOUT14 21 20 O Constant current outputOUT15 22 21 O Constant current outputVCC 28 27 — Power-supply voltageGND 1 30 — Power groundXTEST 26 25 I Factory test pin. XTEST must be connected to VCC or GND.12, 13,NC — — No internal connection28, 29
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
INPUT
GND
VCC
SOUT
GND
OUTn
GND
XERR
GND
TEST CIRCUITS
VCC
VCC
GND
IREF OUTn
RIREF
RL
CL
(1) VLED
VCC
VCC
GND
SOUT
CL
(1)
¼¼
VCC
RIREF
VOUTFIX
VOUTn
OUT0VCC
OUTn
OUT15GND
IREF
VCC
VCC
XERR
GND
RL
CL
(1) VXERR
TLC5943
SBVS101 – DECEMBER 2007
Figure 1. SIN, SCLK, XLAT, BCSEL, BLANK, GSCLK Figure 2. SOUT
Figure 3. XERR Figure 4. OUT0 Through OUT15
(1) C
L
includes measurement probe and jig (1) C
L
includes measurement probe and jigcapacitance. capacitance.Figure 5. Rise Time and Fall Time Test Circuit for OUTn Figure 6. Rise Time and Fall Time Test Circuit for SOUT
Figure 8. Constant Current Test Circuit for OUTn(1) C
L
includes measurement probe and jigcapacitance.
Figure 7. Rise Time and Fall Time Test Circuit for XERR
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TIMING DIAGRAMS
T ,T ,T
WH0 WH1 WL0
INPUT(1)
CLOCK
INPUT(1)
DATA/CONTROL
INPUT(1)
T ,T ,T ,T ,T ,T ,T ,T ,T
SU0 SU1 SU2 SU3 SU4 SU5 SU6 H0 H1 H2 H3
,T ,T
TSU TH
VCC
VCC
GND
VCC
GND
GND
50%
50%
50%
TWH TWL
t ,t ,t ,t ,t ,t ,t ,t ,t ,t :
R0 R1 F0 F1 D0 D1 D2 D3 D4 D5
INPUT(1) 50%
50%
90%
10%
OUTPUT(2)
tD
t ort
R F
V orV L
OL OUTn
V orV H
OH OUTn
GND
VCC
TLC5943
SBVS101 – DECEMBER 2007
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Input Timing
(1) Input pulse rise and fall time is 1 ns to 3 ns.(2) Input pulse high level is V
CC
and low level is GND.
Figure 10. Output Timing
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GS0
0A
GS15
15B
GS15
14B
GS15
13B
GS15
12B
GS15
11B
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS15
15A
GS15
14A
GS15
13A
GS15
12A
GS15
11A
GS15
10A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
GS15
15B
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
9
TSU0
TH0 TH1
TWH0
TWL0
TWH0
TWL0
tD0
tD1
tD2
tD2 tOUTON
tD3 tOUTON
tD4 tOUTON
tD5 tOUTON
tD3
tD4
tD5
t /t
R0 F0
2531 2 3 4 5 254 255 256
TWH1
TH2
TH3
TSU6
PreviousData LatestData
SIN
SCLK
65,536
GSCLK
XLAT
BLANK
LatchedData
forGrayscale
(Internal)
SOUT
OFF
ON
OFF
ON
OFF
ON
OFF
ON
TWH1
TSU2
tR1
tF1
TurningoffoutputswiththeBLANKsignal(allGSdataaregreaterthan0300h):
TurningoffoutputswithGSCLK(allGSdataaresetto0001h):
(V H)
OUTn
(V L)
OUTn
OUT
0,4,8,12
OUT
1,5,9,13
OUT
2,6,10,14
OUT
3,7,11,15
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OUT
0,4,8,12
OUT
1,5,9,13
OUT
2,6,10,14
OUT
3,7,11,15
TSU1
t =t T-
ON_ERR OUTON GSCLK
IfGSdata=FFFFh(65535d)
BCSEL
TSU3
TSU4
65,534 65,535 65,53865,537
TGSCLK
TLC5943
SBVS101 – DECEMBER 2007
Figure 11. Grayscale Data Write and Constant Current Output Timing
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N/A BC
7B
BC
7C
BC
7C
BC
7A
BC
7B
BC
6B
BC
6C
BC
6A
BC
6B
BC
5B
BC
5C
BC
5A
BC
5B
BC
4B
BC
4C
BC
4A
BC
4B
BC
3B
BC
3C
BC
3A
BC
3B
BC
2B
BC
2C
BC
2A
BC
2B
BC
1B
BC
1C
BC
1A
BC
1B
BC
0B
BC
0C
BC
0A
BC
0B
TSU0
TH0
TSU3
TWH0
TWL0
tD0
t /t
R0 F0
TH1
1 2 3 4 5
TWH1
TH2
TH3
PreviousData NewBCData
SIN
SCLK
XLAT
LatchedData
forBrightnessControl
(Internal)
SOUT
TSU1
TSU4
BCSEL
6781 2 3 4 5 678
GS0
1A
GS0
0A
GS15
15B
GS15
14B
GS15
13B
GS15
12B
GS15
11B
GS15
2B
GS15
1B
GS15
0B
GS14
15B
GS14
14B
GS14
13B
GS14
12B
GS0
1B
GS0
0B
255 256 1 2 3 4 5 13 14 15 20 254 255 25619181716
TSU1
TH1 TWH1 TSU5
tD0
GS15
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
3
LOD
2
LOD
1
LOD
0TEF GS14
14A
GS14
13A
GS0
1A
GS0
0A
239 238 2
1
GS15
15B
SIDareenteredintheGSshiftregisteratthefirstrisingedgeofSCLKafterXLATgoeslow.
TheSIDreadoutconsistsofthesavedLODresultatthe33rdGSCLKrisingedgeinthepreviousdisplayperiod
andtheTEFdataafterthepreviousTEFdatareadout.
SIN
SCLK
XLAT
SOUT
TheSCLKfallingedgemustbepriortotheXLATrisingedgeincaseSIDisread.
BCSEL Low level('L')
GS0
0
256 255 254 253 244 243 242 241
TLC5943
SBVS101 – DECEMBER 2007
Figure 12. Brightness Control Data Write Timing
Figure 13. Status Information Data Read Timing
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TYPICAL CHARACTERISTICS
10000
1000 010 20 30 40 50
OutputCurrent(mA)
ReferenceResistor( )W
4920
9840
2460
1968 1640
1406
1230 1093
3280
984
4000
3000
2000
1000
0
-40 -20 020 40 60 80
Free-AirTemperature( C)°
PowerDissipationRate(mW)
TLC5943RHB
TLC5943PWP
PowerPADSoldered
TLC5943PWP
PowerPADNotSoldered
100
60
50
40
30
20
10
0
00.5 1.0 1.5 2.0 2.5 3.0
OutputVoltage(V)
OutputCurrent(mA)
T =+25 C
BC=7Fh
°
AI =50mA
O
I =40mA
O
I =30mA
O
I =20mA
O
I =10mA
O
I =5mA
O
55
54
53
52
51
50
49
48
47
46
45 00.5 1.0 1.5 2.0 2.5 3.0
OutputVoltage(V)
OutputCurrent(mA)
I =50mA
BC=7Fh
O
T = 40- °C
AT =+25°C
A
T =+85°C
A
5
4
3
2
1
0
-1
-2
-3
-4
-5
-40 -20 020 40 60 80 100
AmbientTemperature( C)°
DI (%)
OLC
I =50mA
BC=7Fh
O
V =5V
CC
V =3.3V
CC
5
4
3
2
1
0
-1
-2
-3
-4
-5010 20 30 40 50
OutputCurrent(mA)
DI (%)
OLC
T =+25 C°
BC=7Fh
A
V =5V
CC
V =3.3V
CC
TLC5943
SBVS101 – DECEMBER 2007
At V
CC
= 3.3 V and T
A
= +25 °C, unless otherwise noted.
REFERENCE RESISTOR vs POWER DISSIPATION RATEOUTPUT CURRENT vs FREE-AIR TEMPERATURE
Figure 14. Figure 15.
OUTPUT CURRENT vs OUTPUT CURRENT vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 16. Figure 17.
ΔI
OLC
vs ΔI
OLC
vsAMBIENT TEMPERATURE OUTPUT CURRENT
Figure 18. Figure 19.
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60
50
40
30
20
10
0
020 40 60 80 100 120 140
BrightnessControlData(dec)
OutputCurrent(mA)
T =+25 C°
A
I =50mA
OLCMax
I =30mA
OLCMax
I =5mA
OLCMax
60
50
40
30
20
10
0
020 40 60 80 100 120 140
BrightnessControlData(dec)
OutputCurrent(mA)
I =50mA
OLCMax
T = 40- °C
A
T =+25 C°
A
T =+85 C°
A
Time(25ns/div)
I =50mA
T =+25 C,R =82
C =15pF,VLED=5V
,BC=7Fh
° W
OLCMax
A L
L
CH3-OUT15
(GSData=0x001h)
C 2-OUT0
(GSData=0x001h)
H
CH1-GSCLK
(30MHz)
CH1(2V/div)
CH2(2V/div)
CH3(2V/div)
TLC5943
SBVS101 – DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)At V
CC
= 3.3 V and T
A
= +25 °C, unless otherwise noted.
BRIGHTNESS CONTROL LINEARITY BRIGHTNESS CONTROL LINEARITY
Figure 20. Figure 21.
CONSTANT CURRENT OUTPUTVOLTAGE WAVEFORM
Figure 22.
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DETAILED DESCRIPTION
Setting for the Maximum Constant Sink Current Value
R (k )=W
IREF
V (V)
IREF
I (mA)
OLCMax
´41
(1)
TLC5943
SBVS101 – DECEMBER 2007
On the TLC5943, the maximum constant current sink value for each channel, I
OLCMax
, is determined by anexternal resistor, R
IREF
, placed between the IREF and GND pins. The R
IREF
resistor value is calculated withEquation 1 :
Where:
•V
IREF
= the internal reference voltage on the IREF pin (typically 1.20 V)
I
OLCMax
is the largest current for all outputs. Each output sinks the I
OLCMax
current when it is turned on and thebrightness control data are set to the maximum value of 7Fh (127d). The sink current for each output can bereduced by lowering the brightness control data.
R
IREF
must be between 984 Ω(typ) and 9.84 k Ω(typ) in order to keep I
OLCMax
between 5 mA and 50 mA. Theoutput may become unstable when I
OLCMax
is set lower than 5 mA. However, output currents lower than 5 mAcan be achieved by setting I
OLCMax
to 5 mA or higher, and then using brightness control to lower the outputcurrent.
Figure 14 in the Typical Characteristics and Table 1 show the characteristics of the constant sink current versusthe external resistor, R
IREF
.
Table 1. Maximum Constant Current Output versusExternal Resistor Value
I
OLCMax
(mA, Typical) R
IREF
(Ω)
50 98445 109340 123035 140630 164025 196820 246015 328010 49205 9840
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Brightness Control (BC) Function
I (mA)=I (mA)
OUTn OLCMax ´()
BCn
127d
(2)
TLC5943
SBVS101 – DECEMBER 2007
The TLC5943 is able to adjust the output current of all channels (OUT0 to OUT15). This function is calledbrightness control (BC). The BC function allows users to adjust the global brightness of LEDs connected to theoutputs OUT0 to OUT15. All channel output currents can be adjusted in 128 steps from 0% to 100% of themaximum output current, I
OLCMax
. The brightness control data are entered into the TLC5943 via the serialinterface.
Equation 2 determines the sink current for each output (OUTn):
Where:
•I
OLCMax
= the maximum channel current for each channel determined by R
IREF•BCn = the programmed brightness control value for OUTn (BCn = 0 to 127d)
When the IC is powered on, the data in the Brightness Control Shift Register and data latch 1 and 2 are not setto any default values. Therefore, BC data must be written to the BC latch 1 and 2 before turning on the constantcurrent output.
Table 2 summarizes the BC data versus current ratio and set current value.
Table 2. BC Data versus Current Ratio and Set Current Value
SET CURRENT OUTPUT CURRENT OUTPUT CURRENTBC DATA BC DATA BC DATA RATIO TO (mA, Typical) (mA, Typical)(Binary) (Decimal) (Hex) MAX CURRENT (%) AT I
OLCMax
= 50 mA AT I
OLCMax
= 5 mA
000 0000 0 00 0.0 0.0 0.00000 0001 1 01 0.8 0.4 0.04000 0010 2 02 1.6 0.8 0.08... ... ... ... ... ... ... ... ... ... ... ...111 1101 125 7D 98.4 49.2 4.92111 1110 126 7E 99.2 49.6 4.96111 1111 127 7F 100.0 50.0 5.00
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Grayscale (GS) Function (Enhanced Spectrum PWM Operation)
TLC5943
SBVS101 – DECEMBER 2007
The TLC5943 has an enhanced spectrum pulse-width modulation (ES PWM) function. In this PWM control, thetotal display period is divided to 128 display segments. Total display period means the timing from the firstgrayscale clock (GSCLK) input to the 65,536th grayscale clock input after BLANK goes low. Each display periodhas 512 grayscale as a maximum. The driver (OUTn) on time changes depending on the 16-bit grayscale data.Refer to Table 3 for sequence information and Figure 23 for timing information.
Table 3. ES PWM Drive Turn-On Time Length
GS DATA (Dec) GS DATA (Hex) OUTn DRIVER OPERATION
0 0000h No turn on1 0001h Turns on during 1GSCLK period in first display period2 0002h Turns on during 1GSCLK period in first and 65th display periods3 0003h Turns on during 1GSCLK period in first, 65th, and 33rd display periods4 0004h Turns on during 1GSCLK period in first, 65th, 33rd, and 97th display periods5 0005h Turns on during 1GSCLK period in first, 65th, 33rd, 97th, and 17th display periods6 0006h Turns on during 1GSCLK period in first, 65th, 33rd, 97th, 17th, and 81st displayperiods--- --- The number of display periods in which OUTn turns on during 1GSCLK isincreased by GS data increasing in the following order.The display period order in which OUTn turns on :1>65>33>97>17>81>49>113>9>73>41>105>25>89>57>121>5>69>37>101>21>
85>53>117>13>77>45>109>29>93>61>125>3>67>35>99>19>83>51>115>11>
75>43>107>27>91>59>123>7>71>39>103>23>87>55>119>15>79>47>111>31>
95>63>127>2>66>34>98>18>82>50>114>10>74>42>106>26>90>58>122>6>70>
38>102>22>86>54>118>14>78>46>110>30>94>62>126>4>68>36>100>20>84>
52>116>12>76>44>108>28>92>60>124>8>72>40>104>24>88>56>120>16>80>
48>112>32>96>64>128.127 007Fh Turns on during 1GSCLK period in first through 127th display period. No turn on in128th display period only.128 0080h Turns on during 1GSCLK period in all (1 through 128th) display periods.129 0081h Turns on during 2GSCLK periods in first display period and 1GSCLK period inother display periods.--- --- The number of display periods in which OUTn turns on during 2GSCLKs increasesby GS data as when GS is 130 through 254.255 00FFh Turns on during 2GSCLKs period in 1 through 127th display period and turns on1GSCLK period in 128th display period only.256 0100h Turns on during 2GSCLK periods in all (1 through 128th) display periods.257 0101h Turns on during 3GSCLK periods in first display period and 2GSCLK periods inother display periods.--- --- Display period in which OUTn turn-on time increases by GS data, increasing asdoes above operation65478 FEFFh Turns on during 511 GSCLK period in 1 through 127th display period and turns on510 GSCLK period in 128th display period only.65279 FF00h Turns on during 511 GSCLK period in all (1 through 128th) display periods.65280 FF01h Turns on during 512 GSCLK period in first display period + 511 GSCLK period insecond through 128th display period.--- --- Display period in which OUTn turn-on time increases by GS data, increasing asdoes above operation65534 FFFEh Turns on during 512 GSCLK period in first through 63rd and 65th through 127thdisplay period, and turns on 511 GSCLK period in 64th and 128th display periods.65535 FFFFh Turns on during 512 GSCLK period in first through 127th display periods, and turnson 511 GSCLK period in 128th display period only.
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Constant Current Driver ON/OFF Tming in ES-PWM
1 511 16,3822
512 16,383
3 513 16,384 16,386
514 16,385 16,387
32,766
32,767
32,768 32,770
32,769 32,771
49,150
49,151
49,152 49,154
49,153
65,023
65,024
65,025 65,534
65,535
65,536
65,02649,155
¼
OFF
GSCLK
BLANK
ON
(GSDATA=000h)
OUTn
OFF
ON
(GSDATA=001h)
OUTn
Voltagelevel=High( )'H'
Voltagelevel=Low( )'L’
OFF
ON
(GSDATA=002h)
OUTn
OFF
ON
(GSDATA=003h)
OUTn
OFF
ON
(GSDATA=004h)
OUTn
OFF
ON
(GSDATA=0041h)
OUTn
T=GSCLK 1d´
T=GSCLK 1d´T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK 1d´
T=GSCLK
1d´
T=GSCLK 1d´
¼
¼¼¼¼
¼
¼
OFF
OUTn
T=GSCLK 511d´
T=GSCLK 512d´
T=GSCLK 511d
in2ndthrough128thPeriods
´
¼
¼
¼
OFF
ON
(GSDATA=0080h)
OUTn
T=GSCLK 1d´T=GSCLK 1d´T=GSCLK 1d´T=GSCLK 1d´T=GSCLK 1d´
T=GSCLK
1d´
OFF
ON
(GSDATA=0081h)
OUTn
T=GSCLK 1d´T=GSCLK 1d´T=GSCLK 1d´T=GSCLK
2d´
T=GSCLK 1d´
T=GSCLK
1d´
OFF
ON
(GSDATA=0082h)
OUTn
T=GSCLK
2d´
T=GSCLK 1d´T=GSCLK 1d´T=GSCLK
2d´
T=GSCLK 1d´
¼
ON
(GSDATA=FFC0h)
OFF
OUTn
T=GSCLK 511d
in2ndthrough128thPeriods
´
T=GSCLK 512din2ndthrough63rdand65ththrough127thPeriods;
T=
´
GSCLK 511din64thPeriod´
ON
(GSDATA=FFC1h)
T=GSCLK 512d´T=GSCLK 511d´
OFF
OUTn ON
(GSDATA=FFFEh)
T= GSCLK 512din2ndthrough127thPeriods´
T=GSCLK 512d´T=GSCLK 511d´
OFF
OUTn ON
(GSDATA=FFFFh)
1stPeriod 1stPeriod128thPeriod
2nd
Period
97th
Period
33rd
Period
65th
Period
32nd
Period
127th
Period
64th
Period
96th
Period
IfAutoRepeat
isenabled
TLC5943
SBVS101 – DECEMBER 2007
Figure 23. PWM Operation Timing
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t (ns)=T (ns) GSn
OUTON GSCLK ´
(3)
TLC5943
SBVS101 – DECEMBER 2007
When the IC powers on, the data in the Grayscale Shift Register and latch 1/2 are not set to any default value.Therefore, grayscale data must be written to the Grayscale latch before turning on the constant current output.Additionally, BLANK should be high when the device turns on, to prevent the outputs from turning on before theproper grayscale and brightness control values can be written. All constant current outputs are always off whenBLANK is high. Equation 3 determines each output (OUTn) total on time (t
OUTON
):
Where:
•T
GSCLK
= the period of GSCLK•GSn = the programmed grayscale value for OUTn (GSn = 0 to 65,535d)
Table 4 summarizes the GS data versus OUTn on duty and on time.
Table 4. GS Data versus OUTn Total On Duty
GS DATA (Decimal) GS DATA (Hex) ON-TIME DUTY (%) GS DATA (Decimal) GS DATA (Hex) ON-TIME DUTY (%)
0 0 0 32768 8000 50.0011 1 0.002 32769 8001 50.0022 2 0.003 32770 8002 50.0043 3 0.005 32771 8003 50.005--- --- --- --- --- ---8191 1FFF 12.499 40959 9FFF 62.4998192 2000 12.5 40960 A000 62.5018193 2001 12.502 40961 A001 62.502--- --- --- --- --- ---16381 3FFD 24.996 49149 BFFD 74.99716382 3FFE 24.997 49150 C000 74.99816383 3FFF 24.999 49151 C001 7516384 4000 25 49152 C002 75.00116385 4001 25.002 49153 C003 75.00316386 4002 25.003 49154 C004 75.00416387 4003 25.005 49155 C005 75.006--- --- --- --- --- ---24575 5FFF 37.499 57343 DFFF 87.524576 6000 37.501 57344 E000 87.50124577 6001 37.502 57345 E001 87.503--- --- --- ---32765 7FFD 49.996 65533 FFFD 99.99732766 7FFE 49.998 65534 FFFE 99.99832767 7FFF 49.999 65535 FFFF 100
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Auto Display Repeat Function
GSCLK
BLANK
Brightness
1stLatch
Bit7
OUTn
(GSData=FFFFh)
OFF
ON
Bit7= ‘0’
(AutoRepeatOff)
1 1 1 1
162 2 2 2 2
73 3 3 8
44 4 9
5 5 5 1065,533
65,534
65,535
65,536
65,533
65,534 65,534
65,535 65,535
65,536 65,536
1stof128
displayperiod 1stof128
displayperiod
2ndof128
displayperiod
3rdof128
displayperiod
Displayperiodrepeated
byAutoRefreshfunction
OUTnisforcedoff
whenBLANKgoeshigh
OUTnisnot
turnedonuntil
nextBLANK
fallingedge
¼¼ ¼
Bit7= ‘1’
(AutoRepeatOn)
TLC5943
SBVS101 – DECEMBER 2007
This function can repeat the total display period without a BLANK signal as long as GSCLK is input as Figure 24shows. This function can be switched on or off by the data of bit 7 in the first latch of the Brightness Control.When bit 7 is '1', Auto Repeat is enabled and the entire display period repeats without a BLANK signal. When bit7 is '0', Auto Repeat is disabled and the entire display period executes only one time after the falling edge ofBLANK.
Figure 24. Auto Repeat Display Function Timing
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Auto Data Refresh Function
SIN
SCLK
BCSEL
XLAT
SOUT
OUTn
GSCLK
BLANK
GSShiftRegister
(Internal)
GSData
1stLatch(Internal)
GSData
2ndLatch(Internal)
GS0
4A
GS0
3A
GS0
3
GS0
4
GS0
2A
GS0
2
GS0
1B
GS0
1
GS0
0A
GS0
0
BC
7A
GS15
15A
BC
7
BC
7A
BC
6A
BC
6
BC
5A
BC
5
BC
4A
BC
4
BC
3A
BC
3
BC
2A
BC
2
BC
1A
BC
1
BC
0A
BC
0
GS15
15B
GS15
15A
GS15
14A
GS15
14B
GS15
13B
GS15
13A
GS15
12B
GS15
12A
GS15
11A
Highlevel( H )=BrightnessRegisterisselected' '
65,535 1 2 3 4 5 678
Lowlevel( L )' '
LatestGrayscaleData
LatestGrayscaleDataPreviousGrayscaleData
PreviousGrayscaleData
PreviousBrightnessData
PreviousBrightnessData
PWM/BrightnessControlledbyPreviousData PWM/BrightnessControlledbyLatestData
PreviousBrightnessData(Bit0 Bit6)-
LatestGrayscaleData
LatestBrightnessData
LatestBrightnessData
LatestBrightnessData(Bit0 Bit6)-
BCShiftRegister
(Internal)
BCData
1stLatch(Internal)
BCData
2ndLatch(Internal)
OFF
ON
251 255254253252 256 1 81 42 3
Lowlevel( L )=GrayscaleRegisterisselected' '
2 4
35
65,536
67
TLC5943
SBVS101 – DECEMBER 2007
This function allows users to input Grayscale (GS) data or Brightness Control (BC) data any time withoutsynchronizing the input to the BLANK signal. If GS data or BC data are input during a display period, the inputdata are held in the first latch for each data register. Data are then transferred to the second latch when the65,536th GSCLK occurs. The second latch data are used for the next display period. Figure 25 throughFigure 27 show the timing.
However, when the high level signal of BLANK occurs before the 65,536th GSCLK, then the first latch dataupload to the second latch immediately. Also, when the XLAT rising edge inputs while BLANK is at a high level,then the selected shift register data are transferred to the first and second latch at the same time. Bit 7 data ofBC update immediately whenever the data are written into the first latch.
If there is no BLANK input when Auto Repeat is enabled.
Figure 25. Auto Refresh Data Function Timing 1
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 21
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SIN
SCLK
BCSEL
XLAT
SOUT
OUTn
GSCLK
BLANK
GSShiftRegister
(Internal)
GSData
1stLatch(Internal)
GSData
2ndLatch(Internal)
GS0
4A
GS0
3A
GS0
3
GS0
4
GS0
2A
GS0
2
GS0
1B
GS0
1
GS0
0A
GS0
0
BC
7A
GS15
15A
BC
7
BC
6A
BC
6
BC
5A
BC
5
BC
4A
BC
4
BC
3A
BC
3
BC
2A
BC
2
BC
1A
BC
1
BC
0A
BC
0
GS15
15B
GS15
15A
GS15
14A
GS15
14B
GS15
13B
GS15
13A
GS15
12B
GS15
12A
GS15
11A
Highlevel( H )=BrightnessRegisterisselected' '
1 2 3 4 5 678
Lowlevel( L )
' '
LatestGrayscaleData
LatestGrayscaleDataPreviousGrayscaleData
PreviousGrayscaleData
PreviousBrightnessData
PreviousBrightnessData
PWM/BrightnessControlledbyPreviousData PWM/BrightnessControlledbyLatestData
PreviousBrightnessData(Bit0 Bit6)-
LatestGrayscaleData
LatestBrightnessData
LatestBrightnessData
LatestBrightnessData(Bit0 Bit6)-
BCShiftRegister
(Internal)
BCData
1stLatch(Internal)
BCData
2ndLatch(Internal)
OFF
ON
BC
7A
251 252 253 254 255 256 1 2 3 4 5 8 41 2
Lowlevel( L )=GrayscaleRegisterisselected' '
6 7 3
TLC5943
SBVS101 – DECEMBER 2007
When the BLANK input occurs after XLAT.
Figure 26. Auto Refresh Data Function Timing 2
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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SIN
SCLK
BCSEL
XLAT
SOUT
OUTn
GSCLK
BLANK
GSShiftRegister
(Internal)
GSData
1stLatch(Internal)
GSData
2ndLatch(Internal)
GS0
4A
GS0
3A
GS0
3
GS0
4
GS0
2A
GS0
2
GS0
1B
GS0
1
GS0
0A
GS0
0
BC
7A
GS15
15A
BC
7
BC
6A
BC
6
BC
5A
BC
5
BC
4A
BC
4
BC
3A
BC
3
BC
2A
BC
2
BC
1A
BC
1
BC
0A
BC
0
GS15
15B
GS15
15A
GS15
14A
GS15
14B
GS15
13B
GS15
13A
GS15
12B
GS15
12A
GS15
11A
Highlevel( H )=BrightnessRegisterisselected' '
1 2 3 4 5 678
Lowlevel( L )
' '
LatestGrayscaleData
LatestGrayscaleDataPreviousGrayscaleData
PreviousGrayscaleData
PreviousBrightnessData
PreviousBrightnessData
PWM/BrightnessControlledbyPreviousData PWM/BrightnessControlledbyLatestData
PreviousBrightnessData(Bit0 Bit6)-
LatestGrayscaleData
LatestBrightnessData
LatestBrightnessData
LatestBrightnessData(Bit0 Bit6)-
BCShiftRegister
(Internal)
BCData
1stLatch(Internal)
BCData
2ndLatch(Internal)
OFF
ON
BC
7A
251 252 253 254 255 256 1 2 3 4 5 8 1 42
Lowlevel( L )=GrayscaleRegisterisselected' '
6 7 3
GS15
15A
BC
7A
TLC5943
SBVS101 – DECEMBER 2007
When the BLANK input occurs with XLAT.
Figure 27. Auto Refresh Data Function Timing 3
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23
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Grayscale (GS) Shift Register and Data Latch
¼
¼
¼ ¼
¼ ¼
GrayscaleShiftRegister(16Bitsx16Channels)
GSDataforOUT15 GSDataforOUT0
MSB
255 240 239 16 15
LSB
0
GSData
forBit15
ofOUT15
GSData
forBit0
ofOUT15
GSData
forBit0
ofOUT1
GSData
forBit0
ofOUT0
GSData
forBit15
ofOUT0
GSData
forBit15
ofOUT14
GSDataforOUT14 GSDataforOUT1¼
256Bits
ToPWMTimingControlBlock
SINwith
BCSEL=low
SCLKwith
BCSEL=low
¼
¼
¼ ¼
¼ ¼
GrayscaleDataLatch1(16Bitsx16Channels)
GSDataforOUT15 GSDataforOUT0
MSB
255 240 239 16 15
LSB
0
GSData
forBit15
ofOUT15
GSData
forBit0
ofOUT15
GSData
forBit0
ofOUT1
GSData
forBit0
ofOUT0
GSData
forBit15
ofOUT0
GSData
forBit15
ofOUT14
XLATwith
BCSEL=low
GSDataforOUT14 GSDataforOUT1¼
¼ ¼ ¼
GrayscaleDataLatch2(16Bitsx16Channels)
GSDataforOUT15 GSDataforOUT0
MSB
255 240 239 16 15
LSB
0
GSData
forBit15
ofOUT15
GSData
forBit0
ofOUT15
GSData
forBit0
ofOUT1
GSData
forBit0
ofOUT0
GSData
forBit15
ofOUT0
GSData
forBit15
ofOUT14
65,536thGSCLK
whenAutoRepeatis
enabledorBlank
withBCSEL=low
TLC5943
SBVS101 – DECEMBER 2007
The Grayscale (GS) Shift Register and data latch 1 and 2 are each 256 bits in length, and set the PWM timingfor each constant current driver. See Table 4 for the ON time duty of each GS data bit. Figure 28 shows the shiftregister and latch configuration. Refer to Figure 11 for the timing diagram for writing data into the GS shiftregister and latch.
The driver on time is controlled by the data in the GS second data latch. GS data can be set into the latch by therising edge of XLAT with BCSEL = low after writing data into the GS shift register with SIN and GSCLK withBCSEL = low. A BCSEL level change occurs during SCLK = low, and after 100 ns from the rising edge of XLAT.When the device powers up, the data in the GS shift register and latches are not set to any default value.Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANKshould be at a high level when powering on the device, because the constant current may be turned on as well.All constant current output is off when BLANK is at a high level.
Figure 28. Grayscale Shift Register and Data Latch Configuration
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Brightness Control (BC) Shift Register and Data Latch
ToPWMControlBlock ToConstantCurrentDriver
Brightness/AutoRepeatControlShiftRegister(8Bits)
MSB
76 5 432 1
LSB
0
Auto-Repeat
1=Repeat
BCData
forBit6
BCData
forBit5
BCData
forBit4
BCData
forBit3
BCData
forBit2
BCData
forBit1
BCData
forBit0
SINwith
BCSEL=high
SCLKwith
BCSEL=high
SOUT
Shift
Data
Shift
Clock
Brightness/AutoRepeatControlDataLatch1(8Bits)
MSB
76 5 432 1
LSB
0
Auto-Repeat
1=Repeat
BCData
forBit6
BCData
forBit5
BCData
forBit4
BCData
forBit3
BCData
forBit2
BCData
forBit1
BCData
forBit0
XLATrisingedgewith
BCSEL=high
Latch
Signal
BrightnessControlDataLatch2(7Bits)
5432 1
LSB
0
BCData
forBit6
BCData
forBit5
BCData
forBit4
BCData
forBit3
BCData
forBit2
BCData
forBit1
BCData
forBit0
65,536thGSCLKwhen
AutoRepeatisenabled
orBLANKwithBCSEL=high
Latch
Signal
MSB
6
7Bits
1Bit
TLC5943
SBVS101 – DECEMBER 2007
The Brightness Control (BC) data shift register and the first latch are each 8 bits long; the second latch is 7 bitslong. The lower 7 bits in the latch are used to adjust the constant current value for all channels of the constantcurrent driver. The MSB of the first latch is used for the auto repeat mode setting. Table 5 shows the ratio ofsetting the current value against the maximum current value for each BC data point. Figure 29 shows the shiftregister and latch configuration for BC data. Figure 12 shows the timing for writing data.
The driver constant current value is controlled by the data in the second BC data latch. BC data can be set intothe latch at the rising edge of XLAT with BCSEL = high after writing the data into the BC Shift Register by SINand SCLK with BCSEL = high. A BCSEL level change occurs during SCLK = low and after 100 ns from the risingedge of XLAT. When powered up, the data in the BC Shift Register and latches are not set to any default value.Therefore, brightness data must be written to the BC latch before turning on the constant current output.
Table 5. BC Data vs Current Ratio
BC Data (Dec) BC Data (Lower 7 Bits; Hex) Ratio of Setting Current Value Against MAX Value (%)
0 0 01 1 0.82 2 1.63 3 2.4--- --- ---125 7D 98.4126 7E 99.2127 7F 100
Figure 29. Brightness Control Shift Register and Latch Configuration
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Status Information Data (SID)
StatusInformationData(SID)Configuration
¼
¼
¼
MSB
16
OUT15
LODData
OUT14
LODData
OUT1
LODData
OUT0
LODData TEFData
15 2 1
LSB
0
LODDataofOUT15toOUT0 TEF(1Bit)
The16LODbitsforeachchannelandtheTEFbitoverwrite
themostsignificant17bitsoftheGrayscaleShiftRegisteratthe
risingedgeofthefirst SCLKafterXLATgoeslow.
GrayscaleShiftRegister(16Bits 16Channels)´
¼
SOUT
MSB
255
LSB
0
OUT15-Bit15
(LOD-OUT15) OUT0-Bit0 SIN
SCLK
(BCSEL=low)
GSDataforOUT15 GSDataforOUT14-OUT1 GSDataforOUT0
¼
254 241 240
OUT15-Bit1
(LOD-OUT14)
OUT15-Bit1
(LOD-OUT1)
OUT15-Bit0
(LOD-OUT0)
239
OUT14-Bit15
(TEF) ¼
16 15
OUT1-Bit0 OUT0-Bit15
TLC5943
SBVS101 – DECEMBER 2007
Status information data (SID) are 17-bit, read-only data. Both the LED open detection (LOD) error and thethermal error flag (TEF) are shifted out onto the SOUT pin with each rising edge of the shift clock, SCLK. The 16LOD bits for each channel and the TEF bit are written into the 17 most significant bits of the Grayscale ShiftRegister at the rising edge of the first SCLK after XLAT goes low. As a result, the previous data in the 17 mostsignificant bits are lost at the same time. No data are loaded into the other 175 bits. Figure 30 shows the bitassignments. Figure 13 illustrates the read timing for the status information data.
Figure 30. Status Information Data Configuration
The LOD data update at the rising edge of the 33rd GSCLK pulse after BLANK goes low; the LOD data areretained until the next 33rd GSCLK. LOD data are only checked for outputs that are turned on during the risingedge of the 33rd GSCLK pulse. A '1' in an LOD bit indicates an open LED or short LED to GND condition for thecorresponding channel. A '0' indicates normal operation. LOD shows a '0' even if the LED is open or shorted toGND when the grayscale data are less than 1000h (4096d). Therefore, grayscale data must be greater than1001h (4097d) to correctly receive LOD data.
The TEF bit indicates that the IC temperature is too high. The flag also indicates that the IC has turned off alldrivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature hasexceeded the detect temperature threshold (T
(TEF)
) and the driver is turned off. A '0' in the TEF bit indicatesnormal operating temperature conditions. The IC automatically turns the drivers back on when the ICtemperature decreases to less than T
(TEF)
– T
(HYS)
. When the IC powers on, LOD data do not show correct values.Therefore, LOD data must be read from the 33rd GSCLK pulse input after BLANK goes low. Table 6 shows atruth table for both LOD and TEF.
Table 6. LOD and TEF Truth Table
CONDITION
SID DATA LED OPEN DETECTION (LODn) THERMAL ERROR FLAG (TEF)
0 LED is connected (V
OUTn
> V
LOD
) Device temperature is low (temp ≤T
(TEF)
– T
(HYS)
)1 LED is open or shorted to GND (V
OUTn
≤V
LOD
) Device temperature is high (temp > T
(TEF)
)
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Noise Reduction
Continuous Base LED Open Detection
GND
1131 31
2232 32
3333 33
65,533
65,534
65,535
65,536
434 3435 35
GSCLK
BLANK
ON
OFF
OUTn
(Data=FFFFh)
SIDRegisterValue
(Internal)
30 30
IfLODerrorisdetected
IfnoLODerrorisdetected
IfnoLODerrorisdetected
VOUTn
OldLEDopendetectiondata NewLEDopendetectiondata
Low
('L')
XERR
'Hi-Z’
1stGSCLKPeriod
OUTnisturnedoffbyAutoOff
functionifLODerrorisdetected
DependsonLODdata Dependsonprevious
LODdata
IftheOUTnvoltage(V )islessthanVLOD(0.3V,typ)attherisingedgeofthe33rd
GSCLKafterthefallingedgeofBLANK,theLODsetstheSIDbitcorresponding
totheoutputchannelinwhichLEDisopenorshortedtoGNDequalto ‘1.
OUT
ThisLEDOpenDetection(LOD)dataare
keptuntilthenext33rdrisingedgeof
GSCLKafterBLANKgoeslow.
TLC5943
SBVS101 – DECEMBER 2007
Large surge currents may flow through the IC and the printed circuit board (PCB) on which the device is mountedif all 16 LED channels turn on simultaneously at the start of each grayscale cycle. These large current surgescould introduce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5943 turnson the LED channels in a series delay to provide a circuit soft-start feature. The output current sinks are groupedinto four groups of four channels each. The first group is OUT0,4,8,12; the second group is OUT1,5,9,13; thethird group is OUT2,6,10,14; and the fourth group is OUT3,7,11,15. Each group is turns on sequentially with asmall delay between groups; see Figure 11 . Both turn-on and turn-off are delayed.
When the 33rd GSCLK goes high in the first display period after a BLANK falling edge, the LED open detection(LOD) circuit checks the voltage of each constant current output (OUT0 through OUT15 = OUTn) that is turnedon to detect open LEDs and short LEDs to GND. Then, if the voltage of OUTn is less than the LED opendetection threshold (V
LOD
= 0.3 V
TYP
), it sets '1' as the error flag to the LOD error bit that corresponds with theerror channel in the Status Information Data (SID) register. Also, the XERR pin level moves from Hi-Z at thesame time. As a result, GS data should be over 1001h (4097d) to get the LOD result. The OUTn channel thathas the detected LOD error is forced off to avoid an increase in the V
CC
supply current. OUTn turns on at the firstGSCLK after a BLANK falling edge again. LOD data are kept until the next 33rd rising edge of GSCLK in the firstdisplay period after a BLANK falling edge. LOD is always '0' when grayscale data are less than 1001h (4097d).XERR is forced to a Hi-Z state while BLANK is high. When powered up, LOD data are not set to any defaultvalue. Therefore, SID data must be used after OUTn turns on with over 1001h GS data. Figure 31 shows theLED Open Detection timing.
Figure 31. LED Open Detection (LOD) Timing
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 27
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Auto Output Off
GND
1131 31
2232 32
3333 33
65,533
65,534
65,535
65,536
434 3435 35
GSCLK
BLANK
ON
' 'ON
OFF
' 'OFF
VCC
Dissipation
Current
Voltageof
OUTn
SIDRegisterValue
(Internal)
ONSignalofOUTn
(Internal)
(GSdata=FFFFh)
30 30
IfLODerrorisdetected
IfnoLODerrorisdetected
VOUTn
OldLEDopendetectiondata NewLEDopendetectiondata
Remain 'On'(ifno
LODerrordetected)
Turn 'Off'(OUTnisturnedoff
byAutoOfffunctionifLODerror
isdetected)
' 'ON
' 'OFF
Remain 'On'
(ifnoLODerrordetected)
Turn 'Off'(OUTnisturnedoff
byAutoOfffunctionifLODerror
isdetected)
TLC5943
SBVS101 – DECEMBER 2007
If the active OUTn channel is not connected to an LED or if LED is shorted to GND, then V
CC
consumptioncurrent increases. In order to avoid this event, the device has an auto output off function. This function turns offchannel OUTn with a detected LED opening or LED shorting to GND at the 33rd GSCLK after BLANK goes lowautomatically. V
CC
current can be saved by this function. OUTn is controlled normally again after BLANK goeslow. Figure 32 illustrates the auto output off function.
Figure 32. Auto Output Off Function
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Thermal Shutdown and Thermal Error Flag
BLANK
XLAT
T <T
J (TEF) T T³
J (TEF) T T³
J (TEF)
T <T T-
J (TEF) (HYS)
ICJunction
Temperature(T )
J
ON
OFF OFF
OUTn
'0'
'1'
TEF
(Internal) '0'
SCLK
1 2 3 1 2
65,533
65,534
65,535
65,536
34
GSCLK
Low
('L')
XERR
'Hi-Z’
POWER DISSIPATION CALCULATION
P =(V I )+V I´
D CC CC OUT MAX
´ ´ ´NBCn
127d ´dPWM
(4)
TLC5943
SBVS101 – DECEMBER 2007
The Thermal Shutdown (TSD) function turns off all of the constant current outputs on the IC immediately whenthe junction temperature (T
J
) exceeds the threshold (T
(TEF)
= +162 °C, typ) and sets the thermal error flag (TEF)to '1'. The XERR pin goes low at the same time. The XERR pin level and the TEF level are kept until the firstSCLK falling edge after an XLAT falling edge of grayscale data. Then if T
J
is still greater than T
(TEF)
, TEFcontinues at '1' while XERR remains low. If T
J
becomes less than T
(TEF)
– T
(HYS)
, TEF is set to '0' and XERRbecomes Hi-Z. XERR is not forced to a Hi-Z state while BLANK is high. Therefore, the error type TEF or LODcan be distinguished from the BLANK signal control. OUTn is turned on at the first GSCLK after the BLANKfalling edge if T
J
becomes less than T
(TEF)
– T
(HYS)
at the BLANK rising edge.
When the IC powers on, TEF may be set and all output is forced off. Therefore, an XLAT pulse and a BLANKrising edge should be input once to turn on the output. Figure 33 illustrates the TEF/TSD/XERR timing sequence.
Figure 33. TEF/TSD/XERR timing
The device power dissipation must be below the power dissipation rate of the device package (illustrated inFigure 15 ) to ensure correct operation. Equation 4 calculates the power dissipation of the device:
Where:
•V
CC
= device supply voltage•I
CC
= device supply current•V
OUT
= OUTn voltage when driving LED current•I
MAX
= LED current adjusted by R
(IREF)
resistor•BCn = maximum BC value for OUTn•N = number of OUTn driving LED at the same time•d
PWM
= duty ratio defined by BLANK pin or GS PWM value
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TLC5943
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC5943PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943RHBT ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC5943RHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC5943PWPR HTSSOP PWP 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1
TLC5943RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TLC5943RHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5943PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0
TLC5943RHBR QFN RHB 32 3000 367.0 367.0 35.0
TLC5943RHBT QFN RHB 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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