Table Number LIST OF TABLES Page Number 3-1 3-2 3-3 3-4 3-5 MC68336/376 Pin Characteristics ......................................................................... 3-7 MC68336/376 Output Driver Types....................................................................... 3-8 MC68336/376 Power Connections ........................................................................ 3-8 MC68336/376 Signal Characteristics .................................................................... 3-9 MC68336/376 Signal Functions........................................................................... 3-11 4-1 4-2 4-3 4-4 4-5 4-6 4-7 Unimplemented MC68020 Instructions................................................................ 4-10 Instruction Set Summary ..................................................................................... 4-11 Exception Vector Assignments ............................................................................ 4-17 BDM Source Summary ........................................................................................ 4-21 Polling the BDM Entry Source ............................................................................. 4-22 Background Mode Command Summary.............................................................. 4-23 CPU Generated Message Encoding.................................................................... 4-26 5-1 Show Cycle Enable Bits......................................................................................... 5-3 5-2 Clock Control Multipliers ....................................................................................... 5-7 5-3 System Frequencies from 4.194 MHz Re f e r e n................................................. ce 5-9 5-4 Bus Monitor Period .............................................................................................. 5-13 5-5 MODCLK Pin and SWP Bit During Reset............................................................ 5-15 5-6 Software Watchdog Ratio.................................................................................... 5-15 5-7 MODCLK Pin and PTP Bit at Reset..................................................................... 5-16 5-8 Periodic Interrupt Priority ..................................................................................... 5-17 5-9 Size Signal Encoding........................................................................................... 5-21 5-10 Address Space Encoding ................................................................................. 5-21 5-11 Effect of DSACK Signals ................................................................................... 5-23 5-12 Operand Alignment............................................................................................ 5-25 5-13 DSACK, BERR, and HALT Assertion Results ................................................... 5-34 5-14 Reset Source Summary..................................................................................... 5-40 5-15 Reset Mode Selection........................................................................................ 5-41 5-16 Module Pin Functions During Reset .................................................................. 5-45 5-17 SIM Pin Reset States......................................................................................... 5-46 5-18 Chip-Select Pin Functions ................................................................................. 5-56 5-19 Pin Assignment Field Encoding ......................................................................... 5-57 5-20 Block Size Encoding .......................................................................................... 5-58 5-21 Chip-Select Base and Option Register Reset Values........................................ 5-62 5-22 CSBOOT Base and Option Register Reset Values ........................................... 5-63 6-1 SRAM Array Address Space Type ........................................................................ 6-2 7-1 ROM Array Space Type......................................................................................... 7-2 7-2 Wait States Field.................................................................................................... 7-2 8-1 Multiplexed Analog Input Channels ....................................................................... 8-5 MC68336/376 LIST OF TABLES MOTOROLA USER'S MANUAL Rev. 15 Oct 2000 xxi Page Number Table Number 8-2 8-3 8-4 8-5 Analog Input Channels ........................................................................................ 8-12 Queue 1 Priority Assertion................................................................................... 8-17 QADC Clock Programmability ............................................................................. 8-26 QADC Status Flags and Interrupt Sources.......................................................... 8-32 9-1 9-2 9-3 9-4 9-5 Effect of DDRQS on QSM Pin Function ................................................................ 9-5 QSPI Pins .............................................................................................................. 9-9 Bits Per Transfer.................................................................................................. 9-19 SCI Pins............................................................................................................... 9-26 Serial Frame Formats .......................................................................................... 9-27 10-1 10-2 10-3 10-4 10-5 10-6 10-7 CTM4 Time Base Bus Allocation ....................................................................... 10-3 DASM Modes of Operation.............................................................................. 10-11 Channel B Data Register Access .................................................................... 10-11 PWMSM Divide By Options ............................................................................. 10-15 PWM Pulse and Frequency Ranges (in Hz) Using / 2 Option (20.97 MHz) ... 10-17 PWM Pulse and Frequency Ranges (in Hz) Using / 3 Option (20.97 MHz) ... 10-18 CTM4 Interrupt Priority and Vector/Pin Allocation ........................................... 10-20 11-1 11-2 11-3 11-4 TCR1 Prescaler Control................................................................................... 11-14 TCR2 Prescaler Control................................................................................... 11-15 TPU Function Encodings ................................................................................. 11-16 Channel Priority Encodings ............................................................................. 11-17 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 Common Extended/Standard Format Frames................................................... 13-4 Message Buffer Codes for Receive Buffers....................................................... 13-5 Message Buffer Codes for Transmit Buffers...................................................... 13-5 Extended Format Frames .................................................................................. 13-6 Standard Format Frames................................................................................... 13-6 Receive Mask Register Bit Values..................................................................... 13-8 Mask Examples for Normal/Extended Messages .............................................. 13-8 Example System Clock, CAN Bit Rate and S-Clock Frequencies ..................... 13-9 Interrupt Sources and Vector Addresses......................................................... 13-20 A-1 Maximum Ratings.................................................................................................. A-1 A-2 Typical Ratings...................................................................................................... A-2 A-3 Thermal Characteristics ........................................................................................A-2 A-4 Clock Control Timing............................................................................................. A-3 A-5 DC Characteristic s ............................................................................................... A-4 A-6 AC Timing ............................................................................................................ A-6 A-7 Background Debug Mode Timing........................................................................ A-18 A-8 ECLK Bus Timing ................................................................................................ A-19 A-9 QSPI Timing ........................................................................................................A-21 A-10 Time Processor Unit Timing .............................................................................. A-24 A-11 QADC Maximum Ratings .................................................................................. A-25 A-12 QADC DC Electrical Characteristics (Operating) .............................................. A-26 MC68336/376 LIST OF TABLES MOTOROLA USER'S MANUAL Rev. 15 Oct 2000 xxii Page Number Table Number A-13 A-14 A-15 A-16 A-17 A-18 A-19 QADC AC Electrical Characteristics (Operating) .............................................. A-27 QADC Conversion Characteristics (Operating)................................................. A-28 FCSM Timing Characteristics............................................................................A-29 MCSM Timing Characteristics........................................................................... A-29 SASM Timing Characteristics............................................................................A-30 DASM Timing Characteristics ........................................................................... A-30 PWMSM Timing Characteristics........................................................................ A-31 B-1 MC68336 Ordering Information............................................................................. B-4 B-2 MC68376 Ordering Information............................................................................. B-5 D-1 Module Address Map ............................................................................................D-1 D-2 T[1:0] Encoding .....................................................................................................D-3 D-3 SIM Address Map..................................................................................................D-4 D-4 Show Cycle Enable Bits ........................................................................................D-7 D-5 Port E Pin Assignments ......................................................................................D-10 D-6 Port F Pin Assignments.......................................................................................D-11 D-7 Software Watchdog Timing Field ........................................................................D-12 D-8 Bus Monitor Time-Out Period..............................................................................D-13 D-9 Pin Assignment Field Encoding ..........................................................................D-15 D-10 CSPAR0 Pin Assignments ................................................................................D-15 D-11 CSPAR1 Pin Assignments ................................................................................D-16 D-12 Reset Pin Function of CS[10:6].........................................................................D-16 D-13 Block Size Field Bit Encoding ...........................................................................D-17 D-14 BYTE Field Bit Encoding...................................................................................D-18 D-15 Read/Write Field Bit Encoding ..........................................................................D-19 D-16 DSACK Field Encoding .....................................................................................D-19 D-17 Address Space Bit Encodings...........................................................................D-20 D-18 Interrupt Priority Level Field Encoding ..............................................................D-20 D-19 SRAM Address Map..........................................................................................D-21 D-20 RASP Encoding ................................................................................................D-22 D-21 MRM Address Map ...........................................................................................D-23 D-22 ROM Array Space Field ....................................................................................D-24 D-23 Wait States Field ...............................................................................................D-25 D-24 QADC Address Map..........................................................................................D-27 D-25 Queue 1 Operating Modes................................................................................D-31 D-26 Queue 2 Operating Modes................................................................................D-33 D-27 Queue Status ....................................................................................................D-35 D-28 Input Sample Times ..........................................................................................D-36 D-29 Non-multiplexed Channel Assignments and Pin Designations .........................D-37 D-30 Multiplexed Channel Assignments and Pin Designations.................................D-38 D-31 QSM Address Map............................................................................................D-39 D-32 PQSPAR Pin Assignments ...............................................................................D-46 D-33 Effect of DDRQS on QSM Pin Function............................................................D-47 D-34 Bits Per Transfer ...............................................................................................D-48 D-35 CTM4 Address Map ..........................................................................................D-54 MC68336/376 LIST OF TABLES MOTOROLA USER'S MANUAL Rev. 15 Oct 2000 xxiii Page Number Table Number D-36 D-37 D-38 D-39 D-40 D-41 D-42 D-43 D-44 D-45 D-46 D-47 D-48 D-49 D-50 D-51 D-52 D-53 D-54 D-55 D-56 D-57 D-58 D-59 D-60 D-61 D-62 D-63 Interrupt Vector Base Number Bit Field ............................................................D-56 Time Base Register Bus Select Bits .................................................................D-56 Prescaler Division Ratio Select Field ................................................................D-57 Drive Time Base Bus Field................................................................................D-58 Counter Clock Select Field................................................................................D-59 Drive Time Base Bus Field................................................................................D-60 Modulus Load Edge Sensitivity Bits ..................................................................D-60 Counter Clock Select Field................................................................................D-61 DASM Mode Flag Status Bit States ..................................................................D-62 Edge Polarity.....................................................................................................D-64 DASM Mode Select Field ..................................................................................D-64 DASMA Operations...........................................................................................D-65 DASMB Operations...........................................................................................D-66 PWMSM Output Pin Polarity Selection .............................................................D-68 PWMSM Divide By Options ..............................................................................D-69 TPU Register Map.............................................................................................D-71 TCR1 Prescaler Control Bits .............................................................................D-72 TCR2 Prescaler Control Bits .............................................................................D-72 FRZ[1:0] Encoding ............................................................................................D-73 Breakpoint Enable Bits......................................................................................D-74 Channel Priorities..............................................................................................D-78 Parameter RAM Address Map ..........................................................................D-79 TPURAM Address Map.....................................................................................D-79 TouCAN Address Map ......................................................................................D-81 RX MODE[1:0] Configuration ............................................................................D-86 Transmit Pin Configuration................................................................................D-86 Transmit Bit Error Status...................................................................................D-91 Fault Confinement State Encoding ...................................................................D-92 MC68336/376 LIST OF TABLES MOTOROLA USER'S MANUAL Rev. 15 Oct 2000 xxiv