3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Z9972
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07088 Rev. *B Revised January 23, 2002
Features
• Output frequency up to 125 MH z
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or crystal reference input
• Spread Spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC972
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Table 1. Freque ncy Table
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0
00008x
000112x
001016x
001120x
010016x
010124x
011032x
011140x
10004x
10016x
10108x
101110x
11008x
110112x
111016x
111120x
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
Block Diagram Pin Configurati o n
REF_SEL
0
1
0
1
Phase
Detector VCO
LPF
Sync
Frz
DQQA0
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
XIN
XOUT
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1) 2
SELB(0,1) 2
SELC(0,1) 2
FB_SEL(0,1) 2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
FB_SEL1
SYNC
VSS
QC0
VDDC
QC1
SELC0
SELC1
QC2
VDDC
QC3
VSS
INV_CLK
SELB1
SELB0
SELA1
SELA0
QA3
VDDC
QA2
VSS
QA1
VDDC
QA0
VSS
VCO_SEL
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29972
Z9972
Document #: 38-07088 Rev. *B Page 2 of 9
Pin Descriptions
Pin Name PWR I/O Type Description
11 XIN I Oscillator Input. Connect to a crystal.
12 XOUT O Oscillator Output. Connect to a crystal.
9TCLK0 IPUExternal Reference/Test Clock Input.
10 TCLK1 I PU External Reference/Test Clock Input.
44, 46, 48 , 50 QA(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.
32, 34, 36 , 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.
16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.
29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal ope rati on. The
divider rat io for this outp ut is set by FB_SEL(0 :2). See Table 1. A bypass
delay ca pac it or at this output wil l c ontr ol Input Referenc e/ Ou tpu t Banks
phase relationships.
25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchroni-
zation. The risi ng edge of the output pul se is in sync wi th bo th the ris in g
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider
ratios selected.
42, 43 SELA(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
40, 41 SELB(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
19, 20 SELC(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2.
5, 26, 27 FB_SEL(2:0 ) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 2.
52 VCO_SEL I PU VCO Divi der Select Input. When set LO W , the V CO outp ut is divi ded by
2. When set HIGH, the divider is bypassed. See Table 1.
31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
6 PLL_EN I PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when
LOW, the phase-lock loop (PLL) is bypassed.
7 REF_SEL I PU Reference Select Input. When HIGH, the crystal oscillator is selected.
And when LOW, TCLK (0,1) is the reference clock.
8 TCLK_SEL I PU TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
2MR#/OE IPUMaster Rese t/Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
14 INV_CLK I PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
3SCLK IPUSerial Clock Input. Clocks data at SDATA into the internal register.
4SDATA IPUSerial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
33,37, 45, 49 VDDC 3.3V Power Supply for Output Clock Buffers.
13 VDD 3.3V Supply for PLL.
1, 15, 24, 30,
35, 39, 47, 51 VSS Common Ground.
Note:
2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Z9972
Document #: 38-07088 Rev. *B Page 3 of 9
Description
The CY29972 has an integrated PLL that provides low-skew
and low-jitter clock outputs for high-performance micropro-
cessors. Three independent banks of four outputs as well as
an independent PLL feedback output, FB_OUT, provide
exceptional flexibility for possible output configurations. The
PLL is ensured stable operation given that the VCO is
configured to run between 200 MHz to 480 MHz. This allows
a wide range of output frequencies up to125 MHz.
The p hase detec tor com pares th e in put refere nce cl ock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OU T. The inte rnal VC O is run ning at mu ltiple s of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
inputs (see Table 1). The VCO frequency is then divided to
provide the required output frequencies. These dividers are
set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see
Table 2). For situations in which the VCO needs to run at
relatively low frequencies and therefore might not be stable,
assert VCO_SEL LOW to d ivide the VCO freq uency by 2. This
will maintain the desired output relationships, but will provide
an enhanced PLL lock range.
The CY29972 is also capable of providing inverted output
clocks. When INV_CLK is asserted HIGH, QC2 and QC3
output clocks are inverted. These clocks could be used as
feedback outputs to the CY29972 or a second PLL device to
generate early or late clocks for a specific design. This
inversion does not affect the output to output skew.
Glitch- Free Ou tput Frequency Transitions
Cust om ar i ly wh en o u t pu t b uffe r s ha v e t h ei r i n t ern al c ou n t er’s
changed “on the fly’ their output clock periods will:
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequency to which they are being transitioned.
2. contai n stretched clock peri ods . These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency to which they are being transitioned.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for sy stem synchro nizat ion. Th e CY2 9972 m onito rs the
relationship between the QA and the QC output clocks. It
provide s a lo w goi ng pul se, one period in dura tion, o ne peri od
prior to the coincident rising edges of the QA and QC outputs.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output. Note. The SYNC output is defined for all possible
combinations of the QA and QC outputs even though under
some relationships the lower frequency clock could be used as
a synchronizing signal.
Table 2. Frequency Select Inputs
VCO_SEL SELA1 SELA0 QA SELB1 SELB0 QB SELC1 SELC0 QC
0 0 0 VCO/8 0 0 VCO/8 0 0 VCO/4
0 0 1 VCO/12 0 1 VCO/12 0 1 VCO/8
0 1 0 VCO/16 1 0 VCO/16 1 0 VCO/12
0 1 1 VCO/24 1 1 VCO/20 1 1 VCO/16
1 0 0 VCO/4 0 0 VCO/4 0 0 VCO/2
1 0 1 VCO/6 0 1 VCO/6 0 1 VCO/4
1 1 0 VCO/8 1 0 VCO/8 1 0 VCO/6
1 1 1 VCO/12 1 1 VCO/10 1 1 VCO/8
Z9972
Document #: 38-07088 Rev. *B Page 4 of 9
Power Management
The individual output enable/freeze control of the CY29972
allows the user to implement unique power management
schem es i nto t he design. Th e ou tputs are st op ped i n the l ogic
“0” state w he n th e free ze con trol bits are a cti va ted . The seri al
input re gister contains one programmable freeze ena ble bit for
12 of th e 14 output clocks. The Q C0 and FB_OUT outputs can
not be frozen with the se rial port, this avoids any potentia l lock
up sit uati on shou ld an error occu r in t he lo ading o f th e seria l
data. An output is frozen when a logic “0” is progr ammed and
enabled when a logic “1” is written. The enabli ng and free zi ng
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA
input by writing a logic “0” start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equal s the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
SYNC
QC
QA
SYNC
QC
QA
SYNC
QA
QC
SYNC
QC
QA
SYNC
QA
QC
SYNC
QC
QA
SYNC
QC
QA
VCO
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:1 Mode
4:3 Mode
6:1 Mode
Figure 1. Sync Output Waveform s
Z9972
Document #: 38-07088 Rev. *B Page 5 of 9
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
Figure 2. SDATA Input Register
Z9972
Document #: 38-07088 Rev. *B Page 6 of 9
Maximum Ratings
Maximum Input Voltage Relative to VSS:............ VSS – 0.3 V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature:................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD protection...............................................2 kV
Maximum Power Supply:................................................5.5V
Maximum Input Current :.......... ..... ...... ...... ..... ............±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, VIN and VOUT should be constrained to the
range:
VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameters Description Conditions Min. Typ. Max. Unit
VIL Input LOW Voltage VSS 0.8 V
VIH Input HIGH Voltage 2.0 VDD V
IIL Input LOW Current[3] –120 µA
IIH Input HIGH Current 10 µA
VOL Output LOW Voltage[4] IOL = 20 mA 0.5 V
VOH Output HIGH Volta ge[4] IOH = –20 mA 2.4 V
IDDQ Quiescent Supply Current 10 15 mA
IDDA PLL Supply Current VDD only 15 20 mA
IDD Dynamic Supply Current QA and QB @ 60 MHz
QC @ 120 MHz, CL = 30pF 225 mA
QA and QB @ 25 MHz
QC @ 50 MHz, CL = 30pF 125
CIN Input Pin Capacitance 4 pF
Notes:
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50W (or 50W to VDD/2) transmission lines.
Z9972
Document #: 38-07088 Rev. *B Page 7 of 9
AC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C[5]
Parameters Description Conditions Min. Typ. Max. Unit
Tr / Tf TCLK Input Rise/Fall 3.0 ns
Fref Reference Input Frequency Note 6 Note 6 MHz
Fxtal Crystal Oscillator Frequency see Table 3 10 25 MHz
FrefDC Reference Input Duty Cycle 25 75 %
Fvco PLL VCO Lock Range 200 480 MHz
Tlock Maximum PLL lock Time 10 ms
Tr / Tf Output Clocks Rise/Fall Time[7] 0.8V to 2. 0V 0.15 1.2 ns
Fout Maximum Output Frequency Q (³2) 125 MHz
Q (³4) 120
Q (³6) 80
Q (³8) 60
FoutDC Output Duty Cycle[7] TCYCLE/2 – 750 TCYCLE/2 + 750 ps
tpZL, tpZH Output Enable Time[7](all outputs) 2 10 ns
tpLZ, tpHZ Output Disable Time[7](all outputs) 2 8 ns
TCCJ Cycle to Cycle Jitter[7](peak t o peak) ±100 ps
TSKEW Any Output to Any Output Skew[7,8] 250 350 ps
Tpd Propagati on De la y[8,9] TCLK0 QFB = (³8) –270 130 530 ps
TCLK1 –330 70 470
Table 3. Crystal Oscillator Frequency
Parameter Description Conditions Min. Typ. Max. Units
TCFrequency Tolerance Note 10 ±100 PPM
TSFrequency Temperature
Stability (TA –10 to +60°C) Note 10 ±100 PPM
TAAging (first 3 years @ 25°C) Note 10 5PPM/Yr.
CLLoad Capa citance The crys tal ’s rate d load. Note 1 0 20 pF
RESR Effec tive Se ries Resista nce
(ESR) Note 11 40 80 Ohms
Notes:
5. Parameters are guaranteed by design and characterization. Not 100% tested in production.
6. Maximum and minimum input reference is limited by VC0 lock range.
7. Outputs loaded with 30 pF each.
8. 50Ω transmission line terminated into VDD/2.
9. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter.
10. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these
specifications.
11. Larger values may cause this device to exhibit oscillator startup problems.
Order in g In fo rmat io n
Part Number Package Type Production Flow
Z9972AI 52-pin TQFP Industrial, –40°C to +85°C
Z9972
Document #: 38-07088 Rev. *B Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embo died in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support system s application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
All product and company names mentioned in this document are the trademarks of their respective holders.
52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52
51-85131-**
Z9972
Document #: 38-07088 Rev. *B Page 9 of 9
Document Title: Z9972 3.3V, 125 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07088
Rev. ECN No. Issue Date Orig. of
Change Description of Change
** 107124 06/12/01 IKA Convert from IMI to Cypress
*A 108066 07/03/01 NDP Changed Commercial to Industrial
*B 111798 02/06/02 BRK Convert from Word doc to Adobe Framemaker Cypress format
Changed the Timing Diagram and the operating voltage condition
