IDT5T9950PF - Integrated Device Technology

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

sOE

1Q0

Skew

Select 1Q1

1F1:0

2Q0

Skew

Select 2Q1

2F1:0

REF PLL

3Q0

Skew

Select 3Q1

3F1:0

4Q0

4Q1

Skew

Select

4F1:0

PE TEST

MARCH 2001

2001 Integrated Device Technology, Inc. DSC-5869/-c

IDT5T9950/A

PRELIMINARY

INDUSTRIAL TEMPERATURE RANGE

2.5V PROGRAMMABLE

SKEW PLL CLOCK DRIVER

TURBOCLOCK™ II JR.

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT5T9950 is a high fanout 2.5V PLL based clock driver intended

for high performance computing and data-communications applications. A

key feature of the programmable skew is the ability of outputs to lead or lag

the REF input signal. The IDT5T9950 has eight programmable skew

outputs in four banks of 2. Skew is controlled by 3-level input signals that

may be hard-wired to appropriate high-mid-low levels.

When the sOE pin is held low, all the outputs are synchronously enabled.

However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are

synchronously disabled.

Furthermore, when PE is held high, all the outputs are synchronized with

the positive edge of the REF clock input. When PE is held low, all the outputs

are synchronized with the negative edge of REF. The IDT5T9950 has

LVTTL outputs with 12mA balanced drive outputs.

FEATURES:

• REF is 3.3V tolerant

• 4 pairs of programmable skew outputs

• Low skew: 185ps same pair, 250ps all outputs

• Selectable positive or negative edge synchronization:

Excellent for DSP applications

• Synchronous output enable

• Input frequency:

− Std: 6MHz to 160MHz

− A: 6MHz to 200MHz

• Output frequency:

− Std: 6MHz to 160MHz

− A: 6MHz to 200MHz

• 2x, 4x, 1/2, and 1/4 outputs

• 3-level inputs for skew and PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <100ps cycle-to-cycle

• Standard and A speed grades

• Available in 32-pin TQFP Package

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

PIN CONFIGURATION

TQFP

TOP VIEW

30 29 28 27 26 25

11 12 13 14 15 16

REF

GND

TEST

DDQ

GND

3F1

4F0

4F1

4Q1

4Q0

GND

VDDQ

18 GND

sOE

1F1

1F0

1Q0

1Q1

VDDQ

17 GND

PR32

ABSOLUTE MAXIMUM RATINGS (1)

Symbol Rating Max. Unit

DDQ

DD Supply Voltage to Ground –0.5 to +4.6 V

VI DC Input Voltage –0.5 to VDD+0.5 V

REF Input Voltage –0.5 to +4.6 V

Maximum Power TA = 85°C 0.7 W

Dissipation TA = 55°C 1.1

TSTG Storage Temperature Range –65 to +150 °C

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

CAPACITANCE

(TA = 25° C, f = 1MHz, VIN = 0V)

Parameter Description Typ. Max. Unit

CIN Input Capacitance 5 7 pF

NOTE:

1. Capac i t ance applies to al l i nput s except TEST, FS, and nF[1:0].

PIN DESCRIPTION

Pin Name Type Description

REF IN Reference Clock Input

FB IN Feedback Input

TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control

Summary Table) remain in effect. Set LOW for normal operation.

sOE (1) IN Synchronous Output Enable. When HIGH, i t stops cl ock outputs (exc ept 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1

may be used as the feedback signal to maintain phase lock. When TEST is hel d at MID lev el and sOE is HIGH, the nF[1:0] pins act

as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).

PE IN Selectable positi v e or negative edge control. When LOW/HIGH the outputs are s ync hroni zed wi th the negativ e/posi ti ve edge of the

reference clock (has internal pull-up).

nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions

FS IN Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)

nQ[1:0] OUT Four banks of two outputs with programmable skew

VDDQ PWR Power supply for output buffers

VDD PWR Power supply for phase locked loop and other internal circuitry

GND PWR Ground

NOTE:

1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL funct i oni ng as an output disabl e control for indi vidual output bank s. Skew

selections remain in effect unless nF[1:0] = LL.

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate

requirements for special timing relationships between clocked compo-

nents. Skew is selectable as a multiple of a time unit (tU) which ranges

from 782ps to 1.5625ns for Standard version and 625ps to 1.3ns for A

version (see Programmable Skew Range and Resolution Table). There

are nine skew configurations available for each output pair. These con-

figurations are chosen by the nF1:0 control pins. In order to minimize the

number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they

are intended for but not restricted to hard-wiring. Undriven 3-level in-

puts default to the MID level. Where programmable skew is not a re-

quirement, the control pins can be left open for the zero skew default

setting. The Control Summary Table shows how to select specific skew

taps by using the nF1:0 control pins.

PROGRAMMABLE SKEW

EXTERNAL FEEDBACK

By providing external feedback, the IDT5T9950 gives users flexibility

with regard to skew adjustment. The FB signal is compared with the

input REF signal at the phase detector in order to drive the VCO. Phase

differences cause the VCO of the PLL to adjust upwards or downwards

accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

IDT5T9950 IDT5T9950A

FS = LOW FS = MID FS = HIGH FS = LOW FS = MID FS = HIGH Comments

Timing Unit Calculation (tU) 1/(32 x FNOM) 1/(16 x FNOM)1/(8 x F

NOM) 1/(32 x FNOM) 1/(16 x FNOM)1/(8 x F

NOM)

VCO Frequency Range (FNOM) (1,2) 24 to 40MHz 40 to 80MHz 80 to 160 MHz 24 to 50MHz 48 to 100MHz 96 to 200

MHz

Skew Adjustment Range (3)

Max Adjustment: ±7.8125ns ±9.375ns ±9.375ns ±7.8125ns ±7.8125ns ±7.8125ns ns

±67.5° ±135° ±270° ±67.5° ±135° ±270° Phase Degrees

±18.75% ±37.5% ±75% ±18.75% ±37.5% ±75% % of Cycle Time

Example 1, FNOM = 25MHz tu = 1.25ns — — tu = 1.25ns — —

Example 2, FNOM = 37.5MHz tu = 0.833ns — — tu = 0.833ns — —

Example 3, FNOM = 50MHz — tu = 1.25ns — tu = 0.625ns tu = 1.25ns —

Example 4, FNOM = 75MHz — tu = 0.833ns — — tu = 0.833ns —

Example 5, FNOM = 100MHz — — tu = 1.25ns — tu = 0.625ns tu = 1.25ns

Example 6, FNOM = 150MHz — — tu = 0.833ns — — tu = 0.833ns

Example 7, FNOM = 200MHz — — — — — tu = 0.625ns

NOTES:

1. The devic e may be operated outs i de recommended frequency ranges without dam age, but funct i onal operation is not guarant eed.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always

appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated i n their undi vi ded modes. The frequenc y appeari ng at t he REF and FB i nputs

will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO

frequency when the part is c onfigured for frequency multipli cation by us i ng a di v i ded output as the FB i nput.

3. Skew adj ustment range as sumes that a zero skew output is used for feedback . If a skewed Q output i s used f or feedback , then adjus tm ent range wil l

be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is

programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest

FNOM value.

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4)

LL (1) –4tUDivide by 2 Divide by 2

LM –3tU–6tU–6tU

LH –2tU–4tU–4tU

ML –1tU–2tU–2tU

MM Zero Skew Zero Skew Zero Skew

MH 1tU2tU2tU

HL 2tU4tU4tU

HM 3tU6tU6tU

HH 4tUDivide by 4 Inverted (2)

NOTES:

1. LL disables outputs if TEST = MID and sOE = HIGH.

2. When pair #4 is s et to HH (inverted), sOE disables pair #4 HIGH when P E = HIGH, sOE disables pai r #4 LOW when PE = LOW.

RECOMMENDED OPERATING RANGE

Symbol Description Min. Typ. Max. Unit

VDD / VDDQ Power Supply Voltage 2.3 2.5 2.7 V

TAAmbient Operating Temperature -40 — +85 °C

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Conditions Min. Max. Unit

VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 1.7 — V

VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) — 0.7 V

VIHH Input HIGH Voltage (1) 3-Level Inputs Only VDD−0.4 — V

VIMM Input MID Voltage (1) 3-Level Inputs Only VDD/2−0.2 VDD/2+0.2 V

VILL Input LOW Voltage (1) 3-Level Inputs Only — 0.4 V

IIN Input Leakage Current

(REF, FB Inputs Only) VIN = VDD or GND

VDD = Max. −5+5µA

IN = VDD HIGH Level — +200

I33-Level Input DC Current (TEST, FS, nF[1:0]) VIN = VDD/2 MID Level −50 +50 µA

VIN = GND LOW Level −200 —

IPU Input Pull-Up Current (PE) VDD = Max., VIN = GND −100 — µA

IPD Input Pull-Down Current (sOE)V

DD = Max., VIN = VDD — +100 µA

VOH Output HIGH Voltage VDDQ = Min., IOH = −12mA 2 — V

VOL Output LOW Voltage VDDQ = Min., IOL = 12mA — 0.4 V

NOTE:

1. These inputs are normally wired t o VDD, GND, or unconnect ed. Internal terminat ion resistors bi as unconnected inputs to VDD/2. If these inputs are

switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are

achieved.

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

POWER SUPPLY CHARACTERISTICS 5T9950 5T9950A

Symbol Parameter Test Conditions(1) Typ. (2 ) Max. Typ. (2) Max. Unit

IDDQ Quiescent Power Supply Current VDD = Max., TEST = MID, REF = LOW,

PE = LOW, sOE = LOW

All outputs unloaded

20 30 20 30 mA

∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 2.3V 1 30 1 30 µA

FS = L 190 290 190 290

IDDD Dynamic Power Supply Current per Output FS = M 150 230 150 230 µA/MHz

FS = H 130 200 130 200

FS = L FVCO = 40MHz, CL = 0pF 49 — — —

FVCO = 50MHz, CL = 0pF — — 56 —

ITOT Total Power Supply Current FS = M FVCO = 80MHz, CL = 0pF 66 — — — mA

FVCO = 100MHz, CL = 0pF — — 80 —

FS = H FVCO = 160MHz, CL = 0pF 103 — — —

FVCO = 200MHz, CL = 0pF — — 125 —

NOTES:

1. Measurem ents are for divi de-by-1 outputs and DS [1:0] = MM.

2. For nominal voltage and temperat ure.

INPUT TIMING REQUIREMENTS 5T9950 5T9950A

Symbol Description (1) Min. Max. Min. Max. Unit

tR, tFMaximum input rise and fall times, 0.7V to 1.7V — 10 — 10 ns/V

tPWC Input clock pulse, HIGH or LOW 2 — 2 — ns

DHInput duty cycle 10 90 10 90 %

FS = LOW 6 40 6 50

FREF Reference clock input frequency FS = MID 10 80 12 100 MHz

FS = HIGH 20 160 24 200

NOTE:

1. Where pulse widt h i m pl i ed by DH is less than tPWC limit, tPWC limit applies.

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

5T9950 5T9950A

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table

tRPWH REF Pulse Width HIGH (10) 2—— 2 — —ns

RPWL REF Pulse Width LOW (10) 2—— 2 — —ns

UProgrammable Skew Time Unit See Control Summary Table

tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1) (1,2) — 50 185 — 50 185 ps

tSKEW0 Zero Output Skew (All Outputs) (3) — 0.1 0.25 — 0.1 0.25 ns

tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) (4) — 0.1 0.25 — 0.1 0.25 ns

tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) (4) — 0.2 0.5 — 0.2 0.5 ns

tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) (4) — 0.15 0.5 — 0.15 0.5 ns

tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) (1) — 0.3 0.9 — 0.3 0.9 ns

tDEV Device-to-Device Skew (1,5) — — 0.75 — — 0.75 ns

t(φ)REF Input to FB Static Phase Offset (7) −0.3 — 0.3 −0.25 0 0.25 ns

tODCV Output Duty Cycle Variation from 50% −1— 1 −1— 1ns

PWH Output HIGH Time Deviation from 50% (8) — — 1.5 — — 1.5 ns

tPWL Output LOW Time Deviation from 50% (9) ——2 — — 2ns

ORISE Output Rise Time 0.15 0.7 1.5 0.15 0.7 1.5 ns

tOFALL Output Fall Time 0.15 0.7 1.5 0.15 0.7 1.5 ns

tLOCK PLL Lock Time (6) — — 0.5 — — 0.5 ms

tCCJH Cycle-to-Cycle Output Jitter (peak-to-peak)

(divide by 1 output frequency, FS = H) — — 100 — — 100

tCCJM Cycle-to-Cycle Output Jitter (peak-to-peak)

(divide by 1 output frequency, FS = M) — — 200 — — 150 ps

tCCJL Cycle-to-Cycle Output Jitter (peak-to-peak)

(divide by 1 output frequency, FS = L) — — 200 — — 200

NOTES:

1. S kew is the t im e between the earl ies t and t he lates t out put t ransit ion am ong all out puts for whic h the sam e tU del ay has been s elected when al l are

loaded with t he s pecified load.

2. tSKEWPR i s the skew between a pai r of outputs (xQ0 and x Q 1) when al l ei ght outputs are sel ected for 0tU.

3. tSK(0) is the skew between output s when they are sel ected for 0tU.

4. There are 3 c las ses of out puts : Nomi nal (mul tipl e of t U delay), Inv erted (4Q0 and 4Q1 onl y with 4F 0 = 4F1 = HIGH), and Di vided (3Qx and 4Qx only

in Divide-by-2 or Divide-by-4 m ode). Test condi t i on: nF0:1 = MM is set on unused output s.

5. tDEV is the output-to-out put skew between any two devices operating under the same conditions (V DDQ, VDD, ambient tem perat ure, air flow, et c.)

6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal

operating lim i ts. This param et er i s measured from the applicati on of a new signal or frequency at REF or FB unt i l tPD is within specified limits.

7. t(φ) is m easured with REF input ri se and fall times (from 0.7V to 1.7V) of 0. 5ns. Measured f rom 1.25V REF to 1.25V on FB.

8. Measured at 1.7V.

9. Measured at 0.7V.

10. Ref er to Input Timi ng Requi rem ent s table for more detail.

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

AC TEST LOADS AND WAVEFORMS

1.7V

tPWL

tPWH

tORISE tOFALL

0.7V

VTH = 1.25V

≤1ns ≤1ns

1.7V

0.7V

2.5V

VTH = 1.25V

150Ω

VDDQ

Output

150Ω20pF

LVTTL INPUT TEST WAVEFORM

2.5V OUTPUT WAVEFORM

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

REF

OTHER Q

INVERTED Q

REF D IVIDED BY 2

REF D IVIDED BY 4

tREF

tSKEW2

tSKEW 3, 4

tSKEW1, 3, 4 tSKEW 2, 4

tSKEW 3, 4

tSKEW2

tSKEWPR

tSKEW 0, 1

tCCJ, H,

M, L

tODCV tODCV

tRPWH

tRPWL

tSKEWPR

tSKEW 0, 1

t(φ)

AC TIMING DIAGRAM

NOTES:

PE: The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs

change on the negati ve edge of REF, and t he positive edges of the divi de-by-2 and the divide-by-4 signals al i gn.

Skew: T he time between the earli est and the lat est output t ransition among all outputs for whi ch the same t U delay has been select ed when all are

loaded with 20pF and t erm i nat ed wi th 75Ω to VDDQ/2.

tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all ei ght outputs are s el ected for 0tU.

tSKEW0: The skew bet ween out puts when they are selected for 0tU.

tDEV: The out put -to-output sk ew between any two devices operating under t he same conditi ons (VDDQ, VDD, ambient temperature, ai r flow, etc.)

tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifi cations.

tPWH is measured at 1.7V.

tPWL is m easured at 0.7V.

tORISE and tOFALL are measured between 0. 7V to 1.7V.

tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal

operating lim i ts. This param et er i s measured from the applicati on of a new signal or frequency at REF or FB unt i l tPD is within specified limits.

INDUSTRIAL TEMPERATURE RANGE

IDT5T9950/A

2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II

CORPORATE HEADQUARTERS for SALES:

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Santa Clara, CA 95054 fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Turboclock is a registered trademark of Integrated Device Technology, Inc.

ORDERING INFORMATION

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Package

Device Type

5T9950

5T9950A 2.5V P rogramm able Skew P LL C lock Driver TurboClock II Jr.

Thin Quad F lat Pack (P R32)