VND810P-E Double channel high-side driver Features Type RDS(on) IOUT VCC VND810P-E 160 m(1) 3.5 A(1) 36 V 1. Per each channel. ECOPACK(R): lead free and RoHS compliant Automotive Grade: compliance with AEC Guidelines Very low standby current CMOS compatible input On-state open-load detection Off-state open-load detection Thermal shutdown protection and diagnosis Undervoltage shutdown Overvoltage clamp Output stuck to VCC detection Load current limitation Reverse battery protection Electrostatic discharge protection Table 1. SO-16 Description The VND810P-E is a monolithic device designed in STMicroelectronicsTM VIPowerTM M0-3 technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device detects open-load condition both in on-state and off-state. Output shorted to VCC is detected in the off-state. Device automatically turns off in case of ground pin disconnection. Device summary Package SO-16 September 2013 Order codes Tube Tape and reel VND810P-E VND810PTR-E Doc ID 17606 Rev 2 1/28 www.st.com 1 Contents VND810P-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 4 6 2/28 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 17 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 18 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 20 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17 SO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 SO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 SO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 17606 Rev 2 VND810P-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 17606 Rev 2 3/28 List of figures VND810P-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. 4/28 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Maximum turn-off current versus load inductance(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-16 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21 Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal fitting model of a quad channel HSD in SO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-16 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 17606 Rev 2 VND810P-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram Vcc Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE CLAMP 1 GND OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 DRIVER 2 LOGIC OUTPUT2 OVERTEMP. 1 OPEN LOAD ON 1 CURRENT LIMITER 2 INPUT2 OPEN LOAD OFF 1 OPEN LOAD ON 2 STATUS2 OPEN LOAD OFF 2 OVERTEMP. 2 Figure 2. Configuration diagram (top view) 1 VCC 16 N.C. VCC GND OUTPUT 1 INPUT 1 OUTPUT 1 STATUS 1 STATUS 2 OUTPUT 2 OUTPUT 2 VCC INPUT 2 8 VCC Table 2. VCC 9 VCC Suggested connections for unused and not connected pins Connection / pin Status N.C. Output Input Floating X X X X To ground X Doc ID 17606 Rev 2 Through 10K resistor 5/28 Electrical specifications VND810P-E 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol VCC DC supply voltage Value Unit 41 V - VCC Reverse DC supply voltage - 0.3 V - IGND DC reverse ground pin current - 200 mA Internally limited A -6 A DC input current +/- 10 mA ISTAT DC Status current +/- 10 mA VESD Electrostatic discharge (human body model: R=1.5K; C = 100pF) - INPUT - STATUS - OUTPUT - VCC 4000 4000 5000 5000 V V V V EMAX Maximum switching energy (L = 1.5mH; RL = 0; Vbat = 13.5V; Tjstart = 150C; IL = 5A) 26 mJ Power dissipation (per island) at Tlead = 25C 8.3 W Internally limited C IOUT - IOUT IIN Ptot DC output current Reverse DC output current Tj Junction operating temperature Tc Case operating temperature - 40 to 150 Storage temperature - 55 to 150 Tstg 6/28 Parameter Doc ID 17606 Rev 2 C VND810P-E 2.2 Electrical specifications Thermal data Table 4. Thermal data (per island) Symbol Parameter Rthj-lead Thermal resistance junction-lead Rthj-amb Thermal resistance junction-ambient Value Unit 15 C/W 77(1) 57(2) C/W 2 1. When mounted on a standard single-sided FR-4 board with 0.5 cm of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2. When mounted on a standard single-sided FR-4 board with 4 cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2.3 Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40 C < Tj < 150 C, unless otherwise stated. Figure 3. Current and voltage conventions IS VF1 (1) IIN1 ISTAT1 VIN1 IOUT1 OUTPUT 1 STATUS 1 VSTAT1 IIN2 VOUT1 INPUT 2 IOUT2 VIN2 ISTAT2 OUTPUT 2 STATUS 2 VSTAT2 VCC VCC INPUT 1 VOUT2 GND IGND 1. VFn = VCCn - VOUTn during reverse battery condition. Doc ID 17606 Rev 2 7/28 Electrical specifications Table 5. VND810P-E Power output Symbol Parameter VCC(1) Operating supply voltage VUSD(1) VOV(1) RON IS(1) Test conditions Min. Typ. Max. Unit 5.5 13 36 V Undervoltage shutdown 3 4 5.5 V Overvoltage shutdown 36 V IOUT = 1 A; Tj = 25 C IOUT = 1 A; VCC > 8 V On-state resistance Supply current 160 320 m m Off-state; VCC = 13 V; VIN = VOUT = 0 V 12 40 A Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25 C 12 25 A On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A 5 7 mA 0 50 A -75 0 A IL(off1) Off-state output current VIN = VOUT = 0 V IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 C 5 A IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 C 3 A 1. Per device. Table 6. Protections(1) Symbol Parameter Min. Typ. Max. Unit Shutdown temperature 150 175 200 C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload conditions Ilim Current limitation TTSD Vdemag Test conditions C 15 Tj > TTSD VCC = 13 V 5.5 V < VCC < 36 V Turn-off output clamp voltage IOUT = 1 A; L = 6 mH 3.5 5 C 20 s 7.5 A 7.5 A VCC-41 VCC-48 VCC-55 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 8/28 Doc ID 17606 Rev 2 V VND810P-E Electrical specifications Table 7. VCC - output diode Symbol Parameter VF Forward on voltage Table 8. Test conditions Min. Typ. Max. Unit -- -- 0.6 V Min. Typ. Max. Unit -IOUT = 0.5 A; Tj = 150 C Status pin Symbol Parameter Test conditions VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 A CSTAT Status pin Input capacitance Normal operation; VSTAT = 5 V 100 pF 8 V VSCL Status clamp voltage Table 9. Symbol ISTAT = 1mA 6 6.8 ISTAT = - 1mA -0.7 V Switching (VCC = 13V) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 13 from VIN rising edge to VOUT = 1.3 V (see Figure 5) -- 30 -- s td(off) Turn-off delay time RL = 13 from VIN falling edge to VOUT = 11.7 V (see Figure 5) -- 30 -- s -- See Figure 21 -- V/s -- See Figure 22 -- V/s RL = 13 from VOUT = 1.3 V dVOUT/dt(on) Turn-on voltage slope to VOUT = 10.4 V (see Figure 5) dVOUT/dt(off) Turn-off voltage slope Table 10. RL = 13 from VOUT = 11.7 V to VOUT = 1.3 V (see Figure 5) Open-load detection Symbol Parameter IOL Open-load on-state detection threshold VIN = 5 V Open-load on-state detection delay IOUT = 0 A VOL Open-load off-state voltage detection threshold VIN = 0 V tDOL(off) Open-load detection delay at turn-off tDOL(on) Test conditions Doc ID 17606 Rev 2 Min. 20 1.5 Typ. Max. 40 2.5 Unit 80 mA 200 s 3.5 V 1000 s 9/28 Electrical specifications Table 11. VND810P-E Logic inputs Symbol Parameter Test conditions VIL Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage Figure 4. Status timings VIN = 1.25 V Min. Unit 1.25 V A 3.25 V 10 0.5 IIN = 1 mA 6 IIN = -1 mA VINn 6.8 8 V -0.7 V OVER TEMP STATUS TIMING Tj > TTSD VSTATn tSDL tDOL(off) tDOL(on) Switching time waveforms Doc ID 17606 Rev 2 A V VINn VSTATn 10/28 Max. 1 VIN = 3.25 V OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL Figure 5. Typ. tSDL VND810P-E Electrical specifications Table 12. Truth table Conditions Input Output Status Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L Doc ID 17606 Rev 2 11/28 Electrical specifications Table 13. VND810P-E Electrical transient requirements (part 1/3) ISO T/R Test level 7637/1 Test pulse I II III IV Delays and impedance 1 - 25 V - 50 V - 75 V - 100 V 2 ms, 10 2 + 25 V + 50 V + 75 V + 100 V 0.2 ms, 10 3a - 25 V - 50 V - 100 V - 150 V 0.1 s, 50 3b + 25 V + 50 V + 75 V + 100 V 0.1 s, 50 4 -4V -5V -6V -7V 100 ms, 0.01 5 + 26.5 V + 46.5 V + 66.5 V + 86.5 V 400 ms, 2 Table 14. Electrical transient requirements (part 2/3) ISO 7637-1: Test pulse I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Table 15. Class 12/28 Test level results Electrical transient requirements (part 3/3) Contents C All functions of the device performed as designed after exposure to disturbance. E One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 17606 Rev 2 VND810P-E Electrical specifications Figure 6. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined OVERVOLTAGE VCC<VOV VCC > VOV VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn VOUT > VOL OUTPUT VOLTAGEn VOL STATUSn OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn Tj TTSD TR OVERTEMPERATURE INPUTn OUTPUT CURRENTn STATUSn Doc ID 17606 Rev 2 13/28 Electrical specifications VND810P-E 2.4 Electrical characteristics curves Figure 7. Off-state output current Figure 8. IL(off1) (uA) High level input current Iih (uA) 1.6 5 1.44 4.5 Off state Vcc=36V Vin=Vout=0V 1.28 1.12 Vin=3.25V 4 3.5 0.96 3 0.8 2.5 0.64 2 0.48 1.5 0.32 1 0.16 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) Figure 9. 50 75 100 125 150 175 125 150 175 125 150 175 Tc (C) Input clamp voltage Figure 10. Status leakage current Ilstat (uA) Vicl (V) 0.05 8 7.8 Iin=1mA 7.6 0.04 Vstat=5V 7.4 0.03 7.2 7 0.02 6.8 6.6 0.01 6.4 6.2 0 6 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Figure 11. 50 75 100 Tc (C) Tc (C) Status low output voltage Figure 12. Status clamp voltage Vstat (V) Vscl (V) 8 0.8 7.8 0.7 Istat=1.6mA Istat=1mA 7.6 0.6 7.4 0.5 7.2 0.4 7 6.8 0.3 6.6 0.2 6.4 0.1 6.2 0 6 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) 14/28 -25 0 25 50 75 Tc (C) Doc ID 17606 Rev 2 100 VND810P-E Electrical specifications Figure 13. On-state resistance vs Tcase Figure 14. On-state resistance vs VCC Ron (mOhm) Ron (mOhm) 400 300 275 350 300 Iout=0.5A 250 Iout=0.5A Vcc=8V; 13V & 36V Tc= 150C 225 250 200 175 200 150 150 Tc= 25C 125 100 100 Tc= - 40C 50 75 50 0 -50 -25 0 25 50 75 100 125 150 5 175 10 15 20 25 30 35 40 Vcc (V) Tc (C) Figure 15. Open-load on-state detection threshold Iol (mA) Figure 16. Open-load off-state voltage detection threshold Vol (V) 60 5 55 4.5 Vcc=13V Vin=5V 50 Vin=0V 4 45 3.5 40 3 35 2.5 30 2 25 1.5 20 1 15 0.5 0 10 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 100 125 150 175 Tc (C) Tc (C) Figure 17. Input high level Figure 18. Input low level Vih (V) Vil (V) 3.6 2.6 3.4 2.4 3.2 2.2 3 2 2.8 1.8 2.6 1.6 2.4 1.4 2.2 1.2 1 2 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 Tc (C) Tc (C) Doc ID 17606 Rev 2 15/28 Electrical specifications VND810P-E Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown Vov (V) Vhyst (V) 50 1.5 48 1.4 46 1.3 44 1.2 42 1.1 40 1 38 0.9 36 0.8 34 0.7 32 0.6 30 0.5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Figure 21. Turn-on voltage slope 75 100 125 150 175 150 175 Figure 22. Turn-off voltage slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 1000 500 900 450 Vcc=13V Rl=13Ohm 800 Vcc=13V Rl=13Ohm 400 700 350 600 300 500 250 400 200 300 150 200 100 100 50 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) Ilim (A) 10 9 Vcc=13V 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 -25 0 25 50 75 Tc (C) Figure 23. ILIM vs Tcase 100 125 150 175 Tc (C) 16/28 50 Tc (C) Tc (C) Doc ID 17606 Rev 2 100 125 VND810P-E 3 Application information Application information Figure 24. Application schematic +5V +5V +5V VCC Rprot STATUS1 Dld C Rprot INPUT1 OUTPUT1 Rprot STATUS2 Rprot INPUT2 OUTPUT2 GND RGND VGND 3.1 DGND GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: a resistor in the ground line (RGND only) This can be used with any type of load. The following show how to dimension the RGND resistor: Equation 1: RGND 600 mV / IS(on)max Equation 2 RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Doc ID 17606 Rev 2 17/28 Application information VND810P-E Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = (-VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with Equation 1 where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several highside drivers sharing the same RGND. If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1 k) should be inserted in parallel to DGND if the device is driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift not varies if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os: -VCCpeak / Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Example For the following conditions: VCCpeak = - 100 V Ilatchup 20 mA VOHC 4.5 V 5 k Rprot 65 k. 18/28 Doc ID 17606 Rev 2 VND810P-E Application information Recommended values are: Rprot = 10 k 3.4 Open-load detection in off-state Off-state open-load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. No false open-load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL + RPU))RL < VOlmin. 2. No misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in Section 2.3: Electrical characteristics. Figure 25. Open-load detection in off-state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + STATUS R VOL RL GROUND Doc ID 17606 Rev 2 19/28 Application information 3.5 VND810P-E Maximum demagnetization energy (VCC = 13.5 V) Figure 26. Maximum turn-off current versus load inductance(1) I LM AX (A) 10 A B C 1 0,1 1 10 100 L(mH) A = single pulse at TJstart = 150 C B= repetitive pulse at TJstart = 100 C C= repetitive pulse at TJstart = 125 C VIN, IL Demagnetization Demagnetization Demagnetization t 1. Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 20/28 Doc ID 17606 Rev 2 VND810P-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 SO-16 thermal data Figure 27. SO-16 PC board(1) 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 1.6 mm, Cu thickness = 35 m, Copper areas: 0.26 cm2, 4 cm2). Figure 28. Rthj-amb vs PCB copper area in open box free air condition RTH j-am b (C/W) 85 80 75 70 65 60 55 50 45 40 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2) Doc ID 17606 Rev 2 21/28 Package and PCB thermal data VND810P-E Figure 29. Thermal impedance junction ambient single pulse ZTH (C/W) 1000 100 0.26 cm 4 cm 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation 3: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Figure 30. Thermal fitting model of a quad channel HSD in SO-16 Tj_1 Pd1 Tj_2 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 C1 C2 R1 R2 Pd2 T_amb 22/28 Doc ID 17606 Rev 2 2 2 VND810P-E Package and PCB thermal data Table 16. Thermal parameters Area / island (cm2) 0.5 R1 (C/W) 0.35 R2 (C/W) 1.8 R3 (C/W) 4.5 R4 (C/W) 10 R5 (C/W) 16 R6 (C/W) 48 C1 (W.s/C) 0.0001 C2 (W.s/C) 7E-04 C3 (W.s/C) 6E-03 C4 (W.s/C) 0.2 C5 (W.s/C) 0.7 C6 (W.s/C) 2 Doc ID 17606 Rev 2 4 25 4 23/28 Package and packing information VND810P-E 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 SO-16 package information Figure 31. SO-16 package dimensions 24/28 Doc ID 17606 Rev 2 VND810P-E Package and packing information Table 17. SO-16 mechanical data mm. DIM. Min. Typ. A a1 Max. 1.75 0.1 0.2 a2 1.65 b 0.35 0.46 b1 0.19 0.25 C 0.5 c1 45 (typ.) D 9.8 10 E 5.8 6.2 e 1.27 e3 8.89 F 3.8 4.0 G 4.6 5.3 L 0.5 1.27 M 0.62 S 8 Doc ID 17606 Rev 2 25/28 Package and packing information 5.3 VND810P-E SO-16 packing information Figure 32. SO-16 tube shipment (no suffix) B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C A 50 1000 532 3.2 6 0.6 All dimensions are in mm. Figure 33. SO-16 tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 8 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components Empty components pockets saled with cover tape. User direction of feed 26/28 Doc ID 17606 Rev 2 No components 500mm min 500mm min VND810P-E 6 Revision history Revision history Table 18. Document revision history Date Revision Changes 20-Jul-2010 1 Initial release. 19-Sep-2013 2 Updated Disclaimer Doc ID 17606 Rev 2 27/28 VND810P-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 28/28 Doc ID 17606 Rev 2