K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY K9F1208X0C INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Document Title 64M x 8 Bits NAND Flash Memory Revision History Revision No. History Draft Date Remark 0.0 Initial issue. Nov. 10th 2005 Advance 0.1 2.7V part is added July 13th 2006 Advance 0.2 Address of Read 2 is changed (A4~A7 : Don't care -> Fixed "Low" ) Aug. 1st 2006 Advance 0.3 1. Add tRPS/tRCS/tREAS parameter for status read 2. Add nWP timing guide Oct. 12th 2006 Advance 0.4 1. Change from tRPS/tRCS/tREAS to tRPB/tRCB/tREAB parameter for 1.8V device busy state Nov. 14th 2006 Advance 0.5 1. Sequential Row Read is added Nov. 15th 2006 Preliminary 1.0 1. tCRY is changed (50ns+tR(R/B) --> 5us) Dec. 28th 2006 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site. http://www.samsung.com/Products/Semiconductor/ The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 2 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY 64M x 8 Bits NAND Flash Memory PRODUCT LIST Part Number Vcc Range K9F1208R0C-J 1.65V ~ 1.95V K9F1208B0C-P 2.5V ~ 2.9V K9F1208U0C-P Organization PKG Type FBGA x8 TSOP1 TSOP1 2.7V ~ 3.6V K9F1208U0C-J FBGA FEATURES * Voltage Supply - 1.8V Device(K9F1208R0C) : 1.65V ~ 1.95V - 2.7V Device(K9F1208B0C) : 2.5V ~ 2.9V - 3.3V Device(K9F1208U0C) : 2.7V ~ 3.6V * Organization - Memory Cell Array : (64M + 2M) x 8bits - Data Register : (512 + 16) x 8bits * Automatic Program and Erase - Page Program : (512 + 16) x 8bits - Block Erase : (16K + 512)Bytes * Page Read Operation - Page Size : (512 + 16)Bytes - Random Access : 15s(Max.) - Serial Page Access : 42ns(Min.) * Fast Write Cycle Time - Program time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC) - Data Retention : 10 Years * Command Register Operation * Unique ID for Copyright Protection * Package - K9F1208U0C-PCB0/PIB0 : Pb-Free Package 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F1208X0C-JCB0/JIB0: Pb-Free Package 63-Ball FBGA(8.5 x 13 x 1.2mmt) - K9F1208B0C-PCB0/PIB0 : Pb-Free Package 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) GENERAL DESCRIPTION Offered in 64Mx8bits, the K9F1208X0C is 512Mbit with spare 16Mbit capacity. The device is offered in 1.8V, 2.7V and 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200s on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can be read out at 42ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1208X0Cs extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1208X0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 3 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PIN CONFIGURATION (TSOP1) K9F1208X0C-PCB0/PIB0 N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) Unit :mm/Inch 0.10 MAX 0.004 48 - TSOP1 - 1220AF #48 #24 #25 12.40 0.488 MAX 12.00 0.472 +0.003 ( 0.25 ) 0.010 #1 0.008-0.001 0.50 0.0197 0.16 -0.03 +0.075 18.400.10 0.7240.004 0~8 0.45~0.75 0.018~0.030 +0.003 0.005-0.001 0.25 0.010 TYP 1.000.05 0.0390.002 0.125 0.035 +0.07 0.20 -0.03 +0.07 20.000.20 0.7870.008 ( 0.50 ) 0.020 4 1.20 0.047MAX 0.05 0.002 MIN K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PIN CONFIGURATION (FBGA) K9F1208X0C-JCB0/JIB0 1 2 3 4 5 6 N.C N.C N.C N.C A N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 B C D E F NC NC Vcc VccQ I/O5 NC I/O7 G H NC I/O1 NC Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C N.C N.C N.C Top View 5 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY 63-Ball FBGA (measured in millimeters) Top View Bottom View #A1 INDEX MARK(OPTIONAL) 8.500.10 6 8.500.10 0.80 x 9= 7.20 0.80 x 5= 4.00 0.80 5 4 3 2 A B 1 #A1 0.80 (Datum A) A D 2.80 E F G H 63-0.450.05 0.20 M A B 0.350.05 Side View 13.000.10 0.10MAX 0.450.05 6 0.900.10 2.00 13.000.10 0.80 x 7= 5.60 13.000.10 C 0.80 x 11= 8.80 B (Datum B) K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PIN DESCRIPTION Pin Name Pin Function I/O0 ~ I/O7 DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE control during read operation, refer to 'Page read' section of Device operation . RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. DNU DO NOT USE Leave it disconnected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. 7 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM VCC VSS A9 - A25 X-Buffers Latches & Decoders A0 - A7 Y-Buffers Latches & Decoders 512M + 16M Bits NAND Flash ARRAY (512 + 16)Bytes x 131,072 Page Register & S/A A8 Y-Gating Command Command Register I/O Buffers & Latches Control Logic & High Voltage Generator CE RE WE VCC VSS Output Driver Global Buffers I/0 0 I/0 7 CLE ALE WP Figure 2. K9F1208X0C ARRAY ORGANIZATION 1 Block = 32 Pages = (16K + 512) Bytes 128K Pages (=4,096 Blocks) 1st half Page Register 2nd half Page Register (=256 Bytes) (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 Bytes x 32 Pages = (16K + 512) Bytes 1 Device = 528Bytes x 32Pages x 4,096 Blocks = 528 Mbits 8 bits 512Bytes 16 Bytes I/O 0 ~ I/O 7 Page Register 512 Bytes I/O 0 I/O 1 16 Bytes I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 4th Cycle A25 *L *L *L *L *L *L *L NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired. 8 Column Address Row Address (Page Address) K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Product Introduction The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 135,168 NAND structures reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1208X0C. The K9F1208X0C has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1208X0C. Table 1. Command Sets Function 1'st Cycle 2'nd Cycle Read 1 00h/01h(1) - Read 2 50h - Read ID 90h - Reset FFh - Page Program 80h 10h Block Erase 60h D0h Block Protect 1 41h - Block Protect 2 42h - Block Protect 3 43h - Read Status 70h - Read Protection Status 7Ah - Acceptable Command during Busy O O NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. 9 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS K9F1208X0C-XCB0 Temperature Under Bias Rating Symbol 2.7V/3.3V Device VCC -0.6 to + 2.45 -0.6 to + 4.6 VIN -0.6 to + 2.45 -0.6 to + 4.6 VI/O -0.6 to Vcc + 0.3 (< 2.45V) V -0.6 to Vcc + 0.3 (< 4.6V) -10 to +125 TBIAS K9F1208X0C-XIB0 C -40 to +125 K9F1208X0C-XCB0 Storage Temperature Unit 1.8V Device TSTG -65 to +150 C IOS 5 mA K9F1208X0C-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND at the condision of K9F1208X0C-XCB0 : TA=0 to 70C or K9F1208X0C-XIB0 : TA=-40 to 85C) Parameter Supply Voltage 2.7V(K9F1208B0C) 1.8V(K9F1208R0C) Symbol 3.3V(K9F1208U0C) Unit Min Typ. Max Min Typ. Max Min Typ. Max VCC 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 V VSS 0 0 0 0 0 0 0 0 0 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.) K9F1208X0C Parameter Symbol Test Conditions 1.8V 2.7V Min Typ Max Operating Current Sequential Read ICC1 Program ICC2 Erase ICC3 tRC=42ns, CE=VIL, IOUT=0mA Min Uni t 3.3V Typ Max Min Typ Max - 8 20 - 10 20 - 10 20 - - 8 20 - 10 20 - 10 20 - - 8 20 - 10 20 - 10 20 Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1 - - 1 Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50 - 10 50 10 Input Leakage Current ILI VIN=0 to Vcc(max) - - 10 - - 10 - - Output Leakage Current ILO VOUT=0 to Vcc(max) - - 10 - - 10 - - 10 2.0 - VCC +0. 3 Input High Voltage VIH Input Low Voltage, All inputs VIL VCC - VCC +0.3 VCC - 0.4 -0.3 - - - - 0.1 3 4 - -0.3 Output High Voltage Level VOH K9F1208R0C: IOH=-100A K9F1208B0C: IOH=-100A K9F1208U0C: IOH=-400A Output Low Voltage Level VOL K9F1208R0C: IOL=100A K9F1208B0C: IOL=100A K9F1208U0C: IOL=2.1mA Output Low Current(R/B) - -0.4 IOL(R/B) VOL=0.4V Notes : 1. Typical values are measured at Vcc=3.3V, TA=25C. And not 100% tested. 10 VCC -0.1 -0.4 - VCC +0.3 - 0.5 -0.3 - 0.8 - - 2.4 - - - - 0.4 - - 0.4 3 4 - 8 10 - VCC -0.4 mA A V mA K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY VALID BLOCK Parameter Valid Block Number Symbol Min Typ. Max Unit NVB 4,026 - 4,096 Blocks NOTE : 1. The K9F1208X0C may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC. 3. Minimum 1,004 valid blocks are guaranteed for each contiguous 128Mb memory space. AC TEST CONDITION (K9F1208X0C-XCB0 :TA=0 to 70C, K9F1208X0C-XIB0:TA=-40 to 85C). Value Parameter Input Pulse Levels K9F1208R0C K9F1208B0C K9F1208U0C 0V to VCC 0V to Vcc 0.4V to 2.4V Input Rise and Fall Times Input and Output Timing Levels 5ns 5ns 5ns VCC/2 Vcc/2 1.5V K9F1208R0C:Output Load (Vcc:1.8V +/-10%) K9F1208B0C:Output Load (Vcc:2.7V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF K9F1208U0C:Output Load (Vcc:3.3V +/-10%) K9F1208U0C:Output Load (Vcc:3.0V +/-10%) - - 1 TTL GATE and CL=100pF 1 TTL GATE and CL=50pF CAPACITANCE(TA=25C, VCC=1.8V/2.7V/3.3V, f=1.0MHz) Symbol Test Condition Min Max Unit Input/Output Capacitance Item CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF NOTE : Capacitance is periodically sampled and not 100% tested. MODE SELECTION CLE ALE CE H L L H H L L WE RE WP Mode L H X L H X L L H H H L H H L L H H L L L H X Data Output L L L H H X During Read (Busy) X X X X X H During Program (Busy) X X X X X H During Erase (Busy) X X(1) X X X L Write Protect X X H X X Read Mode Command Input Address Input (4 clocks) Write Mode Command Input Address Input (4 clocks) Data Input 0V/VCC(2) Stand-by NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. 11 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Program / Erase Characteristics Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol Min Typ Max Unit tPROG(1) - 200 500 s - - 1 cycle - - 2 cycle - 2 3 ms Nop tBERS NOTE NOTE: 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25'C AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT Parameter Symbol Min Max Unit CLE setup Time tCLS 21 - ns CLE Hold Time tCLH 5 - ns CE setup Time tCS 31 - ns CE Hold Time tCH 5 - ns tWP(1) 21 - ns ALE setup Time tALS 21 - ns ALE Hold Time tALH 5 - ns Data setup Time tDS 20 - ns Data Hold Time tDH 5 - ns Write Cycle Time tWC 42 - ns WE High Hold Time tWH 15 - ns WE Pulse Width NOTE: The transition of the corresponding control pins must occur only once while WE is held low. 12 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY AC CHARACTERISTICS FOR OPERATION Symbol Min Max Unit Data Transfer from Cell to Register Parameter tR - 15 s ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 21 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 42 - ns RE Access Time tREA - 30 ns CE Access Time tCEA - 35 ns RE High to Output Hi-Z tRHZ - 30 ns CE High to Output Hi-Z tCHZ - 20 ns CE High to ALE or CLE Don't Care tCSD 10 - ns RE or CE High to Output hold tOH 15 - ns RE High Hold Time tREH 15 - ns tIR 0 - ns WE High to RE Low tWHR 60 - ns Device resetting time(Read/Program/Erase) tRST - 5/10/500(1) s RE Pulse Width during Busy State tRPB(2) 35 - ns Read Cycle Time during Busy State tRCB(2) 50 - ns - 40 ns Uni Output Hi-Z to RE Low RE Access Time during Busy State tREAB (2) Parameter K9F1208X0C-P only Symbol Min Max Last RE High to Busy(at sequential read) tRB - 100 ns CE High to Ready(in case of interception by CE at read) tCRY - 5 s CE High Hold Time(at the last serial read)(4) tCEH 100 - ns NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. This parameter (tRPB/tRCB/tREAB) must be used only for 1.8V device. 3. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 13 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC. Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address No Create (or update) Initial Invalid Block(s) Table * Check "FFh" at the column address 517 of the 1st and 2nd page in the block Check "FFh" ? Yes No Last Block ? Yes End Figure 3. Flow chart to create initial invalid block table. 14 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed blocks. Failure Mode Write Read ECC Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Single Bit Failure Verify ECC -> ECC Correction : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bits detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? * Program Error No Yes No I/O 0 = 0 ? Yes Program Completed * 15 : If program operation results in an error, map out the block including the page in error and copy the target data to another block. K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Read Data Read Status Register ECC Generation No I/O 6 = 1 ? or R/B = 1 ? Reclaim the Error * No Verify ECC Yes Yes Erase Error No Page Read Completed I/O 0 = 0 ? Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement 1st (n-1)th nth { Block A 2 an error occurs. (page) 1st (n-1)th nth Buffer memory of the controller. { Block B 1 (page) * Step1. When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2. Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B') * Step3. Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block 'B'. * Step4. Do not further erase Block 'A' by creating an 'invalid Block' table or other appropriate scheme. 16 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Pointer Operation of K9F1208X0C Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h' command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from 'B' area, '01h' command must be inputted right before '80h' command is written. Table 2. Destination of the pointer Command Pointer position Area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(A) 2nd half array(B) spare array(C) "A" area (00h plane) "B" area (01h plane) "C" area (50h plane) 256 Bytes 256 Bytes 16 Bytes "A" "B" "C" Internal Page Register Pointer select commnad (00h, 01h, 50h) Pointer Figure 4. Block Diagram of Pointer Operation (1) Command input sequence for programming 'A' area The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h Address / Data input 10h 00h 'A','B','C' area can be programmed. It depends on how many data are inputted. 80h 10h '00h' command can be omitted. (2) Command input sequence for programming 'B' area The address pointer is set to 'B' area(256~511), and will be reset to 'A' area after every program operation is executed. Address / Data input 01h 80h Address / Data input 10h 01h 'B', 'C' area can be programmed. It depends on how many data are inputted. 80h 10h '01h' command must be rewritten before every program operation (3) Command input sequence for programming 'C' area The address pointer is set to 'C' area(512~527), and sustained Address / Data input 50h 80h Address / Data input 10h 50h Only 'C' area can be programmed. 80h '50h' command can be omitted. 17 10h K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY System Interface Using CE don't-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption. Figure 5. Program Operation with CE don't-care. CLE CE don't-care WE CE ALE I/OX 80h Start Add.(4Cycle) Data Input tCH tCS Data Input 10h tCEA CE CE tREA RE tWP WE I/OX out Figure 6. Read Operation with CE don't-care. CLE On K9F1208X0C-P CE must be held low during tR CE don't-care CE RE ALE tR R/B WE I/OX 00h Data Output(sequential) Start Add.(4Cycle) 18 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY * Command Latch Cycle CLE tCLS tCLH tCS tCH CE tWP WE tALH tALS ALE tDH tDS Command I/OX * Address Latch Cycle tCLS CLE tCS tWC tWC tWC CE tWP tWP tWP tWP WE tWH tALH tALS tALS tWH tALH tWH tALH tALS tALH tALS ALE tDS I/OX tDH A0~A7 tDS tDH A9~A16 19 tDS tDH A17~A24 tDS tDH A25~A26 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY * Input Data Latch Cycle tCLH CLE tCH CE tWC ALE tWP tALS tWP tWP WE tWH tDH tDS tDH tDS tDH tDS I/Ox DIN n DIN 1 DIN 0 * Serial access Cycle after Read(CLE=L, WE=H, ALE=L) tRC CE tCHZ* tREH tREA tREA tOH tREA RE tRHZ* tRHZ* I/Ox Dout Dout tOH Dout tRR R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 20 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Status Read Cycle (During Ready State) tCLR CLE tCLS tCLH tCS CE tCH tWP WE tCEA tCHZ tOH tWHR tRP RE tDH tDS I/OX tRHZ tREA tIR tOH Status Output 70h/7Ah R/B Status Read Cycle (During Busy State) tCLR CLE tCLS tCLH tCS CE tCH tWP WE tCEA tCHZ tOH tWHR tRPB RE tDS I/OX tDH tIR tREAB tRHZ tOH Status Output 70h/7Ah R/B 21 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY READ1 OPERATION (READ ONE PAGE) CLE 1) CE tCEH On K9F1208X0C-P CE must be held low during tR tCHZ tOH tWC WE tWB ALE tCRY tAR tR tRHZ tOH tRC N Address RE 00h or 01h A0 ~ A7 A9 ~ A16 Column Address A17 ~ A24 A25 Dout N Dout N+1 Dout N+2 Page(Row) Address I/OX tRR Busy X8 device : m = 528 , Read CMD = 00h or 01h NOTES : 1) is only valid on K9F1208X0C-P Read1 Operation (Intercepted by CE) CLE On K9F1208U0C-P CE must be held low during tR CE WE tWB ALE tCHZ tOH tAR tRC tR RE A0 ~ A7 Column Address R/B A9 ~ A16 A17 ~ A24 A25 Page(Row) Address Busy 00h or 01h tRR I/OX 22 1) tRB 1) R/B Dout m Dout N Dout N+1 Dout N+2 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Read2 Operation (Read One Page) CLE On K9F1208X0C-P CE must be held low during tR CE WE tR tWB tAR ALE tRR I/OX 50h A0 ~ A7 A9 ~ A16 A17 ~ A24 Dout n+M A25 R/B RE n+m Selected Row M Address A0~A3 : Valid Address A4~A7 : Dont care 16 512 Start address M Sequential Row Read Operation (Within a Block) CLE CE WE A25 Dout N Dout N+1 Busy Dout 0 Dout 1 Dout 527 R/B Ready Busy Dout 527 A0 ~ A7 A9 ~ A16 A17 ~ A24 00h I/OX RE ALE M M+1 N Output 23 Output K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Page Program Operation CLE CE tWC tWC tWC WE tWB tPROG ALE I/OX A0 ~ A7 A9 ~ A16 A17 ~ A24 80h Sequential Data Column Input Command Address A25 Page(Row) Address RE Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input R/B 70h I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program Block Erase Operation (Erase One Block) CLE CE tWC WE tWB tBERS ALE RE I/OX 60h A9 ~ A16 A17 ~ A24 A25 DOh 70h I/O 0 Page(Row) Address Busy R/B Erase Setup Command Erase Command 24 Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Read ID Operation CLE CE WE ALE RE tREA I/OX 90h Read ID Command 00h Address. 1cycle ECh Maker Code Device Code ID Defintition Table 90 ID : Access command = 90H Value 1st Byte 2nd Byte 3rd Byte 4th Byte ECh 76h 5Ah 3Fh 76h Description Maker Code Device Code Don't support Copy Back Operation Don't support Multi Plane Operation 25 5Ah 3Fh K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 15s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. CE must be held low while in busy for K9F1208X0C-PXB0, while CE is don't-care with K9F1208X0C-JXB0. If CE goes high before the device returns to Ready, the random read operation is interrupted and Busy returns to Ready as the defined by tCRY. Since the operation was aborted, the serial page read does not output valid data. Once the data in a page is loaded into the registers, they may be read out in 42ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512 to 527 bytes may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 7 to 10 show typical sequence and timings for each read operation. Sequential Row Read is available only on K9F1208X0C-P : After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read operation. 26 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 7. Read1 Operation CLE On K9F1208X0C-P CE must be held low during tR CE WE ALE tR R/B RE I/O0~7 00h Data Output(Sequential) Start Add.(4Cycle) A0 ~ A7 & A9 ~ A25 (00h Command) 1) (01h Command) 1st half array Main array Data Field Spare Field 2st half array Data Field Spare Field NOTE : 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 27 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 8. Read2 Operation CLE On K9F1208X0C-P CE must be held low during tR CE WE ALE tR R/B RE I/OX 50h Data Output(Sequential) Start Add.(4Cycle) A0 ~ A3 & A9 ~ A25 (A4 ~ A7 : Fixed "Low") Spare Field Main array Data Field 28 Spare Field K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY I/OX tR tR R/B 00h Start Add.(4Cycle) 01h A0 ~ A7 & A9 ~ A25 Figure 9. Sequential Row Read1 Operation (only for K9F1208X0C-P valid within a block) Data Output 1st Data Output Data Output 2nd (528 Byte) Nth (528 Byte) ( 01h Command) ( 00h Command) 1st half array tR 2nd half array 1st half array 2nd half array 1st 2nd Nth Block Data Field 1st 2nd Nth Data Field Spare Field Spare Field The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. I/OX tR tR R/B 50h Start Add.(4Cycle) A0 ~ A3 & A9 ~ A25 Figure 10. Sequential Row Read2 Operation (only for K9F1208X0C-P valid within a block) Data Output 1st Data Output Data Output 2nd (16Byte) Nth (16Byte) (A4 ~ A7 : Don't Care) 1st Block Nth Data Field Spare Field 29 tR K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 byte, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure11. Program Operation tPROG R/B I/O0~7 80h Address & Data Input 10h 70h I/O0 Pass A0 ~ A7 & A9 ~ A25 528 Bytes Data Fail BLOCK ERASE The Erase operation is done on a block(16K Bytes) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence. Figure 12. Block Erase Operation tBERS R/B I/OX 60h Address Input(3Cycle) 70h D0h I/O0 Block Add. : A14 ~ A25 Fail 30 Pass K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY BLOCK PROTECT Each block is protected from programming and erasing, controlled by the protect flag written in a specified area in the block. Block Proctect opreation is initiated by wirting 4xh-80h-10h to the command register along with four address cycles. Only address A14 to A26 is valid while A0 to A13 is fixed as 00h. The data must not be loaded. Once the Block Protect opreation starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of Page Program operation for protecting a block by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while Block Protect operation is in progress. But, if Reset command is inputted while Block Protect operation is in progress, the block will not be guaranteed whether it is protected or not. When the Page Program operation for protecting a block is completed, the Write Status Bit(I/O 0) may be checked(Figure 13). The command register remains in Read Status command mode until another valid command is written to the command register. When programming is prohibited by 41h command, the protect flag and the data of protected block can be erased by Block Erase operation. Once erasing is prohibited by 42h/43h command, the protect flag and the data of protected block can not be erased. If 80h-10h is written to command register along with four address cycles at the program protected block or at the program/erase protected block, and if 60h-D0h is written to command register along with three address cycles at the program/erase protected block, the R/B pin changes to low for tR. The Block Protect operation must not be excuted on the aleady protected block. The Block Protect operation will be aborted by Reset command(FFh). The Block Protect operation can only be used from first block to 200th block. The device contains a Status Register which may be used to read out the state of the selected block. After writing 7Ah command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last(Figure 14). Refer to table 3 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Three commands are provided to protect the block. 41h : Programming is prohibited 42h : Erasing is prohibited 43h : Both programming and erasing are prohibited Figure 13. Block Protect Operation tPROG R/B I/OX 4Xh 80h Address Input(4Cycle) 10h 70h A0 ~ A7 : 00h Fix A9 ~ A13 : 00h Fix A14 ~ A25 : 0 to 4095 I/O0 Fail 31 Pass FFh FFh K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 14. Read Block Status CLE ALE WE I/OX 00h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 7Ah Status A0~7 : 00h, A9~13 : 0 fixed, A14~25 : 0 to 4095 RE tR R/B Table 3. Status Register Definition for 7Ah Command I/O Status I/O 0 Programming Protect Not protected : "0" Protected : "1" I/O 1 Erasing Protect Not protected : "0" Protected : "1" I/O 2 Not use Don't -cared I/O 3 Not Use Don't -cared I/O 4 Not Use Don't -cared I/O 5 Not Use I/O 6 Device Operation I/O 7 Write Protect Definition Don't -cared Busy: "0" Protected : "0" NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. 32 Ready : "1" Not protect : "1" K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. Table 4. Status Register Definition for 70h Command I/O Page Program Block Erase Read I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" Definition I/O 1 Not use Not use Not use Don't -cared I/O 2 Not use Not use Not use Don't -cared I/O 3 Not Use Not Use Not Use Don't -cared I/O 4 Not Use Not Use Not Use Don't -cared Don't -cared I/O 5 Not Use Not Use Not Use I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" I/O 7 Write Protect Write Protect Write Protect Protected : "0" Fail : "1" Ready : "1" Not Protected : "1" NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. . Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 15 shows the operation sequence. Figure 15. Read ID Operation CLE tCEA CE WE tAR ALE RE I/O0~7 tWHR 90h tREA 00h ECh Address. 1cycle Maker code 33 Device Code 5Ah 3Fh Device Device Code K9F1208R0C 36h K9F1208B0C 76h K9F1208U0C 76h K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 16 below. Figure 16. RESET Operation tRST R/B I/OX FFh Table 5. Device Status Operation mode After Power-up After Reset 00h Command is latched Waiting for next command 34 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be determined by the following guidance. Rp ibusy 1.8V device - VOL : 0.1V, VOH : Vcc-0.1V 2.7V device - VOL : 0.4V, VOH : VccQ-0.4V 3.3V device - VOL : 0.4V, VOH : 2.4V VCC Ready Vcc R/B open drain output VOH VOL : 0.4V, VOH : 2.4V CL VOL Busy tf GND Device 35 tr K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Ibusy 300n 200n 1.7 2m tr 100n 3m 30 0.85 120 90 60 0.57 1.7 tf 1K 1.7 1.7 2K 3K Rp(ohm) Ibusy [A] tr,tf [s] @ Vcc = 1.8V, Ta = 25C , CL = 30pF 1m 0.43 1.7 4K 300n 3m 2.3 Ibusy 200n 100n 2m 1.1 30 2.3 tr tf 1K 90 60 0.75 2.3 2.3 2K Ibusy [A] tr,tf [s] @ Vcc = 2.7V, Ta = 25C , CL = 30pF 120 1m 2.3 0.55 4K 3K Rp(ohm) @ Vcc = 3.3V, Ta = 25C , CL = 100pF tr,tf [s] Ibusy 300n 300 3m 1.2 200 0.8 2m 3.6 tf 3.6 3.6 3.6 1K 2K 3K 4K 200n tr 100n 100 0.6 Rp(ohm) Figure 17. Rp vs tr ,tf & Rp vs ibusy Rp value guidance Rp(min, 1.8V part) = Rp(min, 2.7V part) = Rp(min, 3.3V part) = 1.85V VCC(Max.) - VOL(Max.) IOL + IL = 2.5V VCC(Max.) - VOL(Max.) IOL + IL = 3mA + IL 3.2V VCC(Max.) - VOL(Max.) IOL + IL 3mA + IL = where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr 36 8mA + IL 1m Ibusy [A] 400 2.4 K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100s is required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software protection. Figure 18. AC Waveforms for Power Transition 1.8V device : ~ 1.5V 2.7V device : ~ 2.0V 3.3V device : ~ 2.5V VCC High WP WE 100s 37 1.8V device : ~ 1.5V 2.7V device : ~ 2.0V 3.3V device : ~ 2.5V K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY WP AC Timing guide Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: Figure A-1. Program Operation 1. Enable Mode WE I/O 80h 10h WP R/B tww(min.100ns) 2. Disable Mode WE I/O 80h 10h WP R/B tww(min.100ns) Figure A-2. Erase Operation 1. Enable Mode WE I/O 60h D0h WP R/B tww(min.100ns) 2. Disable Mode WE I/O 60h D0h WP R/B tww(min.100ns) 38