FLASH MEMORY
1
K9F1208R0C
K9F1208U0C K9F1208B0C
K9F1208X0C
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
Document Title
64M x 8 Bits NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUN G Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
0.1
0.2
0.3
0.4
0.5
1.0
Remark
Advance
Advance
Advance
Advance
Advance
Preliminary
Final
History
Initial issue.
2.7V part is added
Address of Read 2 is changed (A4~A7 : Don’t care -> Fixed "Low" )
1. Add tRPS/tRCS/tREAS parameter for status read
2. Add nWP timing guide
1. Change from tRPS/tRCS/tREAS to tRPB/tRCB/tREAB parameter for
1.8V device busy state
1. Sequential Row Read is added
1. tCRY is changed (50ns+tR(R/B) --> 5us)
Draft Date
Nov. 10th 2005
July 13th 2006
Aug. 1st 2006
Oct. 12th 2006
Nov. 14th 2006
Nov. 15th 2006
Dec. 28th 2006
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
GENERAL DESCRIPTION
FEATURES
• Voltage Supply
- 1.8V Device(K9F1208R0C) : 1.65V ~ 1.95V
- 2.7V Device(K9F1208B0C) : 2.5V ~ 2.9V
- 3.3V Device(K9F1208U0C) : 2.7V ~ 3.6V
• Organization
- Memory Cell Array : (64M + 2M) x 8bits
- Data Register : (512 + 16) x 8bits
• Automatic Program and Erase
- Page Program : (512 + 16) x 8bits
- Block Erase : (16K + 512)Bytes
• Page Read Operation
- Page Size : (512 + 16)Bytes
- Random Access : 15µs(Max.)
- Serial Page Access : 42ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
64M x 8 Bits NAND Flash Memory
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
(with 1bit/512Byte ECC)
- Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package
- K9F1208U0C-PCB0/PIB0 : Pb-Free Package
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1208X0C-JCB0/JIB0: Pb-Free Package
63-Ball FBGA(8.5 x 13 x 1.2mmt)
- K9F1208B0C-PCB0/PIB0 : Pb-Free Package
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
Offered in 64Mx8bits, the K9F1208X0C is 512Mbit with spare 16Mbit capacity. The device is offered in 1.8V, 2.7V and 3.3V Vcc. Its
NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in
typical 200µs on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can
be read out at 42ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input.
The on-chip write control au tomates all program and erase functi ons including pulse repetition, wher e required, and internal verifica-
tion and margining of data. Even the write-intensive systems can take advantage of the K9F1208X0C′s extended reliability of 100K
program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F1208X0C is an optimum solution for large nonvolatile stor age applications such as solid state file stor age and other portable
applications requiring non-volatility.
PRODUCT LIST
Part Number Vcc Range Organization PKG Type
K9F1208R0C-J 1.65V ~ 1.95V
x8
FBGA
K9F1208B0C-P 2.5V ~ 2.9V TSOP1
K9F1208U0C-P 2.7V ~ 3.6V TSOP1
K9F1208U0C-J FBGA
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
PIN CONFIGURATION (TSOP1)
K9F1208X0C-PCB0/PIB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.16+0.07
-0.03
0.008+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40MAX
12.00
0.472
0.10
0.004 MAX
0.25
0.010
()
0.039±0.002
1.00±0.05 0.002
0.05 MIN
0.047
1.20 MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8°
0.010
0.25 TYP
0.125+0.075
0.035
0.005+0.003
-0.001
0.50
0.020
()
0.20+0.07
-0.03
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
K9F1208X0C-JCB0/JIB0
R/B/WE/CEVssALE/WP
/RE CLE
NCNC
NC NC Vcc
NCNC I/O0
I/O1NC NC VccQ I/O5 I/O7
VssI/O6I/O4I/O3I/O2Vss
NC
NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC NC NC
NC
NC
NC
NC
NC
N.C
N.C N.C
N.C
N.C N.C
N.C
N.C
N.C N.C
N.CN.C
N.C N.C
N.C
PIN CONFIGURATION (FBGA)
3456 1 2
A
B
C
D
G
E
F
H
Top View
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
8.50±0.10
#A1
Side View
Top View
63-Ball FBGA (measured in millimeters)
0.90±0.10
0.45±0.05
4321
A
B
C
D
G
Bottom View
13.00±0.10
63-∅0.45±0.05
0.80 x 7= 5.60
13.00±0.10
0.80 x 5= 4.00
0.80
0.35±0.05
0.10MAX
B
A
2.80
2.00
8.50±0.10
(Datum B)
(Datum A)
0.20
M
A B
∅
0.80
0.80 x 1 1 = 8.80
0.80 x 9= 7.20
65
13.00±0.10
E
F
H
#A1 INDEX MARK(OPTIONA L)
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
PIN DESCRIPTION
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
Pin Name Pin Function
I/O0 ~ I/O7DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command reg ister. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .
RE READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
Vcc POWER
VCC is the power supply for device.
Vss GROUND
N.C NO CONNECTION
Lead is not internally connected.
DNU DO NOT USE
Leave it disconnected.
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
512Bytes 16 Bytes
Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM
Figure 2. K9F1208X0C ARRAY ORGANIZATION
VCC
X-Buffers 512M + 16M Bits
Command
NAND Flash
ARRAY
(512 + 16)Bytes x 131,072
Y-Gating
Page Register & S/A
I/O Buffers & Latches
Y-Buffers
Control Logic
Global Buffers Output
Driver
VSS
A9 - A25
A0 - A7
Command
CE
RE
WE
WP
I/0 0
I/0 7
VCC
VSS
A8
1st half Page Register
(=256 Bytes) 2nd half Page Register
(=256 Bytes)
128K Pages
(=4,096 Blocks)
512 Bytes
8 bits
16 Bytes
1 Block = 32 Pages
= (16K + 512) Bytes
I/O 0 ~ I/O 7
1 Page = 528 Bytes
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Bytes
1 Device = 528Bytes x 32Pages x 4,096 Blocks
= 528 Mbits
Column Address
Row Address
(Page Address)
Page Register
CLE ALE
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the st arting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reg uired.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle A0A1A2A3A4A5A6A7
2nd Cycle A9A10 A11 A12 A13 A14 A15 A16
3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24
4th Cycle A25 *L *L *L *L *L *L *L
Register
& High Voltage
Generator
Latches
& Decoders
Latches
& Decoders
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
Product Introduction
The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-bytes data register is conn ected to memory cell ar rays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 135,168 NAND structures reside in a block. The
program and read operations ar e executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 4,096 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F1208X0C.
The K9F1208X0C has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Addr ess
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires
26 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-
ation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9F1208X0C.
Table 1. Command Sets
NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h)
on the next cycle.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Function 1’st Cycle 2’nd Cycle Acceptable Command
during Busy
Read 1 00h/01h(1) -
Read 2 50h -
Read ID 90h -
Reset FFh - O
Page Program 80h 10h
Block Erase 60h D0h
Block Protect 1 41h -
Block Protect 2 42h -
Block Protect 3 43h -
Read Status 70h - O
Read Protection Status 7Ah -
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
DC AND OPERAT ING CHARACTERISTICS (Recommended operating conditions otherwise noted.)
Notes :
1. Typical values are measured at Vcc=3.3 V, TA=25°C. And not 100% tested.
Parameter Symbol Test Conditions
K9F1208X0C Uni
t
1.8V 2.7V 3.3V
Min Typ Max Min Typ Max Min Typ Max
Operating
Current
Sequential
Read ICC1 tRC=42ns, CE=VIL,
IOUT=0mA - 8 20 - 10 20 - 10 20
mA
Program ICC2 - - 8 20 - 10 20 - 10 20
Erase ICC3 - - 8 20 - 10 20 - 10 20
Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC --1 - -1--1
Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC -1050 -1050 -1050
µA
Input Leakage Current ILI VIN=0 to Vcc(max) --±10 - - ±10 - - ±10
Output Leakage Current ILO VOUT=0 to Vcc(max) --±10 - - ±10 - - ±10
Input High Voltage VIH VCC
-0.4 -VCC
+0.3 VCC
-0.4 -VCC
+0.3 2.0 - VCC
+0.
3
V
Input Low Voltage, All inputs VIL - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8
Output High Voltage Level VOH
K9F1208R0C: IOH=-100µA
K9F1208B0C: IOH=-100µA
K9F1208U0C: IOH=-400µA
VCC
-0.1 --
VCC
-0.4 --2.4--
Output Low Voltage Level VOL
K9F1208R0C: IOL=100µA
K9F1208B0C: IOL=100µA
K9F1208U0C: IOL=2.1mA - - 0.1 - - 0.4 - - 0.4
Output Low Current(R/B)IOL(R/B)V
OL=0.4V 34 - 3 4- 810-mA
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND at the condision of K9F1208X0C-XCB0 : TA=0 to 70°C or K9F1208X0C-XIB0 : TA=-40 to 85°C)
Parameter Symbol 1.8V(K9F1208R0C) 2.7V(K9F1208B0C) 3.3V(K9F1208U0C) Unit
Min Typ. Max Min Typ. Max Min Typ. Max
Supply Voltage VCC 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 V
VSS 000000000V
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.6V on input/ output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
1.8V Device 2.7V/3.3V Device
Voltage on any pin relative to VSS
VCC -0.6 to + 2.45 -0.6 to + 4.6
V
VIN -0.6 to + 2.45 -0.6 to + 4.6
VI/O -0.6 to Vcc + 0.3 (< 2.45V) -0.6 to Vcc + 0.3 (< 4.6V)
Temperature Under
Bias K9F1208X0C-XCB0 TBIAS -10 to +125 °C
K9F1208X0C-XIB0 -40 to +125
Storage Temperature K9F1208X0C-XCB0 TSTG -65 to +150 °C
K9F1208X0C-XIB0
Short Circuit Current IOS 5mA
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
CAPACITANCE(TA=25°C, VCC=1.8V/2.7V/3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Condition Min Max Unit
Input/Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF
VALID BLOCK
NOTE :
1. The K9F1208X0C may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate manageme nt of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
3. Minimum 1,004 valid blocks are guaranteed for each contiguous 128Mb memory space.
Parameter Symbol Min Typ. Max Unit
Valid Block Number NVB 4,026 - 4,096 Blocks
AC TEST CONDITION
(K9F1208X0C-XCB0 :TA=0 to 70°C, K9F1208X0C-XIB0:TA=-40 to 85°C).
Parameter Value
K9F1208R0C K9F1208B0C K9F1208U0C
Input Pulse Levels 0V to VCC 0V to Vcc 0.4V to 2.4V
Input Rise and Fall Times 5ns 5ns 5ns
Input and Output Timing Levels VCC/2 Vcc/2 1.5V
K9F1208R0C:Output Load (Vcc:1.8V +/-10%)
K9F1208B0C:Output Load (Vcc:2.7V +/-10%)
K9F1208U0C:Output Load (Vcc:3.3V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and
CL=100pF
K9F1208U0C:Output Load (Vcc:3.0V +/-10%) - - 1 TTL GATE and CL=50pF
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE ALE CE WE RE WP Mode
HLL HX
Read Mode Command Input
L H L H X Address Input (4 clocks)
HLL HH
Write Mode Command Input
L H L H H Address Input (4 clocks)
L L L H H Data Input
L L L H X Data Output
L L L H H X During Read (Busy)
X X X X X H During Program (Busy)
X X X X X H During Erase (Busy)
XX(1) X X X L Write Protect
XXHXX
0V/VCC(2) Stand-by
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
Program / Erase Characteristics
NOTE NOTE: 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C
Parameter Symbol Min Typ Max Unit
Program Time tPROG(1) - 200 500 µs
Number of Partial Program Cycles
in the Same Page Main Array Nop --1cycle
Spare Array - - 2 cycle
Block Erase Time tBERS -23ms
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
NOTE: The transition of the corresponding control pins must occur only once while WE is held low.
Parameter Symbol Min Max Unit
CLE setup Time tCLS 21 - ns
CLE Hold Time tCLH 5-ns
CE setup Time tCS 31 - ns
CE Hold Time tCH 5-ns
WE Pulse Width tWP(1) 21 - ns
ALE setup Time tALS 21 - ns
ALE Hold Time tALH 5-ns
Data setup Time tDS 20 - ns
Data Hold Time tDH 5-ns
Write Cycle Time tWC 42 - ns
WE High Hold Time tWH 15 - ns
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
AC CHARACTERISTICS FOR OPERATION
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. This parameter (tRPB/tRCB/tREAB) must be used only for 1.8V device.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
Parameter Symbol Min Max Unit
Data Transfer from Cell to Register tR-15µs
ALE to RE Delay tAR 10 - ns
CLE to RE Delay tCLR 10 - ns
Ready to RE Low tRR 20 - ns
RE Pulse Width tRP 21 - ns
WE High to Busy tWB -100ns
Read Cycle Time tRC 42 - ns
RE Access Time tREA -30ns
CE Access Time tCEA -35ns
RE High to Output Hi-Z tRHZ -30ns
CE High to Output Hi-Z tCHZ -20ns
CE High to ALE or CLE Don’t Care tCSD 10 - ns
RE or CE High to Output hold tOH 15 - ns
RE High Hold Time tREH 15 - ns
Output Hi-Z to RE Low tIR 0-ns
WE High to RE Low tWHR 60 - ns
Device resetting time(Read/Program/Erase) tRST -5/10/500(1) µs
RE Pulse Width during Busy State tRPB(2) 35 - ns
Read Cycle Time during Busy State tRCB(2) 50 - ns
RE Access Time during Busy State tREAB(2) -40ns
Parameter Symbol Min Max Uni
K9F1208X0C-P only
Last RE High to Busy(at sequential read) tRB -100ns
CE High to Ready(in case of interception by CE at read) tCRY -5µs
CE High Hold Time(at the last serial read)(4) tCEH 100 - ns
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
NAND Flash Technical Notes
Identifying Initial Invalid Block(s)
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor . The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of
every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable
in most cases, it is impossible to recover the information once it has been erased . Therefore, the system must be able to recognize
the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug-
gested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
*Check "FFh" at the column address 517
Figure 3. Flow chart to create initial invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update) No
Initial Invalid Block(s) Table
of the 1st and 2nd page in the block
FLASH MEMORY
15
K9F1208R0C
K9F1208U0C K9F1208B0C
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Program Completed
or R/B = 1 ?
Program Er ror
Yes
No
Yes
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block
failure rate.The following p ossible failure modes should be considered t o implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an
erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC
must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should
be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those
reclaimed blocks.
Failure Mode Detection and Countermeasure sequence
Write Erase Failure Status Read after Erase --> Block Replacement
Program Failure Status Read after Program --> Block Replacement
Read Single Bit Failure Verify ECC -> ECC Correction
ECC : Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bits detection
: If program operation results in an error, map out
the block including the page in error and copy the
*t a rget data to anothe r block.
FLASH MEMORY
16
K9F1208R0C
K9F1208U0C K9F1208B0C
Erase Flow Chart
Star t
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another blo ck.
*
Erase Completed
Yes
Read Flow Chart
Start
Ver ify ECC
No
Write 00h
Writ e Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes (Continued)
Block Replacement
* Step1. When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2. Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3. Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4. Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
Buffer memory of the controller.
1st Block A
Block B
(n-1)th
nth
(page)
1
2
{
∼
1st
(n-1)th
nth
(page)
{
∼
an error occurs.
FLASH MEMORY
17
K9F1208R0C
K9F1208U0C K9F1208B0C
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however , is ef fective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed on ce with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is writt en. A comp lete read operation prior to ’80h’ command is not necessary. To pro gram data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
00h
(1) Command input sequenc e for programming ’A’ area
Address / Data input
80h 10h 00h 80h 10h
Address / Data input
The address pointer is set to ’A’ area(0~255), and sustained
01h
(2) Command input sequenc e for programming ’B’ area
Address / Data input
80h 10h 01h 80h 10h
Address / Data input
’B’, ’C’ area can be programmed.
It depends on how many data are inputted. ’01h’ command must be rewritten before
every program operation
The address pointer is set to ’B’ area(256~511), and will be reset to
’A’ area after every program operatio n i s executed.
50h
(3) Command input sequenc e for programming ’C’ area
Address / Data input
80h 10h 50h 80h 10h
Address / Data input
Only ’C’ area can be programmed. ’50h’ command can be omitted.
The address pointer is set to ’C’ area(512~527), and sustained
’00h’ command can be omitted.
It depends on how many data are inputted.
’A’,’B’,’C’ area can be programmed.
Pointer Operation of K9F1208X0C
Table 2. Destination of the pointer
Command Pointer position Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
256 Bytes
(00h plane) "B" a rea
(01h plane) "C" area
(50h plane)
256 Bytes 16 Bytes
"A" "B" "C"
Internal
Page Regi st er
Pointer selec t
commnad
(00h, 01h, 50h) Pointer
Figure 4. Block Diagram of Pointer Operation
FLASH MEMORY
18
K9F1208R0C
K9F1208U0C K9F1208B0C
System Interface Using CE do n’t-care.
For an easier system interface, CE may be inactive during the data-loading or se quential data-reading as shown below. The internal
528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the orde r of u -second s, de-activating CE durin g the data-loading and read-
ing would provide significant savings in power consumption.
Start Add.(4Cycle)00h
CE
CLE
ALE
WE
I/OXData Output(sequent ial)
CE don’t-care
≈
R/B tR
RE
Figure 5. Program Operation with CE don’t-care.
Figure 6. Read Operation with CE don’t-care.
CE
WE tWP
tCH
tCS
Start Add.(4Cycle)80h Data Input
CE
CLE
ALE
WE
I/OXData Input
CE don’t-care
≈
≈
10h
tCEA
out
tREA
CE
RE
I/OX
On K9F1208X0C-P
CE must be held
low during tR
FLASH MEMORY
19
K9F1208R0C
K9F1208U0C K9F1208B0C
* Command Latch Cycle
* Address Latch Cycle
CE
WE
CLE
ALE
I/OXCommand
tCLS
tCS
tCLH
tCH
tWP
tALS tALH
tDS tDH
CE
WE
CLE
ALE
I/OXA0~A7
tCLS
tCS tWC
tWP
tALS
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH tALH
tDS tDH
tWP
A9~A16 A17~A24 A25~A26
FLASH MEMORY
20
K9F1208R0C
K9F1208U0C K9F1208B0C
* Input Data Latch Cycle
* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
RE
CE
R/B
Dout Dout Dout
tRC
tREA
tRR
tOH
tREA
tREH tREA tOH
tRHZ*
≈≈≈≈
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
I/Ox
tCHZ*
tRHZ*
CE
CLE
WE
DIN 0 DIN 1 DIN n
ALE
tALS
tCLH
tWC
tCH
tDS tDH tDS tDH tDS tDH
tWP
tWH
tWP tWP
≈
≈
≈
I/Ox
FLASH MEMORY
21
K9F1208R0C
K9F1208U0C K9F1208B0C
Status Read Cycle (During Ready State)
CE
WE
CLE
RE
I/OX70h/7Ah Status Output
tCLR
tCLH
tCS
tWP tCH
tDS tDH tREA
tIR tOH
tOH
tWHR
tCEA
tCLS
tCHZ
tRHZ
tRP
Status Read Cycle (During Busy State)
CE
WE
CLE
RE
I/OX70h/7Ah Status Output
tCLR
tCLH
tCS
tWP tCH
tDS tDH tREAB
tIR tOH
tOH
tWHR
tCEA
tCLS
tCHZ
tRHZ
tRPB
R/B
R/B
FLASH MEMORY
22
K9F1208R0C
K9F1208U0C K9F1208B0C
tCHZ
tOH
READ1 OPERATION (READ ONE PAGE)
X8 device : m = 528 , Read CMD = 00h or 01h
1)
NOTES : 1) is only valid on K9F1208X0C-P
On K9F1208X0C-P
CE must be held
low during tR
1)
CE
CLE
R/B
I/OX
WE
ALE
RE
Busy
00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2
Column
Address Page(Row)
Address
tWB tAR
tRtRC tRHZ
tRR
Dout m
tRB
tCRY
tWC
≈≈ ≈
A25
tCEH
1)
N Address
tOH
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈
On K9F1208U0C-P
CE must be held
low during tR
Read1 Operation (Intercepted by CE)
CE
CLE
R/B
I/OX
WE
ALE
RE
Busy
00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2
Page(Row)
Address
Address
Column
tWB tAR tCHZ
tR
tRR
tRC
A25
tOH
≈≈≈≈≈≈≈≈
FLASH MEMORY
23
K9F1208R0C
K9F1208U0C K9F1208B0C
On K9F1208X0C-P
CE must be held
low during tR
Read2 Operation (Read One Page)
CE
CLE
R/B
I/OX
WE
ALE
RE
50h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout n+m
M Address
n+M
tAR
tR
tWB
tRR
A0~A3 : Valid Address
A4~A7 : Don′t care
≈
≈
A25
Selected
Row
Start
address M
512 16
Sequential Row Read Operation (Within a Block)
CE
CLE
R/B
I/OX
WE
ALE
RE
00h A0 ~ A7
Busy
M
Output
A9 ~ A16 A17 ~ A24 Dout
NDout
N+1 Dout
527 Dout
0Dout
1Dout
527
Busy
M+1
Output
N
Ready
≈
≈
≈
A25
≈
≈
≈
≈ ≈ ≈ ≈ ≈ ≈ ≈
≈ ≈ ≈
FLASH MEMORY
24
K9F1208R0C
K9F1208U0C K9F1208B0C
Page Program Operation
CE
CLE
R/B
I/OX
WE
ALE
RE
80h 70h I/O0
Din
NDin 10h
527
A0 ~ A7A17 ~ A24A9 ~ A16
Sequential Data
Input Command Column
Address Page(Row)
Address 1 up to 528 Byte Data
Serial Input Program
Command Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tPROG
tWB
tWC tWC tWC
≈
≈
≈
A25
≈
Block Erase Operation (Erase One Block)
CE
CLE
R/B
I/OX
WE
ALE
RE
60h A17 ~ A24A9 ~ A16
Erase Setup Command Erase Command Read Status
Command I/O0=1 Error in Erase
DOh 70h I/O 0
Busy
tWB tBERS
I/O0=0 Successful Erase
Page(Row)
Address
tWC
A25
FLASH MEMORY
25
K9F1208R0C
K9F1208U0C K9F1208B0C
Read ID Operation
CE
CLE
I/OX
WE
ALE
RE
90h
Read ID Command Maker Code Device Code
00h ECh 76h
tREA
Address. 1cycle
5Ah 3Fh
ID Defintition Table
90 ID : Access command = 90H
Value Description
1st Byte
2nd Byte
3rd Byte
4th Byte
ECh
76h
5Ah
3Fh
Maker Code
Device Code
Don’t support Copy Back Operation
Don’t support Multi Plane Operation
FLASH MEMORY
26
K9F1208R0C
K9F1208U0C K9F1208B0C
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.
Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of dat a within the selected p age are transferred
to the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. CE must be held low while in busy fo r K9F1208X0C-PXB0, while CE is don’t-care with K9F1208X0C- JXB0. If CE
goes high before the device returns to Ready, the random read operation is interrupted and Busy returns to Ready as the defined by
tCRY. Since the operation was aborted, the serial page read does not output valid data. Once the data in a page is loaded into the reg-
isters, they may be read out in 42ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stat-
ing from the selected column address up to the last column address.
The way the Read1 and Read2 commands work is like a point er set to either the main a rea or the spare area. The spare area of 512
to 527 bytes may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare
area while addresses A4 to A7 are ignored. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Fig-
ures 7 to 10 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F1208X0C-P :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE hig h. When the page address moves onto the
next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read
operation.
FLASH MEMORY
27
K9F1208R0C
K9F1208U0C K9F1208B0C
Figure 7. Read1 Operation
Start Add.(4Cycle)00h Data Output(Sequential)
CE
CLE
ALE
R/B
WE
I/O0~7
RE
tR
A0 ~ A7 & A9 ~ A25 (00h Command)
Data Field Spare Field
Main array
(01h Command)
Data Field Spare Field
1st half array 2st half array
NOTE :
1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
1)
On K9F1208X0C-P
CE must be held low during tR
FLASH MEMORY
28
K9F1208R0C
K9F1208U0C K9F1208B0C
Figure 8. Read2 Operation
50h Data Output(Sequen tial)
Spare Field
CE
CLE
ALE
R/B
WE
Start Add.(4Cycle)
I/OX
RE
tR
A0 ~ A3 & A9 ~ A25
Main array
Data Field Spare Field
(A4 ~ A7 : Fixed "Low")
On K9F1208X0C-P
CE must be held low during tR
FLASH MEMORY
29
K9F1208R0C
K9F1208U0C K9F1208B0C
Figure 9. Sequential Row Read1 Operation (only for K9F1208X0C-P valid within a block)
00h
01h A0 ~ A7 & A9 ~ A25
I/OX
R/B
Start Add.(4Cycle) Data Output Data Output Data Output
1st 2nd Nth
(528 Byte) (528 Byte)
tRtRtR
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
≈
( 00h Command)
Data Field Spare Field
( 01h Command)
Data Field Spare Field
1st half array 2nd half array
1st
2nd
Nth
1st half array 2nd half array
1st
2nd
Nth
Block
Figure 10. Sequential Row Read2 Operation (only for K9F1208X0C-P valid within a block)
50h
A0 ~ A3 & A9 ~ A25
I/OX
R/B
Start Add.(4Cycle) Data Output Data Output Data Ou tp ut
2nd Nth
(16Byte) (16Byte)
1st
tRtRtR
≈
Data Field Spare Field
1st
Block
(A4 ~ A7 :
Don’t Care)
Nth
FLASH MEMORY
30
K9F1208R0C
K9F1208U0C K9F1208B0C
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528 byte, in a single page program cycle. The number of consecutive partial page programming operation within the same page
without an intervening erase operation must not exceed 1 for main arr ay and 2 for spare array. The addressing may be done in any
random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded
into the page register, followed by a non-volatile programming per iod where the loaded data is programmed into the appropriate cell.
Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial D ata Input command(80h), followe d by the four cycle address input and
then serial data loading. The bytes other than those to be pro grammed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in p rogress. When the Pag e Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure11. Program Operation
80h
A0 ~ A7 & A9 ~ A25
I/O0~7
R/B
Address & Data Input I/O0Pass
528 Bytes Data
10h 70h
Fail
tPROG
Figure 12. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(16K Bytes) basis. Block address loading is accomplished in three cycles initiated by an
Erase Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following
the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write contr oller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.
60h
Block Add. : A14 ~ A25
I/OX
R/B
Address Input(3Cycle) I/O0Pass
D0h 70h
Fail
tBERS
FLASH MEMORY
31
K9F1208R0C
K9F1208U0C K9F1208B0C
Figure 13. Block Protect Operation
BLOCK PROTECT
Each block is protected from programming and erasing, controlled by the protect flag written in a specified a rea in the block. Block
Proctect opreation is initiated by w irting 4xh-80h-10h to the command register along with four address cycles. Only address A14 to
A26 is vali d while A0 to A13 is fixed as 00h. The da ta must not be loaded. Once the Block Protect opreation starts, the Read Status
Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion
of Page Program operation for protecting a block by monitoring the R/B output, or the S tatus bit(I/O 6) of the Status Register . Only the
Read Status command and Reset command are valid while Block Protect operation is in progress. But, if Reset command is inputted
while Block Protect operation is in progre ss, the block w ill not be gu aranteed whether it is pr otected or not. When the Page Pr ogram
operation for protecting a block is completed, the Write Status Bit(I/O 0) may be checked(Figure 13). The command register remains
in Read Status command mode until another valid command is written to the command register.
When programming is prohibited by 41h command, th e protect flag and the data of protected block can be erased by Block Erase
operation. Once erasing is prohibited by 42h/43h command, the protect flag and the data of protected block can not be erased. If
80h-10h is written to command register along with four address cycles at the program protected block or at the program/erase pro-
tected block, and if 60h-D0h is w ritten to command register along with three address cycles at the pr ogram/erase protected block,
the R/B pin changes to low for tR. The Block Protect operation must not be excuted on the aleady protected block. The Block Protect
operation will be aborted by Reset command(FFh). The Block Protect operation can only be used from first block to 200th block.
The device contains a Status Register which may be used to read out the state of the se lected block. After writing 7Ah command to
the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, wh ich-
ever occurs last(Figure 14). Refer to table 3 for specific Status Regist er definitions. The command register remains in Status Read
mode until further commands are issued to it.
80h
A0 ~ A7 : 00h Fix
I/OX
R/B
Address Input(4Cycle) I/O0Pass
10h 70h
Fail
tPROG
Three commands are provided to protect the block.
41h : Programming is prohibited
42h : Erasing is prohibited
43h : Both programming and erasing are prohibited
FFh
FFh
4Xh
A9 ~ A13 : 00h Fix
A14 ~ A25 : 0 to 4095
FLASH MEMORY
32
K9F1208R0C
K9F1208U0C K9F1208B0C
Table 3. Status Register Definition for 7Ah Command
NOTE :
1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
I/O Status Definition
I/O 0 Programming Protect Not protected : "0" Protected : "1"
I/O 1 Erasing Protect Not protected : "0" Protected : "1"
I/O 2 Not use Don’t -cared
I/O 3 Not Use Don’t -cared
I/O 4 Not Use Don’t -cared
I/O 5 Not Use Don’t -cared
I/O 6 Device Operation Busy: "0" Ready : "1"
I/O 7 Write Protect Protected : "0" Not protect : "1"
ALE
WE
CLE
I/OX00h A9 ~ A16A0 ~ A7A25 7Ah Status
A0~7 : 00h, A9~13 : 0 fixed, A14~25 : 0 to 4095
A17 ~ A24
RE
R/B
tR
Figure 14. Read Block Status
FLASH MEMORY
33
K9F1208R0C
K9F1208U0C K9F1208B0C
READ STATUS
The device contains a Status Register w hic h may be read to find o ut whether program or erase operation is completed, and w hethe r
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of C E or RE, whichever occu rs la st. This two line control allow s
the system to poll the progress of each device in multiple memory connections even when R/ B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table 4. Status Register Definition for 70h Command
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
.
I/O Page Program Block Erase Read Definition
I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" Fail : "1"
I/O 1 Not use Not use Not use Don’t -cared
I/O 2 Not use Not use Not use Don’t -cared
I/O 3 Not Use Not Use Not Use Don’t -cared
I/O 4 Not Use Not Use Not Use Don’t -cared
I/O 5 Not Use Not Use Not Use Don’t -cared
I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1"
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th cycle ID respectively. The
command register remains in Read ID mode until further commands are issued to it. Figure 15 shows the operation sequence.
Figure 15. Read ID Operation
CE
CLE
I/O0~7
ALE
RE
WE
90h 00h ECh
Address. 1cycle Maker code
tCEA
tAR
tREA
5Ah 3Fh
tWHR
Device
Device Device Code
K9F1208R0C 36h
K9F1208B0C 76h
K9F1208U0C 76h
Code
FLASH MEMORY
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K9F1208R0C
K9F1208U0C K9F1208B0C
Figure 16. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 16
below.
FFh
I/OX
R/B tRST
Table 5. Device Status
After Power-up After Reset
Operation mode 00h Command is latched Waiting for next command
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K9F1208R0C
K9F1208U0C K9F1208B0C
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allow ing two or more R/B outputs to be Or-tied. Because pull-u p resistor value is related to tr(R /B) and
current drain during busy( ibusy) , an appropriate value can be obtained with the f ollowing reference chart(Fig 17). Its value can be
determined by the following guidance.
R/B
open drain output
Device
GND
Rp ibusy
Busy
Ready Vcc
VOH
tf tr
VOL
VOL : 0.4V, VOH : 2.4V
C
L
1.8V device - VOL : 0.1V, VOH : Vcc-0.1V
3.3V device - VOL : 0.4V, VOH : 2.4V
VCC 2.7V device - VOL : 0.4V, VOH : VccQ-0.4V
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K9F1208R0C
K9F1208U0C K9F1208B0C
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
100
tf
200
300
400
3.6 3.6 3.6 3.6
2.4
1.2
0.8
0.6
Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 1.85V
3mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 3.2V
8mA + ΣIL
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
30
tf
60 90 120
1.7 1.7 1.7 1.7
1.7
0.85
0.57 0.43
Rp(min, 2.7V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 2.5V
3mA + ΣIL
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 2.7V, Ta = 25°C , CL = 30pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
30
tf
60 90 120
2.3 2.3 2.3 2.3
2.3
1.1
0.75 0.55
Figure 17. Rp vs tr ,tf & Rp vs ibusy
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K9F1208R0C
K9F1208U0C K9F1208B0C
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V( 1.8V device), 1.8V(2.7V device), 2V(3.3V device) . WP pin provides hard-
ware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100µs is
required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for
program/erase provides additional software protection.
Data Protection & Power-up sequence
Figure 18. AC Waveforms for Power Transition
VCC
WP
High
≈
≈
WE
3.3V device : ~ 2.5V 3.3V device : ~ 2.5V
100µs
≈≈
2.7V device : ~ 2.0V 2.7V device : ~ 2.0V
1.8V device : ~ 1.5V 1.8V device : ~ 1.5V
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K9F1208R0C
K9F1208U0C K9F1208B0C
WP AC Timing guide
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:
Figure A-1. Program Operation
1. Enable Mode
≈
80h 10h
WE
I/O
WP
R/B tww(min.100ns)
2. Disable Mode
≈
80h 10h
tww(min.100ns)
1. Enable Mode
≈
60h D0h
tww(min.100ns)
2. Disable Mode
≈
60h D0h
tww(min.100ns)
Figure A-2. Erase Operation
WE
I/O
WP
R/B
WE
I/O
WP
R/B
WE
I/O
WP
R/B
