SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 D High Output Current Differential D D D D D D DGN PACKAGE (TOP VIEW) Drive . . . >200 mA Rail-To-Rail Output Unity-Gain Bandwidth . . . 2.4 MHz Slew Rate . . . 1.5 V/s Supply Current . . . 1.4 mA Supply Voltage Range . . . 2.7 V to 5.5 V Specified Temperature Range: - TA = -40C to 85C . . . Industrial Grade SHDN VDD/2 IN+ IN- 1 8 2 7 3 6 4 5 VO - GND VDD VO + description The TLV4120 single supply operational differential amplifier provides a differential output current in excess of 200 mA at 5 V. This enables the amplifier to be used as high current line drivers, buffers, or coil driver applications. The TLV4120 has a shutdown feature that reduces the supply current down to 6 A when the amplifier is not active in the application. The TLV4120 is available in the ultrasmall MSOP PowerPAD package, which offers the exceptional thermal impedance required for amplifiers delivering high current levels. AVAILABLE OPTIONS TA DEVICE NUMBER OF CHANNELS PACKAGE TYPES MSOP (DGN) SYMBOL SHUTDOWN -40C to 85C TLV4120 1 TLV4120IDGN xxTIAHU Yes This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4120IDGNR). functional block diagram VDD 6 4 IN - 3 IN+ 2 VDD/2 - A1 + VO+ 5 - A2 + VO- 8 7 GND 1 SHDN Bias Control Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2000-2006, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Output current,IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA Continuous /RMS output current, IO (each output of amplifier): TJ 105C . . . . . . . . . . . . . . . . . . . . 350 mA TJ 150C . . . . . . . . . . . . . . . . . . . . 110 mA Peak output current, IO (each output of amplifier: TJ 105C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA TJ 150C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to GND. 2. To prevent permanent damage the die temperature must not exceed the maximum junction temperature. DISSIPATION RATING TABLE PACKAGE JC (C/W) JA (C/W) TA 25C POWER RATING TA = 85C POWER RATING DGN (8) 4.7 52.7 2.37 W 1.23 W See The Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature number SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on page 33 of the before mentioned document. recommended operating conditions Supply voltage, VDD Common-mode input voltage range, VICR Operating free-air temperature, TA MIN MAX 2.7 5.5 V VDD-0.5 85 C 0.5 I-suffix -40 V(on) Shutdown turn-on/off voltage level <VDD/3 >VDDx0.75 V(off) Relative to GND 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT V V SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 electrical characteristics at recommend operating conditions, VDD = 2.7 V and 5 V (unless otherwise noted) dc performance PARAMETER VIO CMRR AVD Input offset voltage Common-mode rejection ratio Large-signal differential voltage amplification TEST CONDITIONS VIC = VDD/2, VO = VDD/2 , RS = 50 VDD = 2.7 V, RS = 50 VIC = 0.5 to 2.2 V, VDD = 5 V, RS = 50 VIC = 0.5 to 4.5 V, VDD = 2.7 V, VO(PP)=1 V, VIC = VDD/2 VDD = 5 V, VO(PP)=3 V, VIC = VDD/2 RL=100 TA 25C MIN TYP MAX 100 3000 Full range 4000 25C 69 Full range 66 25C 71 Full range 68 25C 80 Full range 70 25C 90 Full range 80 UNITS V V 95 dB 95 85 dB RL=100 95 Full range is - 40C to 85C for I suffix. input characteristics PARAMETER IIO Input offset current IIB Input bias current ri(d) Differential input resistance CIC Common-mode input capacitance TEST CONDITIONS VIC = VDD/2 VO = VDD/2, RS = 50 TA 25C MIN TYP MAX 0.3 60 Full range 25C 300 0.3 Full range f = 100 Hz VDD/2 biasing resistors Amplifier A2's gain resistors Full range is - 40C to 85C for I suffix. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 60 UNITS pA 300 25C 1000 G 25C 5 pF 25C 500 k 25C 20 k 3 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 electrical characteristics at specified free-air temperature, VDD = 2.7 V and 5 V (unless otherwise noted) (continued) output characteristics PARAMETER TA 25C MIN TYP 2.6 2.67 IOH = -10 mA Full range 2.58 25C 2.35 IOH =-100 mA Full range 2.3 TEST CONDITIONS VDD = 2.7 V, VIC = VDD/2 VOH High-level output voltage VDD = 5 V, VIC = VDD/2 25C 4.9 IOH = -10 mA Full range 4.88 25C 4.7 IOH = -100 mA Full range 4.65 25C 4.45 IOH = -200 mA Full range 4.38 25C IOL = 10 mA VDD = 2.7 V , VIC = VDD/2 Low-level output voltage IOL = 10 mA Full range IOL = 100 mA Full range IO Output current Measured at 0.5 V from rail VDD = 2.7 V VDD = 5 V 4.55 0.1 0.4 0.5 0.03 0.1 0.12 0.2 V 0.3 0.35 25C IOL = 200 mA 4.8 0.12 25C VDD = 5 V, VIC = VDD/2 V 0.3 25C VOL 4.96 0.03 25C Full range UNITS 2.4 Full range IOL = 100 mA MAX 0.5 Full range 0.55 0.62 320 25C mA 200 Full range is- 40C to 85C for I suffix. power supply PARAMETER IDD PSRR TEST CONDITIONS Supply current Power supply rejection ratio (VDD / VIO) MIN VO = VDD/2, SHDN = <Vdd/3 V Full range VDD =2.7 to 3.3 V, VIC = VDD/2 V, No load 25C 80 Full range 75 25C 70 Full range 65 VDD =2.7 to 5 V, VIC = VDD/2 V, No load Full range is - 40C to 85C for I suffix. 4 TA 25C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TYP MAX 1.4 1.7 2.3 UNITS mA 94 84 dB SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 electrical characteristics at specified free-air temperature, VDD = 2.7 V and 5 V (unless otherwise noted) (continued) dynamic performance PARAMETER GBWP SR M TA 25C MIN TYP 25C 0.75 1.48 Full range 0.5 25C 0.9 VDD = 5 V Full range 0.65 CL = 10 pF 25C TEST CONDITIONS RL=100 Gain bandwidth product CL=10 pF Vo(pp) = VDD/2, RL = 100 , CL = 50 pF Slew rate at unity gain Phase margin RL = 100 , Gain margin Vn Input noise voltage Full range is - 40C to 85C for I suffix. VDD = 2.7 V MAX UNITS 2.4 MHz V/ s V/s 1.57 60 f = 10 kHz 25C 20 dB 10 nV/Hz shutdown characteristics PARAMETER IDD(SHDN) TA 25C TEST CONDITIONS SHDN > Vdd x 0.75 Supply current in shutdown mode Full range MIN TYP MAX 6 12 50 UNITS A A Full range is - 40C to 85C for I suffix. TYPICAL CHARACTERISTICS Table of Graphs FIGURE VOH VOL High-level output voltage vs High-level output current 1, 3 Low-level output voltage vs Low-level output current 2, 4 ZO PO Output impedance vs Frequency 5 Output power vs Load resistance 6 IDD PSRR Supply current vs Supply voltage 7 Power supply rejection ratio vs Frequency 8 Avd Differential voltage amplification and phase vs Frequency 9 Phase margin vs Capacitive load 10 vs Free-air temperature 11 vs Supply voltage 12 Total harmonic distortion + noise vs Frequency 13 Inverting large-signal pulse response vs Time 14 Inverting small-signal pulse response vs Time 15 Shutdown supply current vs Free-air temperature 16 Shutdown supply current vs Supply voltage 17 Shutdown mode pulse response vs Time 18 Slew rate IDD(SHDN) IDD(SHDN) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.7 2.1 1.8 1.5 1.2 0.9 TA = 25C TA = 0C TA = -40C 0.6 0.3 TA = 85C 0.0 5.00 VO = Positive & Negative VDD = 2.7 V 2.4 2.1 TA = 85C 1.8 TA = 25C TA = 0C TA = -40C 1.5 1.2 0.9 0.6 0.3 0.0 50 100 150 200 250 300 350 400 450 50 100 3.50 VO = Positive & Negative VDD = 5 V 3.25 150 200 250 300 350 0 50 100 150 200 250 300 350 400 450 500 IOH - High-Level Output Current - mA Figure 3 OUTPUT POWER vs LOAD RESISTANCE 800 1000 VO = Positive & Negative VDD = 5 V VDD = 2.7 V & 5 V TA = 25 C Z o - Output Impedance - 0.8 TA = 85C TA = 25C TA = 0C TA = -40C 0.4 0.3 0.2 10 AV = -10 1 0.1 THD+N = 1% f = 1 kHz 700 100 AV = -1 0.1 600 500 VDD = 5 V 400 300 VDD = 2.7 V 200 100 0.0 0 0.1 100 50 100 150 200 250 300 350 400 450 500 IOL - Low-Level Output Current - mA Figure 4 1k 10k 100k 1M f - Frequency - Hz I DD - Supply Current - mA TA = 25C 1.2 TA = 0C 1.0 TA = -40C 0.8 0.6 VIC = Bypass voltage 1 F Cap on bypass AV= 1 RL = Open 0.2 0.0 0 0.5 1 1.5 16 48 56 24 32 40 RL - Load Resistance - Figure 6 2 2.5 3 3.5 4 4.5 5 5.5 PSRR - Power Supply Rejection Ratio - dB TA = 85C 0.4 8 POWER SUPPLY REJECTION RATIO vs FREQUENCY 1.6 1.4 0 10M Figure 5 SUPPLY CURRENT vs SUPPLY VOLTAGE 80 70 60 50 40 30 20 VDD = 2.7 V & 5 V, AV = -10, RL = 100 , CL = 50 pF, TA = 25C 10 0 -10 -20 0.01 VDD - Supply Voltage - V 0.1 1 10 Figure 8 POST OFFICE BOX 655303 100 f - Frequency - Hz Figure 7 6 TA = 25C TA = 0C TA = -40C 3.75 OUTPUT IMPEDANCE vs FREQUENCY 1.0 0.5 4.00 Figure 2 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 TA = 85C 4.25 IOL - Low-Level Output Current - mA Figure 1 0.7 4.50 3.00 0 IOH - High-Level Output Current - mA 0.9 4.75 PO - Output Power - mW 0 VOL - Low-Level Output Voltage - V V OH - High-Level Output Voltage - V VO = Positive & Negative VDD = 2.7 V 2.4 VOL - Low-Level Output Voltage - V V OH - High-Level Output Voltage - V 2.7 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT * DALLAS, TEXAS 75265 1k 10 k 64 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS PHASE MARGIN vs CAPACITIVE LOAD 80 180 80 70 150 70 60 120 50 90 40 60 30 30 10 0 -10 1k 0 VDD = 2.7 V & 5 V, AV = Open Loop, RL = 100 , CL = 10 pF, TA = 25C 10 k Phase Margin - 20 60 Phase - 30 VDD = 2.7 V & 5 V, RL = 100 , R null = 0, TA = 25C 10 -60 0 10 -90 10 M 1M 40 20 -30 100 k 50 100 SLEW RATE vs SUPPLY VOLTAGE 2 1.75 1.75 SR+ 1.50 SR - Slew Rate - V/s SR - Slew Rate - V/s SR+ SR- 1.25 1 0.75 VDD = 2.7 V & 5 V AV = 1 RL= 100 CL = 50 pF VO = 1 VPP VI = 1.5 / 3 VPP 0.50 0.25 0 -40 1.50 SR- 1.25 1 0.75 AV = 1 RL =100 CL = 50 pF VI = 1.5 VPP 0.50 0.25 0 -15 10 35 60 85 2.5 3 3.5 4 4.5 VDD - Supply Voltage - V TA - Free-Air Temperature - C Figure 11 5 Figure 12 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY INVERTING LARGE-SIGNAL PULSE RESPONSE vs TIME 5 100 VI VDD = 2.7 V & 5 V, RL = 100 , CL = 50 pF Both Channels 10 V O - Output Voltage - V THD + N - Total Harmonic Distortion + Noise - dB 5k Figure 10 Figure 9 SLEW RATE vs FREE-AIR TEMPERATURE 2 1k CL - Capacitive Load - pF f - Frequency - Hz AV = 10 1 AV = 1 0.1 0.01 10 100 1k 10 k 4 3 VDD = 5 V RL =100 CL = 50 pF AV = -1 TA = 25C 5 2 1 0 V I - Input Voltage - V A VD - Differential Voltage Amplification - dB DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE vs FREQUENCY 4 VO+ 3 2 VO- 1 0 0 100 k 2 4 6 8 10 12 14 16 18 t - Time - s f - Frequency - Hz Figure 13 Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS INVERTING SMALL-SIGNAL PULSE RESPONSE vs TIME VDD = 5 V RL = 100 CL = 50 pF AV = -1 TA = 25C 0 -0.05 -0.10 2.55 2.45 VO+ 2.40 0 10 20 30 40 50 60 70 80 90 VIN = Bypass Voltage (VDD/2) 1 F Cap on Bypass AV = 1 RL = Open Shutdown = VDD 3.5 3.0 2.5 2.0 1.5 1.0 VDD = 5 V 0.5 0.0 VDD = 2.7 V -0.5 -1.0 -40 t - Time - s -15 10 35 60 TA - Free-Air Temperature - C Figure 15 Figure 16 SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE SHUTDOWN MODE PULSE RESPONSE vs TIME 0.9 0.8 0.7 0.6 SD in V O - Output Voltage - V I DD(SD) - Shutdown Supply Current - A 1.0 0.5 TA = 85C 0.4 0.3 0.2 TA = 25C 0.1 0.0 TA = -40C -0.1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 3 1 0 VO+ and VO- -1 5.5 0 Figure 17 POST OFFICE BOX 655303 VDD = 5 V RL = 100 CL = 10 pF AV = 1 VI = VDD/2 TA = 25C 2 VDD - Supply Voltage - V 8 85 200 400 600 800 1000 1200 t - Time - s Figure 18 * DALLAS, TEXAS 75265 6 4 2 0 SD - Shutdown Pulse - V 2.50 VO- I DD(SD) - Shutdown Supply Current - A V O - Output Voltage - V 0.05 4.0 V I - Input Voltage - V 0.10 VI SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION differential output drive The TLV4120 is two amplifiers arranged to produce high output current differential drive. The first amplifier, A1, is an operational amplifier, with both inputs uncommitted. This enables the first amplifier to be configured as an inverting amplifier, a noninverting amplifier, or even a difference amplifier. The second amplifier, A2, is internally configured as an inverting amplifier and biased about VDD/2. VDD 6 VDD VDD/2 4 IN - 3 IN+ 2 VDD/2 VO+ 5 - A1 + RL - A2 VO- 8 + 7 GND 1 SHDN Bias Control Figure 19 This approach makes a simple solution to single-ended to differential drive or even differential to differential drive. When using the TLV4120 to drive heavy differential loads, care must be taken not to saturate the output of the first amplifier, as the second amplifier will produce a mirror image (about VDD/2) of the first amplifier's output. This can lead to asymmetrical differential output swings. This differential output drive configuration is ideal for low frequency high current drive applications, such as line drivers, driving LVDTs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION Figure 20 shows the TLV4120 amplifier driving both ends of the load. There are several potential benefits to this differential drive configuration but initially consider power to the load. The differential drive to the load means that as one side is slewing up, the other side is slewing down, and vice versa. This doubles the voltage swing on the load as compared to a ground-referenced load, quadrupling the power delivered to the load. VDD VO(PP) 2x VO(PP) VDD -VO(PP) -1 Figure 20. Bridge-Tied Load Configuration component selection RF VDD 6 VDD/2 CS VIN RS 4 IN - CPS VO+ 5 - A1 3 IN+ 2 VDD/2 + RL CB - A2 VO- 8 + 7 GND 1 = Off 0 = On 1 SHDN Bias Control Figure 21. Driving a Capacitive Load 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VO SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION gain setting resistors, RF and RS The differential gain for the TLV4120, with A1 configured as an inverter, is set by resistors RF and RS using the following equation: R DiffGain + -2 R F S The differential gain for the TLV4120, with A1 in a noninverting configuration, is set by resistors RF and RS using the following equation: DiffGain + 2 1) R R F S Differential drive operation brings about the factor 2 in the gain equation due to amplifier A2, configured as an inverter, mirroring the voltage swing across the load. Given that the TLV4120 is a MOS amplifier, the input impedance is very high; consequently input bias currents in most cases will not generally be a concern (see offset voltage application section). However, the noise in the circuit will increase as RF increases. Typical values for RF will range between 5 k and 20 k. Large values of feedback resistor, RF, at low gains can cause instability due to the pole caused by the input capacitance. This can be alleviated by either reducing the size of RF or by putting a small capacitor in parallel with RF. AC coupling capacitor, CS When the input to the TLV4120 will be AC coupled to the input source, a high pass filter is formed with a corner frequency equal to: fc + 1 2pR C S S The value of CS is important to consider as it directly affects the low frequency operation of the circuit. A further consideration for this capacitor is the leakage path from the input source through the input network (RS, CS) and the feedback resistor (RF ) to the load. This leakage current creates a dc-offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. power supply decoupling, CPS The TLV4120 is a high-performance CMOS amplifier that requires adequate power supply decoupling to ensure stability and low total harmonic distortion (THD). Optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 F placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 F or greater placed near the amplifier is recommended. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION VDD/2 bypass capacitor, CB The VDD/2 bypass capacitor, CB, is the most critical capacitor and serves several important functions. During start-up or recovery from shutdown mode, CB determines the rate at which the amplifier starts up. The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the mid-rail generation circuit internal to the amplifier, which appears as degraded PSRR and THD + N. The capacitor is fed from two internal 500-k potential-dividing resistors. To keep the start-up bounce as low as possible, the relationship shown in equation 4 should be maintained. This ensures the input capacitor is fully charged before the bypass capacitor is fully charged and the amplifier starts up. CB 10 v 1 RF ) RS CS 250 kW As an example, consider a circuit where CB is 2.2 F, CS is 0.47 F, RF is 50 k, and RS is 10 k. Inserting these values into equation 4 produces the following: 18.2 35.5 which satisfies the rule. For bypass capacitor, CB , 0.1-F to 2.2-F ceramic or tantalum low-ESR capacitors are recommended for the best stability and noise performance. using low-ESR capacitors Low-ESR capacitors are recommended. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. shutdown function The TLV4120 has a shutdown terminal for conserving power in energy sensitive applications. When the shutdown terminal is pulled high the amplifier is disabled, placing the outputs into a high impedance state and reducing the supply current to the order of microamperes. To enable the amplifier, the shutdown terminal must be pulled low. If open drain logic is used, pull-up resistors must be employed to ensure proper and known shutdown status. It is not recommended that the shutdown input is left to float, as the device could inadvertently shutdown. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION driving a capacitive load When the amplifier is used to drive heavy capacitive loads, the device's phase margin will be reduced which could lead to high frequency ringing or oscillations. The TLV4120's high current drive capability reduces this possibility. However, for capacitive loads of greater than 1 nF, it is suggested that a resistor be placed in series (RNULL ) with the output of the amplifier as shown in Figure 22 which should help reduce the ringing. RF CS RS - A1 SHDN + RNULL CL RL CB - RNULL A2 + VDD/2 CL NOTE: RNULL will reduce the output drive capability of the TLV4120. Figure 22. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of: 1. The input offset voltage (VIO) multiplied by the noninverting gain 2. The noninverting input bias current (IIB) multiplied by the resistance on this node multiplied by the noninverting gain 3. The inverting bias current multiplied by the feedback resistor. RF IIB- RG - VI RBIAS/2 + VO IIB+ Figure 23. Output Offset Voltage Model POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION offset voltage (continued) The differential nature of the TLV4120 means that both amplifiers must be considered together to calculate the differential output offset voltage (VDOO) (see Figure 24). The VOO of amplifier A1 will be inverted by amplifier A2. This doubles A1's VOO and has A2's VOO added to it, yielding: V DOO + 2V IO1 1) R R F "I S IB) 1) 500k R R F " 2I S IB- R -2V "I 500k " I 20k F IB) IB- IO2 RF IIB- RS VIO - A1 + 20 k IIB+ VDD 20 k IIB- 500 k VIO - A2 + 500 k IIB+ Figure 24. TLV4120 Offset Voltage Model 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION general power design considerations When driving heavy loads at high junction temperatures there is an increased probability of electromigration affecting the long term reliability of ICs. Therefore for this not to be an issue: D The output current must be limited (at these high junction temperatures) or D The junction temperature must be limited. The maximum continuous output current at a die temperature of 150C will be 1/3 of the current at 105C. The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from the die to the ambient, and power dissipated within the IC. TJ = TA + JA x PDIS Where: PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across the output of the IC. JA is the thermal impedance between the junction and the ambient temperature of the IC. TJ is the junction temperature. TA is the ambient temperature. Reducing one or more of these factors will result in a reduced die temperature. The use of the MSOP PowerPAD dramatically reduces the thermal impedance from junction to case. And with correct mounting, the reduced thermal impedance will greatly increase the IC's permissible power dissipation and output current handling capability. For example, the power dissipation of the PowerPAD is increased to above 1 W. Sinusoidal and pulse-width modulated output signals will also increase the output current capability. The equivalent dc current is proportional to the square-root of the duty cycle: I DC(EQ) +I Cont (duty cycle) CURRENT DUTY CYCLE AT PEAK RATED CURRENT EQUIVALENT DC CURRENT AS A PERCENTAGE OF PEAK CURRENT 100 100 70 84 50 71 Note that with an operational amplifier, a duty cycle of 70% will often result in the op-amp sourcing current 70% of the time and sinking current 30%; therefore, the equivalent dc current will still be 0.84 times the continuous current rating at a particular junction temperature. The differential nature of the TLV4120 means that it will dissipate approximately four times the power of a single-ended amplifier driving a similar load referenced to mid rail. The TLV4120 will however be delivering four times the power to the load. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION general PowerPAD design considerations The TLV4120 is available in a thermally-enhanced PowerPAD package. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 25(a) and Figure 25(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 25(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. Soldering the PowerPAD to the PCB is always recommended, even with applications that have low-power dissipation. This provides the necessary connection between the lead frame die pad and the PCB. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with mechanical heatsinking methods. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 25. Views of Thermally-Enhanced DGN Package 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. general PowerPAD design considerations (continued) 1. The thermal pad must be connected to the same voltage potential as the device GND pin. 2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawing at the end of this document. There should be etch for the leads as well as etch for the thermal pad. 3. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLV4120 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 5. Connect all holes to the internal ground plane that is at the same voltage potential as the GND pin. 6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV4120 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 8. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 9. With these preparatory steps in place, the TLV4120 IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given JA, the maximum power dissipation is shown in Figure 26 and is calculated by the following formula: P Where: D + T -T MAX A q JA PD = Maximum power dissipation of TLV4120 IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SLOS310B - DECEMBER 2000 - REVISED SEPTEMBER 2006 APPLICATION INFORMATION general PowerPAD design considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 4 TJ = 150C Maximum Power Dissipation - W 3.5 3 2.5 2 DGN Package Low-K Test PCB JA = 52.7C/W 1.0 1 0.5 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 26. Maximum Power Dissipation vs Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, JA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV4120IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV4120IDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV4120IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV4120IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV4120IDGNR Package Package Pins Type Drawing MSOPPower PAD DGN 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.3 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV4120IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated