SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DHigh Output Current Differential
Drive . . . >200 mA
DRail-To-Rail Output
DUnity-Gain Bandwidth . . . 2.4 MHz
DSlew Rate . . . 1.5 V/µs
DSupply Current . . . 1.4 mA
DSupply Voltage Range . . . 2.7 V to 5.5 V
DSpecified Temperature Range:
− TA = −40°C to 85°C . . . Industrial Grade
description
The TLV4120 single supply operational differential amplifier provides a differential output current in excess of
200 mA at 5 V. This enables the amplifier to be used as high current line drivers, buffers, or coil driver
applications. The TLV4120 has a shutdown feature that reduces the supply current down to 6 µA when the
amplifier is not active in the application.
The TLV4120 is available in the ultrasmall MSOP PowerPAD package, which offers the exceptional thermal
impedance required for amplifiers delivering high current levels.
AVAILABLE OPTIONS
TA
DEVICE
NUMBER OF
PACKAGE TYPES
SYMBOL
SHUTDOWN
T
A
DEVICE
NUMBER OF
CHANNELS MSOP (DGN)†
SYMBOL
SHUTDOWN
−40°C to 85°C TLV4120 1 TLV4120IDGN xxTIAHU Yes
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g.,
TLV4120IDGNR).
functional block diagram
Bias
Control
6
5
7
VO+
VDD
1
2
4IN −
VDD/2
SHDN
VO−8
GND
3 IN+
−
+
−
+
A1
A2
Copyright 2000−2006, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
SHDN
VDD/2
IN+
IN−
VO−
GND
VDD
VO+
DGN PACKAGE
(TOP VIEW)
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current,IO (see Note 2) 800 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous /RMS output current, IO (each output of amplifier): TJ ≤ 105°C 350 mA. . . . . . . . . . . . . . . . . . . .
TJ ≤ 150°C 110 mA. . . . . . . . . . . . . . . . . . . .
Peak output current, IO (each output of amplifier: TJ ≤ 105°C 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TJ ≤ 150°C 155 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: I suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. To prevent permanent damage the die temperature must not exceed the maximum junction temperature.
DISSIPATION RATING TABLE
PACKAGE θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING TA = 85°C
POWER RATING
DGN (8)‡4.7 52.7 2.37 W 1.23 W
‡See The Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature number
SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based
on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on page 33 of the before
mentioned document.
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 2.7 5.5 V
Common-mode input voltage range, VICR 0.5 VDD−0.5 V
Operating free-air temperature, TAI-suffix −40 85 °C
Shutdown turn-on/off voltage level§
V(on) <VDD/3
V
Shutdown turn-on/off voltage level§V(off) >VDD×0.75 V
§Relative to GND
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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electrical characteristics at recommend operating conditions, VDD = 2.7 V and 5 V (unless
otherwise noted)
dc performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
VIO
Input offset voltage
VIC = VDD/2,
VO = VDD/2 ,
25°C 100 3000
V
VIO Input offset voltage VIC = VDD/2,
VO = VDD/2 ,
RS = 50 ΩFull range 4000 µV
VDD = 2.7 V,
VIC = 0.5 to 2.2 V,
25°C 69 95
CMRR
Common-mode rejection ratio
VDD = 2.7 V,
RS = 50 Ω
VIC = 0.5 to 2.2 V,
Full range 66
dB
CMRR Common-mode rejection ratio
VDD = 5 V,
VIC = 0.5 to 4.5 V,
25°C 71 95 dB
VDD = 5 V,
RS = 50 Ω
VIC = 0.5 to 4.5 V,
Full range 68
VDD = 2.7 V,
VO(PP)=1 V,
RL=100 Ω
25°C 80 85
AVD
Large-signal differential voltage
DD
V
O(PP)
=1 V,
VIC = VDD/2 RL=100 ΩFull range 70
dB
AVD
Large-signal differential voltage
amplification VDD = 5 V,
VO(PP)=3 V,
RL=100 Ω
25°C 90 95 dB
DD
V
O(PP)
=3 V,
V
IC
=
V
DD
/2 RL=100 ΩFull range 80
†Full range is −40°C to 85°C for I suffix.
input characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
IIO
Input offset current
V = V /2
25°C 0.3 60
I
IO
Input offset current
VIC = VDD/2
Full range
300
IIO
Input offset current
VIC = VDD/2
VO = VDD/2,
Full range 300
pA
IIB
Input bias current
IC DD
V
O
= V
DD
/2,
RS = 50 Ω
25°C 0.3 60 pA
I
IB
Input bias current
RS = 50 Ω
Full range
300
IIB
Input bias current
S
Full range 300
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 100 Hz 25°C 5 pF
VDD/2 biasing resistors 25°C 500 kΩ
Amplifier A2’s gain resistors 25°C 20 kΩ
†Full range is −40°C to 85°C for I suffix.
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electrical characteristics at specified free-air temperature, VDD = 2.7 V and 5 V (unless
otherwise noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
IOH = −10 mA
25°C 2.6 2.67
VDD = 2.7 V, VIC = VDD/2
IOH = −10 mA Full range 2.58
VDD = 2.7 V, VIC = VDD/2
IOH =−100 mA
25°C 2.35 2.4
IOH =−100 mA Full range 2.3
VOH
High-level output voltage
IOH = −10 mA
25°C 4.9 4.96
V
VOH High-level output voltage IOH = −10 mA Full range 4.88 V
VDD = 5 V, VIC = VDD/2
IOH = −100 mA
25°C 4.7 4.8
VDD = 5 V, VIC = VDD/2 IOH = −100 mA Full range 4.65
IOH = −200 mA
25°C 4.45 4.55
IOH = −200 mA Full range 4.38
IOL = 10 mA
25°C 0.03 0.1
VDD = 2.7 V , VIC = VDD/2
IOL = 10 mA Full range 0.12
VDD = 2.7 V , VIC = VDD/2
IOL = 100 mA
25°C 0.3 0.4
IOL = 100 mA Full range 0.5
VOL
Low−level output voltage
IOL = 10 mA
25°C 0.03 0.1
V
VOL Low−level output voltage IOL = 10 mA Full range 0.12 V
VDD = 5 V, VIC = VDD/2
IOL = 100 mA
25°C 0.2 0.3
VDD = 5 V, VIC = VDD/2 IOL = 100 mA Full range 0.35
IOL = 200 mA
25°C 0.5 0.55
IOL = 200 mA Full range 0.62
IO
Output current
Measured at 0.5 V from rail
VDD = 2.7 V
25°C
320
mA
I
O
Output current
Measured at 0.5 V from rail
VDD = 5 V
25
°
C
200
mA
†Full range is−40 °C to 85°C for I suffix.
power supply
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNITS
IDD
Supply current
VO = VDD/2, SHDN = <Vdd/3 V
25°C 1.4 1.7
mA
IDD Supply current VO = VDD/2, SHDN = <Vdd/3 V Full range 2.3 mA
VDD =2.7 to 3.3 V,
25°C 80 94
PSRR
Power supply rejection ratio (∆VDD / ∆VIO)
VDD =2.7 to 3.3 V,
VIC = VDD/2 V, No load Full range 75
dB
PSRR
Power supply rejection ratio (
∆
V
DD
/
∆
V
IO
)
VDD =2.7 to 5 V,
25°C 70 84
dB
VDD =2.7 to 5 V,
VIC = VDD/2 V, No load Full range 65
†Full range is −40°C to 85°C for I suffix.
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electrical characteristics at specified free-air temperature, VDD = 2.7 V and 5 V (unless
otherwise noted) (continued)
dynamic performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
GBWP Gain bandwidth product RL=100 ΩCL=10 pF 25°C 2.4 MHz
Vo( ) = V ,
VDD = 2.7 V
25°C 0.75 1.48
SR
Slew rate at unity gain
Vo(pp)
= VDD/2
,
RL = 100 Ω,
VDD = 2.7 V Full range 0.5
V/ s
SR Slew rate at unity gain
o(pp)DD/2
R
L
= 100
Ω
,
CL = 50 pF
VDD = 5 V
25°C 0.9 1.57 V/µs
CL = 50 pF
VDD = 5 V Full range 0.65
φMPhase margin
RL = 100 Ω,
CL = 10 pF
25°C
60
Gain margin RL = 100 Ω, CL = 10 pF 25°C20 dB
VnInput noise voltage f = 10 kHz 25°C 10 nV/√Hz
†Full range is −40°C to 85°C for I suffix.
shutdown characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNITS
IDD(SHDN)
Supply current in shutdown mode
SHDN > Vdd × 0.75
25°C 6 12
A
IDD(SHDN
)
Supply current in shutdown mode
SHDN > Vdd
×
0.75
Full range 50 µA
†Full range is −40°C to 85°C for I suffix.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VOH High-level output voltage vs High-level output current 1, 3
VOL Low-level output voltage vs Low-level output current 2, 4
ZOOutput impedance vs Frequency 5
POOutput power vs Load resistance 6
IDD Supply current vs Supply voltage 7
PSRR Power supply rejection ratio vs Frequency 8
Avd Differential voltage amplification and phase vs Frequency 9
Phase margin vs Capacitive load 10
Slew rate
vs Free-air temperature 11
Slew rate
vs Supply voltage 12
Total harmonic distortion + noise vs Frequency 13
Inverting large-signal pulse response vs Time 14
Inverting small-signal pulse response vs Time 15
IDD(SHDN) Shutdown supply current vs Free-air temperature 16
IDD(SHDN) Shutdown supply current vs Supply voltage 17
Shutdown mode pulse response vs Time 18
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 50 100 150 200 250 300 350 400 450
VO = Positive & Negative
VDD = 2.7 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH − High-Level Output Voltage − V
IOH − High-Level Output Current − mA
TA = 25°C
TA = 0°C
TA = −40°CTA = 85°C
Figure 2
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 50 100 150 200 250 300 350
VO = Positive & Negative
VDD = 2.7 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
TA = 0°C
TA = −40°C
TA = 85°C
IOL − Low-Level Output Current − mA
OL
V − Low-Level Output Voltage − V
Figure 3
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
0 50 100 150 200 250 300 350 400 450 500
TA = 25°C
TA = 0°C
TA = −40°C
VO = Positive & Negative
VDD = 5 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V
OH
− High-Level Output Voltage − V
IOH − High-Level Output Current − mA
TA = 85°C
Figure 4
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 50 100 150 200 250 300 350 400 450 500
VO = Positive & Negative
VDD = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
OL
V − Low-Level Output Voltage − V
TA = 85°C
TA = 25°C
TA = 0°C
TA = −40°C
Figure 5
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
100 1k 10k 100k 1M 10M
− Output Impedance −ZoΩ
0.1
10
0.1
1000
AV = −10
AV = −1
VDD = 2.7 V & 5 V
TA = 25° C
1
100
Figure 6
RL − Load Resistance − Ω
OUTPUT POWER
vs
LOAD RESISTANCE
300
200
100
016 3224 40 64
800
8
P
48 56
O− Output Power − mW
400
THD+N = 1%
f = 1 kHz
VDD = 5 V
500
600
VDD = 2.7 V
700
Figure 7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
DD
I Supply Current − −
0 1.5 3.5 4 5 5.5
mA
VIC = Bypass voltage
1 µF Cap on bypass
AV= 1
RL = Open
TA = −40°C
TA = 0°C
TA = 85°CTA = 25°C
4.5
32.5210.5
Figure 8
−20
−10
0
10
20
30
40
50
60
70
80
0.01 0.1 1 10 100 1 k 10 k
VDD = 2.7 V & 5 V,
AV = −10,
RL = 100 Ω,
CL = 50 pF,
TA = 25°C
f − Frequency − Hz
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSRR − Power Supply Rejection Ratio − dB
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
f − Frequency − Hz
30
20
0
1 k 10 k 100 k
− Differential Voltage Amplification − dB
40
50
DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE
vs
FREQUENCY
80
1 M 10 M
60
10
−10
30
0
−60
60
90
150
120
−30
−90
70
180
AVD
Phase − °
VDD = 2.7 V & 5 V,
AV = Open Loop,
RL = 100 Ω,
CL = 10 pF,
TA = 25°C
Figure 9 Figure 10
CL − Capacitive Load − pF
40
30
10
10 100
Phase Margin −
50
60
PHASE MARGIN
vs
CAPACITIVE LOAD
80
1 k 5 k
70
20
0
°
VDD = 2.7 V & 5 V,
RL = 100 Ω,
R null = 0,
TA = 25°C
Figure 11
0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
−40 −15 10 35 60 85
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR − Slew Rate − V/µs
SR+
SR−
VDD = 2.7 V & 5 V
AV = 1
RL= 100 Ω
CL = 50 pF
VO = 1 VPP
VI = 1.5 / 3 VPP
Figure 12
0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
2.5 3 3.5 4 4.5 5
SR−
SR+
SLEW RATE
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
SR − Slew Rate − V/µs
AV = 1
RL =100 Ω
CL = 50 pF
VI = 1.5 VPP
Figure 13
0
1
2
3
4
5
02 4681012141618
0
1
2
3
4
5
VI
VO+
VO−
t − Time − µs
− Output Voltage − VVO
INVERTING LARGE-SIGNAL PULSE RESPONSE
vs
TIME
− Input Voltage − VVI
VDD = 5 V
RL =100 Ω
CL = 50 pF
AV = −1
TA = 25°C
Figure 14
0.01
0.1
1
10
100
10 100 1 k 10 k 100 k
AV = 10
AV = 1
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
f − Frequency − Hz
THD + N − Total Harmonic Distortion + Noise − dB
VDD = 2.7 V & 5 V,
RL = 100 Ω,
CL = 50 pF
Both Channels
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
2.40
2.45
2.50
2.55
0 102030405060708090
−0.10
−0.05
0
0.05
0.10
t − Time − µs
INVERTING SMALL-SIGNAL PULSE RESPONSE
vs
TIME
− Output Voltage − VVO
VDD = 5 V
RL = 100 Ω
CL = 50 pF
AV = −1
TA = 25°C
− Input Voltage − VVI
VO−
VI
VO+
Figure 16
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
−40 −15 10 35 60 85
TA − Free-Air Temperature − °C
VDD = 5 V
VDD = 2.7 V
VIN = Bypass Voltage (VDD/2)
1 µF Cap on Bypass
AV = 1
RL = Open
Shutdown = VDD
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
DD(SD)
I Shutdown Supply Current −−Aµ
Figure 17
0
1
2
3
0200 400 600 800 1000 1200
0
2
4
t − Time − µs
SHUTDOWN MODE PULSE RESPONSE
vs
TIME
− Output Voltage − VVO
VDD = 5 V
RL = 100 Ω
CL = 10 pF
AV = 1
VI = VDD/2
TA = 25°C
VO+ and VO−
SD in
SD − Shutdown Pulse − V
6
−1
Figure 18
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VDD − Supply Voltage − V
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TA = 85°C
TA = 25°C
TA = −40°C
DD(SD)
I Shutdown Supply Current −−
0 1 2 3.5 4.5 5 5.5432.51.50.5
Aµ
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
differential output drive
The TLV4120 is two amplifiers arranged to produce high output current differential drive. The first amplifier, A1,
is an operational amplifier, with both inputs uncommitted. This enables the first amplifier to be configured as an
inverting ampl i f i e r, a noninverting amplifier, or even a dif ference amplifier. The second amplifier, A2, is internally
configured as an inverting amplifier and biased about VDD/2.
Bias
Control
6
5
7
VO+
VDD
1
2
4
VDD/2
IN −
VDD/2
SHDN
VO−8
GND
3 IN+
−
+
−
+
A1
A2
RL
VDD
Figure 19
This approach makes a simple solution to single-ended to differential drive or even differential to differential
drive.
When using the TLV4120 to drive heavy differential loads, care must be taken not to saturate the output of the
first amplifier, as the second amplifier will produce a mirror image (about VDD/2) of the first amplifier’s output.
This can lead to asymmetrical differential output swings.
This di fferential output drive configuration is ideal for low frequency high current drive applications, such as line
drivers, driving LVDTs.
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 20 shows the TLV4120 amplifier driving both ends of the load. There are several potential benefits to
this d i f ferential drive configuration but initially consider power to the load. The dif ferential drive to the load means
that as one side is slewing up, the other side is slewing down, and vice versa. This doubles the voltage swing
on the load as compared to a ground-referenced load, quadrupling the power delivered to the load.
VDD
−1
VDD
2x VO(PP)
VO(PP)
−VO(PP)
Figure 20. Bridge-Tied Load Configuration
component selection
Bias
Control
6
5
7
VO+
VDD
1
2
4
VDD/2
IN −
VDD/2
SHDN
VO−8
GND
3 IN+
−
+
−
+
A1
A2
CB
RS
CS
CPS
RF
RLVO
VIN
1 = Off
0 = On
Figure 21. Driving a Capacitive Load
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APPLICATION INFORMATION
gain setting resistors, RF and RS
The differential gain for the TLV4120, with A1 configured as an inverter , is set by resistors RF and RS using the
following equation:
DiffGain +–2 ǒRF
RSǓ
The dif ferential gain for the TLV4120, with A1 in a noninverting configuration, is set by resistors RF and R S using
the following equation:
DiffGain +2 ǒ1)RF
RSǓ
Differential drive operation brings about the factor 2 in the gain equation due to amplifier A2, configured as an
inverter, mirroring the voltage swing across the load.
Given that the TLV4120 is a MOS amplifier , the input impedance is very high; consequently input bias currents
in most cases will not generally be a concern (see offset voltage application section). However, the noise in the
circuit will increase as RF increases. Typical values for RF will range between 5 kΩ and 20 kΩ.
Large values of feedback resistor, RF, at low gains can cause instability due to the pole caused by the input
capacitance. This can be alleviated by either reducing the size of RF or by putting a small capacitor in parallel
with RF.
AC coupling capacitor, CS
When the input to the TLV4120 will be AC coupled to the input source, a high pass filter is formed with a corner
frequency equal to:
fc+1
2pRSCS
The value of CS is important to consider as it directly affects the low frequency operation of the circuit.
A further consideration for this capacitor is the leakage path from the input source through the input network
(RS, C S) and the feedback resistor (RF ) to the load. This leakage current creates a dc-offset voltage a t the input
to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a
low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive
side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/2,
which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application.
power supply decoupling, CPS
The T LV4120 is a high-performance CMOS amplifier that requires adequate power supply decoupling to ensure
stability and low total harmonic distortion (THD). Optimum decoupling is achieved by using two capacitors of
different types that target different types of noise on the power supply leads. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically
0.1 µF placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise signals,
a larger aluminum electrolytic capacitor of 10 µF or greater placed near the amplifier is recommended.
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
VDD/2 bypass capacitor, CB
The VDD/2 bypass capacitor, CB, is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CB determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the mid-rail generation circuit internal to the amplifier, which appears as degraded PSRR and THD
+ N. The capacitor is fed from two internal 500-kΩ potential-dividing resistors. To keep the start-up bounce as
low as possible, the relationship shown in equation 4 should be maintained. This ensures the input capacitor
is fully charged before the bypass capacitor is fully charged and the amplifier starts up.
10
ǒCB 250 kWǓv1
ǒRF)RSǓCS
As an example, consider a circuit where CB is 2.2 µF, CS is 0.47 µF, RF is 50 kΩ, and RS is 10 k Ω. Inserting these
values into equation 4 produces the following:
18.2 ≤ 35.5
which satisfies the rule. For bypass capacitor, CB , 0.1-µF to 2.2-µF ceramic or tantalum low-ESR capacitors
are recommended for the best stability and noise performance.
using low-ESR capacitors
Low-ESR capacitors are recommended. A real (as opposed to ideal) capacitor can be modeled simply as a
resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects
of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor
behaves like an ideal capacitor.
shutdown function
The TLV4120 has a shutdown terminal for conserving power in energy sensitive applications. When the
shutdown terminal is pulled high the amplifier is disabled, placing the outputs into a high impedance state and
reducing the supply current to the order of microamperes.
To enable the amplifier, the shutdown terminal must be pulled low. If open drain logic is used, pull-up resistors
must be employed to ensure proper and known shutdown status. It is not recommended that the shutdown input
is left to float, as the device could inadvertently shutdown.
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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APPLICATION INFORMATION
driving a capacitive load
When the amplifier is used to drive heavy capacitive loads, the device’s phase margin will be reduced which
could lead to high frequency ringing or oscillations. The TLV4120’s high current drive capability reduces this
possibility. However, for capacitive loads of greater than 1 nF, it is suggested that a resistor be placed in series
(RNULL ) with the output of the amplifier as shown in Figure 22 which should help reduce the ringing.
RNULL
VDD/2
SHDN
−
+
−
+
A1
A2
CB
RS
CS
CL
RF
RNULL
RL
CL
NOTE: RNULL will reduce the output drive capability of the TLV4120.
Figure 22. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of:
1. The input offset voltage (VIO) multiplied by the noninverting gain
2. The noninverting input bias current (IIB) multiplied by the resistance on this node multiplied by the
noninverting gain
3. The inverting bias current multiplied by the feedback resistor.
+
−
VI
RG
RBIAS/2
RF
IIB−
VO
IIB+
Figure 23. Output Offset Voltage Model
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
offset voltage (continued)
The differential nature of the TLV4120 means that both amplifiers must be considered together to calculate the
differential output offset voltage (VDOO) (see Figure 24). The VOO of amplifier A1 will be inverted by amplifier
A2. This doubles A1’s VOO and has A2’s VOO added to it, yielding:
VDOO +2VIO1 ǒ1)ǒRF
RSǓǓ"IIB)500k ǒ1)ǒRF
RSǓǓ"2IIB– RF–2VIO2 "IIB)500k "IIB–20k
−
+
−
+
A1
A2
VDD
IIB+
IIB+
IIB−
VIO
500 kΩ
VIO
IIB−
R
F
RS
500 kΩ
20 kΩ
20 kΩ
Figure 24. TLV4120 Offset Voltage Model
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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APPLICATION INFORMATION
general power design considerations
When driving heavy loads at high junction temperatures there is an increased probability of electromigration
affecting the long term reliability of ICs. Therefore for this not to be an issue:
DThe output current must be limited (at these high junction temperatures) or
DThe junction temperature must be limited.
The maximum continuous output current at a die temperature of 150°C will be 1/3 of the current at 105°C.
The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from
the die to the ambient, and power dissipated within the IC.
TJ = TA + θJA × PDIS
Where: PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across
the output of the IC.
θJA is the thermal impedance between the junction and the ambient temperature of the IC.
TJ is the junction temperature.
TA is the ambient temperature.
Reducing one or more of these factors will result in a reduced die temperature.
The use of the MSOP PowerPAD dramatically reduces the thermal impedance from junction to case. And with
correct mounting, the reduced thermal impedance will greatly increase the IC’s permissible power dissipation
and output current handling capability. For example, the power dissipation of the PowerPAD is increased to
above 1 W. Sinusoidal and pulse-width modulated output signals will also increase the output current capability.
The equivalent dc current is proportional to the square-root of the duty cycle:
IDC(EQ) +ICont (duty cycle)
Ǹ
CURRENT DUTY CYCLE
AT PEAK RATED CURRENT EQUIVALENT DC CURRENT
AS A PERCENTAGE OF PEAK
CURRENT
100 100
70 84
50 71
Note that with an operational amplifier, a duty cycle of 70% will often result in the op-amp sourcing current 70%
of the time and sinking current 30%; therefore, the equivalent dc current will still be 0.84 times the continuous
current rating at a particular junction temperature.
The differential nature of the TLV4120 means that it will dissipate approximately four times the power of a
single-ended amplifier driving a similar load referenced to mid rail. The TLV4120 will however be delivering four
times the power to the load.
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations
The TLV4120 is available in a thermally-enhanced PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted [see Figure 25(a) and Figure 25(b)]. This arrangement results
in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 25(c)]. Because
this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by
providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the PCB is always recommended, even with applications that have low-power
dissipation. This provides the necessary connection between the lead frame die pad and the PCB.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with mechanical heatsinking methods.
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 25. Views of Thermally-Enhanced DGN Package
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
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APPLICATION INFORMATION
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
general PowerPAD design considerations (continued)
1. The thermal pad must be connected to the same voltage potential as the device GND pin.
2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawing
at the end of this document. There should be etch for the leads as well as etch for the thermal pad.
3. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV4120 IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane that is at the same voltage potential as the GND pin.
6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLV4120 PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
9. With these preparatory steps in place, the TLV4120 IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 26 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV4120 IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
SLOS310B − DECEMBER 2000 − REVISED SEPTEMBER 2006
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
TJ = 150°C
4
3
2
0
−55 −40 −10 20 35
Maximum Power Dissipation − W
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
65 95 125
1
TA − Free-Air Temperature − °C
−25 5 50 80 110
3.5
2.5
1.0
0.5
DGN Package
Low-K Test PCB
θJA = 52.7°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 26. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around
the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in
these graphs are for the total package.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV4120IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4120IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4120IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV4120IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV4120IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Apr-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV4120IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Apr-2009
Pack Materials-Page 2
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