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74LVC163
Presettable synchronous 4-bit binary
counter; synchronous reset
Product specification
Supersedes data of 1996 Aug 23
IC24 Data Handbook
1998 May 20
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
2
1998 May 20 853-1865 19421
FEATURES
•Wide supply voltage range of 1.2 V to 3.6 V
•In accordance with JEDEC standard no. 8–1A
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Synchronous reset
•Synchronous counting and loading
•Two count enable inputs for n–bit cascading
•Positive edge–triggered clock
DESCRIPTION
The 74LVC163 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC163 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q0to Q3) of the counters may be preset to a HIGH or
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D0to D3) to be loaded into the counter on the positive–going edge
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q0to Q3) to LOW level
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE, CET and CEP
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The look–ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set–up time,
according to the following formula:
fmax =1
_______________________________
tp(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; TR = TF 2.5ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH
Propagation delay
CP to Qn
CP to TC
CET to TC
CL = 50 pF
VCC = 3.3V 4.9
5.7
4.5 ns
fMAX maximum clock frequency 200 MHz
CIinput capacitance 5.0 pF
CPD power dissipation capacitance per gate notes 1 and 2 39 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
Σ (CL x VCC2 x fo ) = sum of the outputs
2. The condition is V1 = GND to VCC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
16-Pin Plastic SO –40°C to +85°C74LVC163 D 74LVC163 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +85°C74LVC163 DB 74LVC163 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +85°C74LVC163 PW 74LVC163PW DH SOT403-1
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 3
PIN CONFIGURATION
16
15
14
13
12
11
107
6
5
4
3
2
1
CEP
VCC
Q2
Q3
CET
Q1
TC
Q0
MR
CP
D3
D0
D1
D2
98GND PE
SF00656
LOGIC SYMBOL
CEP CET CP MR
71021
VCC = Pin 16
GND = Pin 8
3
4
5
6
D0
D1
D2
D3
TC
15
9PE
SY00065
Q0
Q1
Q2
Q3
14
13
12
11
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 MR asynchronous master
reset (active LOW)
2 CP clock input (LOW-to-HIGH,
edge-triggered)
3,4,5,6 D0 to D3data inputs
7 CEP count enable inputs
8 GND ground (0V)
9 PE parallel enable input
(active LOW)
10 CET count enable carry input
14,13,12,11 Q0 to Q3flip-flop outputs
15 TC terminal count output
16 VCC positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
31,2 D
1
9M1
4
5
6
14
13
12
11
15
4 CT=15
7G3
10 G4
2C2 /1,3,4+
RCTR4
SY00066
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 4
FUNCTIONAL DIAGRAM
PARALLEL LOAD
CIRCUITRY
BINARY
COUNTER
3456
TC 15
14 13 12 11
Q0Q1Q2Q3
1MR
2CP
7
D0D1D2D3
CEP
CET
10
PE9
SY00068
STATE DIAGRAM
8
7
6
5
4
12 11 10 9
13
14
15
0 1 2 3
SF00664
FUNCTION TABLE
OPERATING INPUTS OUTPUTS
MODES MR CP CEP CET PE Dn Qn TC
Reset (clear) l↑X X X X L L
Parallel load
h↑X X l l L L
Parallel
load
h↑X X l h H *
Count h ↑h h h X count *
Hold h X l X h X qn*
(do nothing) h X X l h X qnL
NOTES:
* = The TC output is High when CET is High and the counter
is at Terminal Count (HHHH)
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High
clock transition
q = Lower case letters indicate the state of the referenced
output one setup time prior to the Low-to-High clock
transition
X = Don’t care
↑= Low-to-High clock transition
TYPICAL TIMING SEQUENCE
CP
PE
TC
MR
INHIBITCOUNT
CEP
CET
D0
D2
D1
D3
Q0
Q2
Q1
Q3
RESET PRESET
12 13 14 15 0 1 2
SY00069
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 5
LOGIC DIAGRAM
Q0 Q1 Q2 Q3 TC
D3D2
D1
D0
CEP
CET
PE
MR
CP
D
CP
Q
Q
D
CP
Q
Q
D
CP
Q
Q
D
CP
Q
Q
SY00074
FF0 FF1 FF2 FF3
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 6
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
UNIT
VCC
DC supply voltage (for max. speed performance) 2.7 3.6
V
V
CC DC supply voltage (for low-voltage applications) 1.2 3.6
V
VIDC input voltage range 0 5.5 V
VODC output voltage range 0 VCC V
Tamb Operating free-air temperature range –40 +85 °C
tr, tfInput rise and fall times VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V 0
020
10 ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +6.5 V
IIK DC input diode current VI 0 –50 mA
VIDC input voltage Note 2 –0.5 to +5.5 V
IOK DC output diode current VO VCC or VO 0 50 mA
VODC output voltage Note 2 –0.5 to VCC +0.5 V
IODC output source or sink current VO = 0 to VCC 50 mA
IGND, ICC DC VCC or GND current 100 mA
Tstg Storage temperature range –65 to +150 °C
Power dissipation per package
PTOT
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
PTOT
– plastic shrink mini-pack (SSOP and
TSSOP) above +60°C derate linearly with 5.5 mW/K 500 mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 7
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
HIGH level In
p
ut voltage
VCC = 1.2V VCC
V
V
IH
HIGH
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 2.0
V
V
LOW level In
p
ut voltage
VCC = 1.2V GND
V
V
IL
LOW
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 0.8
V
VCC = 2.7V ; V I = VIH or VIL; IO = –12mA VCC*0.5
VO
HIGH level out
p
ut voltage
VCC = 3.0V ; V I = VIH or VIL; IO = –100µA VCC*0.2 VCC
V
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
VCC = 3.0V ; V I = VIH or VIL; IO = –12mA VCC*0.6
V
VCC = 3.0V ; V I = VIH or VIL; IO = –24mA VCC*1.0
VCC = 2.7V ; V I = VIH or VIL; IO = 12mA 0.40
VOL LOW level output voltage VCC = 3.0V ; V I = VIH or VIL; IO = 100µA GND 0.20 V
VCC = 3.0V ; V I = VIH or VIL; IO = 24mA 0.55
I
In
p
ut leakage current
;
"01
"5
µA
I
I
Inp
u
t
leakage
c
u
rrent
CC =
.
;
I =
.
"0
.
1
"5
µ
A
ICC Quiescent supply current VCC = 3.6V ; V I = VCC or GND; IO = 0 0.1 10 µA
∆ICC Additional quiescent supply current per
input pin VCC = 2.7V to 3.6V ; VI = VCC –0.6V; IO = 0 5 500 µA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0 V ; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85CLIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT
MIN TYP1MAX MIN MAX TYP
tPHL
tPLH Propagation delay
CP to Qn 1 – 4.9 8.0 – 9.0 24 ns
tPHL
tPLH Propagation delay
CP to TC 1 – 5.7 9.5 – 11 28 ns
tPHL
tPLH Propagation delay
CET to TC 2 – 4.5 7.8 – 8.8 19 ns
tWClock pulse width
HIGH or LOW 1 4.0 1.2 – 5.0 – – ns
tsu Set-up time
Dn to CP 3, 4 2.5 1.0 – 3.0 – – ns
tsu Set-up time
MR, PE to CP 4 3.0 1.2 – 3.5 – – ns
tsu Set-up time
CEP, CET to CP 5 5.0 2.1 – 5.5 – – ns
thHold time
Dn, PE, CEP, CET, MR to CP 3, 4, and 5 0 –1.7 – 0 – – ns
fmax Maximum clock
pulse frequency 1 125 200 – 110 – – MHz
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 8
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V
VM = 0.5 S VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VM
VM
1/fMAX
twtPLH
tPHL
CP INPUT
Qn, TC OUTPUT
SY00071
GND
VI
VOH
VOL
Waveform 1. Clock (CP) to outputs (Qn, TC) propagation
delays, the clock pulse width and the maximum clock
frequency.
VM
tPLH tPHL
CET INPUT
TC OUTPUT
VM
VI
GND
VOH
VOL
SY00072
W aveform 2. Input (CET) to output (TC) propagation delays.
VM
VM
tsu tsu
thth
MR
INPUT
CP INPUT
SC0013
9
VI
GND
VI
GND
W aveform 3. Master reset (MR) pulse width, the master reset
to output (Qn, TC) propagation delays and the master reset to
clock (CP) removal times.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
thth
VM
VM
VM
VI
VI
VI
GND
GND
GND
PE INPUT
CP INPUT
Dn INPUT
tSU tSU
th
tSU th
tSU
SC00137
Waveform 4. Setup and hold times for the input (Dn) and
parallel enable input (PE).
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
VM
VMVM
tsu thtsu th
SC00138
VI
VI
GND
GND
CEP, CET
INPUT
CP INPUT
W aveform 5. CEP and CET setup and hold times.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
RT
VID.U.T.
VO
CL
VCC
500Ω
Open
GND
S1
VCC VI
< 2.7V VCC
TEST S1
tPLH/tPHL Open
2.7V2.7–3.6V
50pF 500Ω
2 * VCC
SV00903
W aveform 6. Load circuitry for switching times.
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 9
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 10
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20 11
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Philips Semiconductors Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
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
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
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or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
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indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04497