April 1996 Edition 2.0 DATA SHEET MB86687A Adaptation Layer Controller (ALC) Adaptation Layer Controller The FUJITSU MB86687A is an ATM protocol controller which autonomously terminates ATM Adaptation Layer standards Type 3/4 and Type 5. The device is ideally suited to applications in a variety of customer premises equipment such as ATM workstation Adaptor Cards and ATM Hubs. The device supports simultaneous segmentation and reassembly on up to 1024 virtual circuits (VCs). PLASTIC PACKAGE SQFP208 FEATURES Supports Broadband ISDN Adaptation Layer standards Type 3/4 and Type 5. Supports simultaneous segmentation and reassembly on up to 1024 VCs. Supports up to 12 peak segmentation rates with leaky bucket averaging on a per VC basis with optional bucket fill before segmentation continues. Programmable peak and average rates and leaky bucket averaging on total ALC cell stream output. PIN ASSIGNMENT Support for scatter / gather mode. Transparent ATM cell and cell payload modes including support for OAM and Resource Management cells. 156 105 157 104 UTOPIA Level 1 v2.01 functionally compatible cell stream interface with optional HEC checking on receive. Flexible routing tag append / remove mode for direct ATM Switch connection. Supports buffer chaining and buffer streaming. Supports buffer ageing time-out. Separate 32 bit data and 16 bit control ports with optimized INDEX 53 208 1 52 DMA interface including 128 circuit cache to reduce DMA bus occupancy. Supports JTAG to IEEE1149.1 Fabricated in sub-micron CMOS technology with CMOS/TTL compatible I/O and single +5V power supply. COPYRIGHT 1996 BY FUJITSU LIMITED This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. MB86687A TABLE OF CONTENTS Edition 2.0 CONTENTS 1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. EXTERNAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Logical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 DMA Controller and SAR Memory Interface . . . . . . . . . . . 9 3.2 Traffic Management Controller . . . . . . . . . . . . . . . . . . . . . . 15 3.3 Segmentation and Convergence Sub-layer Controller . 17 3.4 Reassembly and Convergence Sub-layer Controller . . 21 3.5 Cell Stream Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7 Segmentation and Reassembly Memory Interface . . . . . 27 DEVELOPERS NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 Configuration Control Issues . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Transmit Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 Receive Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3. 4. APPENDICES A. REGISTER TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 B. REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 C. RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 C.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 83 C.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 D. AC TIMINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 E. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 E.1 JTAG Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 F.1 Physical Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 F.2 Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 F. G. i Edition 2.0 TABLE OF CONTENTS MB86687A TABLES Table 1 - Pull Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2 - Single Buffer, Chaining and Streaming Modes . . . . . . . . . . . . . . . . . . . . . 13 Table 3 - JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 4 - Miscellaneous - AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 5 - Cell Stream Interface clocks - AC Timing Parameters . . . . . . . . . . . . . . 85 Table 6 - Cell Stream Interface Fujitsu Mode - AC Timing Parameters . . . . . . . . 86 Table 7 - Cell Stream Interface UTOPIA Mode - AC Timing Parameters . . . . . . . 87 Table 8 - Cell Stream Interface Token Passing - AC Timing Parameters . . . . . . . 88 Table 9 - Microprocessor Interface - AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 10 - Microprocessor Interface - AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 11 - Microprocessor Interface - Intel DMA Access AC Timing . . . . . . . . . . 93 Table 12 - Microprocessor Interface - Motorola DMA Access AC Timing . . . . . . 95 Table 13 - DPR / DMA Interface - Intel Cycle AC Timing . . . . . . . . . . . . . . . . . . . . 98 Table 14 - DPR / DMA Interface - Motorola Cycle AC Timing . . . . . . . . . . . . . . . . 101 Table 15 - Single Cycle Burst - Intel Extended Cycle Timing . . . . . . . . . . . . . . . . . 103 Table 16 - Single Cycle Burst - Motorola Extended Cycle Timing . . . . . . . . . . . . . 105 FIGURES ii Fig. 1 - Possible System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Fig. 2 - ALC External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Fig. 3 - ALC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Fig. 4 - Shared Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Fig. 5 - Transmit Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Fig. 6 - ATM Protocol Data Units (a) AAL3/4 (b) AAL5 . . . . . . . . . . . . . . . . . . . . . . 17 Fig. 7 - Convergence Sub-layer Protocol Data Units . . . . . . . . . . . . . . . . . . . . . . . . 18 Fig. 8 - Cell Stream Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Fig. 9 - Cell Stream Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fig. 10 - UTOPIA Transmit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fig. 11 - UTOPIA Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fig. 12 - CSI Token In/Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fig. 13 - Motorola 32 Bit Mode - Normal Mode Read Timing . . . . . . . . . . . . . . . . . 28 Fig. 14 - Intel 32 Bit Mode - Normal Mode Extended Read Timing . . . . . . . . . . . . 28 Fig. 15 - Intel 486 Mode - Normal Reads Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fig. 16 - Intel 486 Mode Single Cycle Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fig. 17 - Start of Cycle Signal Timing - Fast Mode Extended Read . . . . . . . . . . . 30 Fig. 18 - Transmit Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Fig. 19 - Transmit Data Structures - Address Calculation . . . . . . . . . . . . . . . . . . . 35 Fig. 20 - Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Fig. 21 - Circuit Reference Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MB86687A TABLE OF CONTENTS Edition 2.0 FIGURES (CONTINUED) Fig. 22 - ALC Queue Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Fig. 23 - Transmit Pending Queue Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Fig. 24 - Transmit Buffer Release Queue Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Fig. 25 - Receive Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Fig. 26 - Receive Data Structures - Address Calculation . . . . . . . . . . . . . . . . . . . . 47 Fig. 27 - Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Fig. 28 - Buffer Free Queue Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Fig. 29 - Receive Buffer Ready Queue Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Fig. 30 - ALC REGISTER MAP (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Fig. 31 - ALC REGISTER MAP (2 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Fig. 32 - ALC REGISTER MAP (3 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Fig. 33 - REGISTERS 0, 1 AND 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Fig. 34 - REGISTER 3, 4 AND 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Fig. 35 - REGISTER 6, 7 AND 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Fig. 36 - REGISTERS 9 and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Fig. 37 - REGISTER 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Fig. 38 - REGISTER 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Fig. 39 - REGISTER 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Fig. 40 - REGISTER 15 contd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Fig. 41 - REGISTER 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Fig. 42 - REGISTER 16 contd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Fig. 43 - REGISTER 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Fig. 44 - REGISTER 17 (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Fig. 45 - REGISTER 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Fig. 46 - REGISTER 18 (continued) and 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Fig. 47 - REGISTERS 20 to 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Fig. 48 - REGISTER 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Fig. 49 - REGISTER 33 AND 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Fig. 50 - REGISTER 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Fig. 51 - REGISTERS 40 and 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Fig. 52 - REGISTER 42, 43 AND 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Fig. 53 - REGISTER 45, 46 AND 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Fig. 54 - REGISTER 48, 49 AND 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Fig. 55 - REGISTERS 51 AND 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Fig. 56 - REGISTER 53 AND 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Fig. 57 - REGISTER 55 AND 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Fig. 58 - REGISTER 57 AND 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Fig. 59 - REGISTER 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Fig. 60 - System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 iii Edition 2.0 TABLE OF CONTENTS MB86687A FIGURES (CONTINUED) iv Fig. 61 - Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Fig. 62 - Cell Stream Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Fig. 63 - Cell Stream Interface Transmit Port (Fujitsu Mode) Timing . . . . . . . . . . 86 Fig. 64 - Cell Stream Interface Receive Port (Fujitsu Mode) Timing . . . . . . . . . . 86 Fig. 65 - Cell Stream Interface Transmit Port (Utopia mode) Timing . . . . . . . . . . . 87 Fig. 66 - Cell Stream Interface Receive Port (Utopia mode) Timing . . . . . . . . . . . 87 Fig. 67 - CSI Token Transmit and Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Fig. 68 - Microprocessor Interface - Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Fig. 69 - Microprocessor Interface - Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Fig. 70 - Microprocessor Interface - Write to Write Timing . . . . . . . . . . . . . . . . . . . 91 Fig. 71 - Microprocessor Interface - Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . 91 Fig. 72 - Microprocessor Interface - Intel DMA Access Timing (SYNC) . . . . . . . . 92 Fig. 73 - Microprocessor Interface - Intel DMA Access Timing (ASYNC) . . . . . . 92 Fig. 74 - Microprocessor Interface - Intel DMA Access Control Override Timing 93 Fig. 75 - Microprocessor Interface - Motorola DMA Access Timing (SYNC) . . . . 94 Fig. 76 - Microprocessor Interface - Motorola DMA Access Timing (ASYNC) . . 94 Fig. 77 - DPR / DMA Interface - Intel Read Cycle (SYNC) . . . . . . . . . . . . . . . . . . . 96 Fig. 78 - DPR / DMA Interface - Intel Read Cycle (ASYNC) . . . . . . . . . . . . . . . . . 96 Fig. 79 - DPR / DMA Interface - Intel Write Cycle (SYNC) . . . . . . . . . . . . . . . . . . . 97 Fig. 80 - DPR / DMA Interface - Intel Write Cycle (ASYNC) . . . . . . . . . . . . . . . . . 97 Fig. 81 - DPR / DMA Interface - Motorola Read Cycle (SYNC) . . . . . . . . . . . . . . . 99 Fig. 82 - DPR / DMA Interface - Motorola Read Cycle (ASYNC) . . . . . . . . . . . . . 99 Fig. 83 - DPR / DMA Interface - Motorola Write Cycle (SYNC) . . . . . . . . . . . . . . . 100 Fig. 84 - DPR / DMA Interface - Motorola Write Cycle (ASYNC) . . . . . . . . . . . . . 100 Fig. 85 - Single Cycle Burst - Intel Extended Cycle (SBL=0, SYNC) . . . . . . . . . . 102 Fig. 86 - Single Cycle Burst - Intel Extended Cycle (SBL=0, ASYNC) . . . . . . . . . 102 Fig. 87 - Single Cycle Burst - Motorola Extended Cycle (SBL=0, SYNC) . . . . . . 104 Fig. 88 - Single Cycle Burst - Motorola Extended Cycle (SBL=0, ASYNC) . . . . . 104 Fig. 89 - ALC Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Edition 2.0 1. MB86687A OVERVIEW The ALC simultaneously supports autonomous segmentation and reassembly of user data packets on up to 1024 virtual circuits (VCs). User data packets are transferred to and from shared data structure memory using a high speed intelligent DMA controller with a 32 bit data bus. Shared data structures are stored in SAR (Segmentation and Reassembly) memory which can be either dual port memory or a partition of system memory. Packets for segmentation and packets being reassembled are stored in the SAR memory together with external data structures. These are accessed using the ALC's high speed intelligent DMA controller. In non-demanding applications, system memory can be used as SAR memory. When dual port memory is used the ALC's DMA controller has full access to the SAR memory bus. When system memory is used the DMA controller will negotiate access to a portion of the system bus bandwidth. The ALC provides the user with the facility to partition the shared data structures into dual port memory and user data into shared memory. The DMA controller supports autonomous traffic shaping functions. Up to twelve different peak rate queues can be configured for packet segmentation. In addition each VC can be assigned to either 100%, 50% or 25% of the nominal peak rate. In this way the user can select from one of 36 possible peak rates. Average rate management is in accordance with either the single or double leaky bucket averaging algorithms. Fig. 1 shows three possible system configurations. Adaptation Layer Support The ALC autonomously terminates the protocols involved in segmenting and reassembling data streams conforming to Adaptation Layer Types 3/4 and 5. AAL 3/4 and AAL 5 traffic can be handled simultaneously. Streaming and Message Modes as defined for AAL 3/4 and AAL5 are supported. In Message Mode, the Convergence Sublayer payload (Service Data Unit) is considered to be the user data transmitted from or received into a single entity. A single entity being regarded as one user data buffer or linked chain of user data buffers. In Streaming Mode, the Convergence Sublayer payload is considered to be the user data transmitted from or received into multiple entities separated in time. This allows a partial segmentation or reassembly. In Streaming Mode the chaining of buffers is not supported. The ALC Device supports two transparent modes. In transparent payload mode the 48 byte ATM cell payload is received or transmitted transparently into or from SAR Memory. In transparent cell mode the ATM cell is received or transmitted transparently into or from SAR Memory. 1 MB86687A Edition 2.0 System Configurations In adaptor card applications, the ALC interfaces to the Fujitsu MB86683 Network Termination Controller Device (NTC) (or compatible CCITT I.432 device) via a full duplex 8-bit wide UTOPIA compliant cell stream interface for connection to the transmission medium. Alternatively, it may be connected to a proprietary backplane architecture. To support this application the ALC can be configured to transmit and receive ATM cells with a four byte header minus the HEC field. In Hub or Router applications, the ALC connects directly to the Fujitsu MB86680 Self-routing Switch Element (SRE) for autonomous routing. In this case a programmable Tag of 3 bytes must be appended to each cell. SAR Memory Host CPU NTC or SRE ALC EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE System Memory Host CPU NTC or SRE ALC EEEEEEEEEEEEEEEEEEEEEEEEEEE System Memory Host CPU SAR Memory ALC NTC or SRE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE Fig. 1 - Possible System Configurations 2 Edition 2.0 MB86687A 2. EXTERNAL INTERFACES 2.1 Logical Outline A logical view of the ALC's external pins is illustrated in Fig. 2, and a physical pin assignment is shown in Appendix F. JTAG Test Port TDO TDI TCK TMS SRD0-SRD31 TIN TOUT PRTY0-PRTY3 SRA2-SRA23 TXD0-TXD7 TOCS TDCS ROCS RDCS SAR Memory Interface TXSOC TXCLK TXEN TXFULL TXDRV DS / BLAST / TIP BE0 / A0 BE1 / A1 BE2 / SIZ0 BE3 / SIZ1 Cell Stream Interface ALC RXD0-RXD7 RXSOC MRD / AS / ADS / TS MWR / R/W / R/W RXCLK RXEN RXEMPTY HOLD / BR HLDA / BG BGACK DTACK / READY / BERR SADRV DCCK A1-A6 RESET D0-D15 CS IRQ RD WR Microprocessor Interface Fig. 2 - ALC External Interfaces 3 MB86687A Edition 2.0 2.2 Detailed Description 2.2.1 SAR Memory Interface This interface provides the ALC DMA controller with access to external dual port memory or shared access to system memory. The interface comprises the following signals: Intel mode: BE2 Byte Enable 2 Enables data byte on SRD16 - SRD23. SRD0 - SRD31 Bi-directional SAR memory data bus. Motorola mode: SIZ0. PRTY0 - PRTY3 Bi-directional SAR memory data bus parity protection. BE3 / SIZ1 Multifunction tri-state output. Functions are as follows: SRA2 - SRA23 Most significant 22 bits of the SAR memory address bus. All bits are tri-state outputs. SADRV This input allows the SAR memory interface to be permanently driven. BE0 / SRA0 Multifunction tri-state output. Functions are as follows: Intel mode: BE3: Byte Enable 3 Enables data byte on SRD24 - SRD31, Motorola mode: SIZ1. The coding of the SIZ signals has the following meaning: SIZ1 SIZ0 Meaning Intel mode: BE0 Byte Enable 0 Enables data byte on SRD0 - SRD7, 0 1 Burst of 8 1 0 Word 1 1 Burst of 4 Motorola mode: SRA0 SAR Memory Address bus bit 0. 0 0 Long Word BE1 / SRA1 Multifunction tri-state output. Functions are as follows: Intel mode: BE1 Byte Enable 1 Enables data byte on SRD8 - SRD15. Motorola mode: SRA1 SAR Memory Address bus bit 1. 4 BE2 / SIZ0 Multifunction tri-state output. Functions are as follows: MRD / AS / ADS / TS Bi-function tri-state bi-directional signal. SAR memory read signal (Intel mode), SAR memory address strobe (Motorola mode). This signal is used as an input during Motorola mode bus arbitration and is the ADS signal in extended modes. In extended modes for Intel, it is ADS and Motorola (TS). Edition 2.0 MWR / R/W/ R/W Multifunction tri-state output. SAR Memory write signal (Intel mode), SAR Memory read/write signal (Motorola modes) and read/write (Intel Extended mode). DS / BLAST / TIP Multifunction tri-state output. Data Strobe in Motorola mode; BLAST (last in burst) in Intel extended mode; TIP (transmission in progress) in extended Motorola mode. MB86687A BGACK Bus Grant Acknowledge output indicates ALC DMA controller is assuming control of the bus. READY / DTACK / BERR Ready/Data Transfer Acknowledge input. In standard mode used to terminate DMA / DPR cycles. In FAST mode used to generate an ALC interrupt indicating memory access conflict (Bus error). TOCS Transmit Overhead Cycle Start output. This is asserted before any transmit cycle that is not a data cycle. DCCK, DMA CYCLE CLOCK Clock input used to drive the ALC DMA cycles. TDCS Transmit Data Cycle Start output. This is asserted before a transmit data cycle. The microprocessor interface comprises the following signals: ROCS Receive Overhead Cycle Start output. This is asserted before any receive cycle that is not a data cycle. RDCS Receive Data Cycle Start output. This is asserted before a receive data cycle. HOLD / BR Tri-state Hold/Bus request output used to request bus access for ALC DMA controller. HLDA / BG Hold/Bus Grant input used to pass control of the bus to the ALC DMA controller. 2.2.2 Microprocessor Interface A1-A6 Microprocessor address bus inputs. DATA0-DATA15 Bi-directional microprocessor data bus signals DATA 0-15. CS Microprocessor bus chip select input. RD Microprocessor bus read input. WR Microprocessor bus write input. IRQ Interrupt request output. RESET ALC master reset input. 5 MB86687A 2.2.3 Edition 2.0 Cell Stream Interface This interface comprises the following signals: TXD0-TXD7 These tri-state output signals provide 8 bit parallel transmit data which is cell aligned and asynchronous. To enable daisy chaining of ALCs these signals are tri-state. TXSOC Transmit start of cell sync output. This tri -state output indicates that the first byte of an ATM cell or routing tag is available on the TXD0 - TXD7 data lines. The frequency of this signal depends on the cell transmission rate from the ALC. To enable daisy chaining this pin is tri-state. TXCLK This input signal is used to clock transmit data out of the ALC. The signal can be of arbitrary frequency but should be sufficient to support the bandwidth specified by the ALC traffic shaping parameters. No phase relationship is assumed with RXCLK. TXEN This tri-state output signal is asserted in UTOPIA mode when the cell stream transmit is outputting valid data. 6 RXSOC Receive start of cell sync input. This signal indicates when the first byte of an ATM cell or routing tag is available on the RXD0 - RXD 7 pins. RXCLK This input signal is used to clock received data into the ALC. No phase relationship is assumed with TXCLK. RXEN This output signal is used in UTOPIA mode to control the flow of receive cells when using an external FIFO. The signal indicates that the ALC receive buffers are full. RXEMPTY This input signal is used to control the flow of receive cells when using an external FIFO. The signal indicates that the FIFO is empty. TOUT Token out output. This signal is used to enable daisy chaining. The ALC transmits a `token' pulse on the falling edge of TXCLK to indicate that it has completed a cell transfer or has no data to transmit. The output is held low during cell transmission. TXFULL This input is used in UTOPIA mode to halt the ALC transmit cell stream data. TIN Token In input. This input should be wired to the TOUT output of other ALC devices to form a daisy chain. If unused this pin should be pulled high. RXD0-RXD7 These 8 input pins provide the ALC with 8 bit parallel, cell aligned receive data. TXDRV This input allows the ALC to permanently drive the transmit cell stream interface Edition 2.0 MB86687A 2.2.4 JTAG Test Port TCK JTAG test clock input TDI JTAG test data input TMS JTAG test mode input TDO JTAG test data output SIGNAL PULL VALUE COMMENT The following are essential for correct operation BGACK High 2K7 DMA mode High 10K Dual Port Memory mode IRQ High 2K7 TXSOC Low 10K Only when TXDRV is not asserted TXEN High 10K Only when TXDRV is not asserted HOLD/BR Low 2K7 Only in Intel DMA mode High 2K7 Only in Motorola DMA mode High 10K DMA mode High 100K Dual Port Memory mode HLDA/BG High 10K DS High 100K MRD/AS * The following are not essential, but are advisable TXD0-7 SRD0-31 High/Low 100K Only when TXDRV is not asserted High 100K Only when SADRV is not asserted The following can be omitted if the data bus can be guaranteed not to float between 2.2v and 0.8v. MWR/R/W High 100K * BE0/A0 High 100K * BE1/A1 High 100K * BE2/SIZ0 High 100K * BE3/SIZ1 High 100K * A2-21 High 100K * Note: * - These signals are continuously driven when Dual Port Ram mode is selected or SADRV is asserted. Table 1 - Pull Values 7 MB86687A 3. Edition 2.0 FUNCTIONAL DESCRIPTION This section describes the behaviour of each major functional block within the ALC, as illustrated in Fig. 3. The descriptions in this section are from a user's perspective and are intended to give a detailed description of device functionality and modes of operation. The ALC comprises the following major components: Transmit and Receive Buffers, Segmentation and Sub-layer Controller, Convergence Reassembly and Sub-layer Controller, Convergence Cell Stream Interface, Microprocessor Interface, High Speed DMA Controller, Traffic Management Controller, Transmit Buffer ( 3 Cells ) SAR Memory Interface Segmentation and Memory Interface. Segmentation & Convergence Sub-layer Controller Reassembly ATM Cell Transmitter Cell Stream Interface Traffic Management Controller High Speed DMA Controller Receive Buffer ( 2 Cells ) Reassembly and Convergence Sub-layer Controller ATM Cell Receiver VCI Status/ Descriptor Table ALC Internal Registers Cell Stream Interface Processor Interface Fig. 3 - ALC Block Diagram 8 Edition 2.0 MB86687A 3.1 DMA Controller and SAR Memory Interface 3.1.1 General The ALC contains an intelligent DMA Controller to manage the segmentation and reassembly of user data packets using the minimum of host processor intervention. Communication with the host processor is mainly through shared data structures in either dual port or system memory. The system implications of a dual port or system memory approach are largely performance related. 3.1.2 Shared Data Structures The shared data structures used to control the segmentation and reassembly of user data are shown in Fig. 4 on page 10. The transmit side is controlled via the Transmit Pending Queue, the Transmit Descriptor Table, the Circuit Reference Table and the Transmit Buffer Release Queue. The ALC uses reserved fields in the Transmit Descriptor to compose peak rate queues for segmentation at the specified peak rate and for leaky bucket averaging. The host can program up to 12 peak rates for the ALC. The receive side is controlled by the Receive Buffer Free Queue, the Receive Descriptor Table and the Receive Buffer Ready Queue. In addition the DMA Controller uses an internal RAM table, the Receive Status / Descriptor Table to store receive VCI status and descriptor identifiers. The purpose of each of these tables is described below. 3.1.3 Transmit Data Structures The host writes commands to the Transmit Pending Queue to instruct the ALC to queue a data packet for segmentation. The packet can be queued for transmission on one of 12 peak rate queues. Each Transmit Pending Queue entry contains a pointer to a Transmit Descriptor in the Transmit Descriptor Table. The Transmit Descriptor Table is composed of up to 4096 descriptors. Each descriptor contains a pointer to data for segmentation. The reserved fields in the Transmit Descriptor are used by the ALC to construct queues of transmit packets for each selected peak rate. The Transmit Descriptor also contains a pointer to an entry in the Circuit Reference Table (CRT). The CRT is composed of up to 1024 entries, one entry for each active Virtual Circuit. Each entry contains fields for the ATM cell header, an optional routing tag, and the leaky bucket parameters for the virtual circuit. The ALC reads the cell header and the leaky bucket parameters from the CRT each time a cell is segmented from a transmit buffer. Management of the Peak Rate segmentation queues is handled autonomously by the ALC. The only host intervention required is on a per packet basis. To queue a packet the host constructs the relevant descriptor and writes the pointer to the descriptor into the Transmit Pending Queue. Transmit descriptors are recovered by the host by reading the Transmit Buffer Release Queue. 9 MB86687A Edition 2.0 SAR MEMORY ALC CIRCUIT REFERENCE TABLE TRANSMIT PENDING QUEUE ALC READ ENTRY 0 HOST WRITE 1023 TX BUFFER RELEASE QUEUE HOST READ TRANSMIT DESCRIPTOR TABLE ALC WRITE TRANSMIT BUFFER ADDRESS Private ALC working space for Peak Rate Management and Leaky Bucket Averaging QUEUE H1 CR = a ALC DMA Packets Queued For Segmentation At Peak Service Rate H1 CR = b CR = b SEGMENTING WAITING DATA QUEUE H2 QUEUE L4 CR = x CR = x CR = n CR = z CR = z SEGMENTING WAITING Packets Queued For Segmentation At Peak Service Rate L4 QUEUE L3 CR = Circuit Reference ENTRY 0 RECEIVE BUFFER READY QUEUE RECEIVE BUFFER FREE QUEUE HOST READ ALC WRITE HOST WRITE ALC READ ENTRY 1023 RECEIVE VCI STATUS TABLE RECEIVE DESCRIPTOR TABLE ENTRY 0 RECEIVE BUFFER 1023 Fig. 4 - Shared Data Structures 10 Edition 2.0 MB86687A After a packet has been transmitted, the ALC will return the Transmit Descriptor used to the host via the Transmit Buffer Release Queue. Each entry in this queue contains a pointer to the relevant descriptor in the Transmit Descriptor Table. 3.1.4 A more detailed description of the shared data structures is provided in Section 4, Developers Notes, of this datasheet. Receive Data Structures At the start of reassembly for each new packet the ALC finds a new Receive Descriptor (RD) by reading the Receive Buffer Free Queue. Each entry contains a pointer to a RD in the Receive Descriptor Table. The Receive Descriptor Table is composed of up to 4096 RDs. Each RD contains a pointer to a receive buffer. The RD also contains fields to support receive buffer chaining and the received VCI or MID fields. A reserved field in the RD is used by the ALC to support a receive buffer ageing timeout. VCI = N Vertical Queue (Different VCs) VCI = M VCI = L After reception is complete, the ALC passes the receive descriptor to the host using the Receive Buffer Ready Queue. Each entry in the queue contains a pointer to the appropriate RD and the status of the receive buffer. 3.1.5 Packet Segmentation The DMA Controller is responsible for linking transmit descriptors into one of the 12 service rate queues. The queues are composed of a linked list of TDs. The structure of each of the service rate queues is shown in Fig. 5. When the ALC reads a transmit packet command from the Transmit Pending Queue, it links the packet into the service rate queue specified in the appropriate Circuit Reference Table entry (see Fig. 20 on page 36). VCI = N VCI = N Horizontal Queue (Same VCs) VCI = L Fig. 5 - Transmit Queue Structure 11 MB86687A Packets with the same circuit reference, ie same VPI/VCI or MID are queued horizontally. Packets with different circuit references for transmission on the same service rate queue are queued vertically. Horizontally queued packets will be serviced when the packet at the front of the queue is completed. Each service rate queue is serviced vertically at the specified peak rate under the control of the Traffic Management Controller. A queue entry has been serviced when a complete SAR-PDU payload of either 44 or 48 bytes has been read from the packet. The queue has been serviced when each queue entry linked vertically has been serviced. Message Mode Operation In Message Mode, the user data buffer associated with a Transmit Descriptor will contain the full CS-PDU payload to which the CS-PDU header and trailer will be added to terminate the protocol. 12 Edition 2.0 Table 2 describes single buffer, chaining and streaming modes for the ALC. It should be noted that the transmit and receive sides work independently. Transmit operation is controlled by the Transmit Descriptor on a packet by packet basis. The whole receive side is controlled by Control Register17 (see Fig. 43 in Appendix B.). 3.1.6 Packet Reassembly The DMA Controller maintains the status of each receive connection using the internal Receive Descriptor / Status table. This table is accessible to the host for initialisation purposes, diagnostics and support for scatter/gather mode. The host must activate each connection using the host access registers 57 to 59 (Fig. 58 & Fig. 59). The AAL type and ACT bits must be initialised to the required value. Alternatively, the CS-PDU payload may be spread across several user data buffers when the host passes a chain of TDs to the ALC. The CS-PDU header will be added to the first user data buffer in the chain. The ALC will work through the chain until the CHAIN END bit is cleared (CE = 0) and then the CS-PDU trailer will be added. Message Mode Operation In Message Mode, the user data buffer associated with a Receive Descriptor will contain the full reassembled CS-PDU payload. Streaming Mode Operation In Streaming Mode, a partial segmentation can be accomplished. This allows the user data unit to be partially received into SAR memory and for segmentation to commence before the whole unit is received. Alternatively, the CS-PDU payload may be spread across several user data buffers when the host programs the ALC for receive buffer chaining operation. The head of the chain of buffers will be passed back to the host when the end of message is received. If the size of this payload exceeds the buffer size the buffer will be returned to the host with a buffer overflow indication. Edition 2.0 MB86687A Streaming Mode Operation (PR) The size of the CS-PDU payload may be much greater than the size of one receive data buffer. In addition, the memory resource as a whole may be limited or the user may require that sections of the CS-PDU be forwarded to the host as soon as they fill each buffer. This partial reassembly is accomplished by programming the ALC for streaming mode operation. Buffer Chaining is not possible when the streaming mode register bit has been programmed. MESSAGE MODE STREAMING MODE OPERATION DIR SINGLE BUFFER CHAINING Queue Packet Tx M=0, CS=0, CE=0 Whole packet in single buffer M=0 CS 1st buffer=0 CS other buffers=1 CE last buffer=0 CE other buffers=1 M=1, CS=0 in first buffer CE=0 Add buffers via TPQ * Tx NA NA M=1 in extra buffers M=0 in last buffer CE=0 Release buffer Tx When packet Tx complete Released on a buffer by buffer basis (-> TRBQ) Released on a buffer by buffer basis (-> TRBQ) Start Rx Re-assembly BCHAIN=O, SMODE=O Get next BFQ entry BCHAIN=1, SMODE=0 Get next BFQ entry BCHAIN=O, SMODE=1 Get next BFQ entry Buffer full Rx Error buffer overflow Get next BFQ entry Link buffers Get next BFQ entry Release buffer to host (-> RBRQ) Packet complete Rx Release buffer to host Release first buffer to host (-> RBRQ) ** Release buffer to host (-> RBRQ) Notes: * In Transmit Streaming mode the host must queue all current packet buffers on any given circuit before starting a new packet. ** In Receive Chaining the host will be given the descriptor reference of the first buffer in the chain. The host must follow the chain until the condition V=0 is set in the descriptor. Table 2 - Single Buffer, Chaining and Streaming Modes 13 MB86687A Buffer Ageing Support Buffer Ageing support is programmed by setting bit D12 (BAS) in Register 17. If set, upon reassembling the first cell of a packet, the ALC stamps a time base in the RD. On reassembly of further cells for the same packet, the ALC compares the time elapsed against the value programmed in Register 52 - Receive Buffer Timeout Counter Register. If the difference is greater than the value in this register, the RD is returned to the Buffer Ready Queue with a code `1100' indicating Buffer Timed Out - Reassembly Aborted. The rest of the packet will be discarded by the ALC. For a greater time range, Register 51 - Receive Buffer Timeout Counter Period Register - can be programmed. This scales the DCCK used to increment the time base counter. For example, a DCCK at 25MHz provides a time range up to 170 seconds. 14 Edition 2.0 Buffer Ageing Support is only available in Message Non-Chaining mode. Maximum Packet Length At the start of cell reassembly, the ALC compares the value of Bytes Received accumulated in the RD with the value programmed in Register 54 - Maximum Received Packet length Register. If the register value is exceeded, the ALC writes out the RD to the Buffer Ready Queue with a code `1001' indicating Receive Maximum Length Exceeded. For Message Chaining mode, the ALC compares the accumulated value of Bytes Received to date across the chain at the moment of adding a further RD to the chain. Maximum Packet Length checking is not supported in Streaming mode. Edition 2.0 3.2 MB86687A Traffic Management Controller The Traffic Management Controller is responsible for the following functions: Initiate periodic packet segmentation from one of the 12 Peak Rate Queues at intervals specified in the Queue Service Rate registers. The queues are grouped into three priority classes: high, medium and low, with 4 queues in each priority class. Manage total ALC peak transmission rate. If the total peak transmission rate exceeds a specified threshold, the traffic management controller will service the queues according to their priority until the total peak rate falls below the threshold. This feature can be used to ensure that the ALC will not exceed the negotiated quality of service for the overall link connection. Manage average rate shaping of transmit traffic on a per virtual circuit basis using the leaky bucket algorithm. The leaky bucket parameters for this are supplied from the Circuit Reference Table referenced in the Transmit Descriptor. Manage average rate shaping on the total ALC transmission according to the leaky bucket algorithm. The leaky bucket parameters for this averaging are determined by the ALC Peak Cell Transmission and ALC Average Cell Transmission registers. This feature is also used to ensure that the ALC will not exceed the quality of service for the overall connection. 3.2.1 Peak Rate Queue Service Requests The ALC peak rate queue service control logic is responsible for requesting the transmission of cells queued to the peak rate queues on a per virtual circuit basis. Twelve programmable counters are used to specify the peak transmission rate for each queue. The twelve counter values are programmed using the Queue Service Rate Registers and enabled using the Queue Enable Registers. The counter is clock TXCLK (for TXCLK period, see Appendix C.) which can be pre-scaled to increase it's dynamic range. The peak service rate value is used to determine the frequency of access to the respective peak rate queue. Each time the queue is accessed one cell may be transmitted for each queued entry (one per VC) if a leaky bucket token is available for that queue entry. Each Circuit Reference Table contains a sub rate select field which can be used to further reduce the peak cell transmission rate to 50% or 25% of the nominal peak rate specified in the Queue Service Rate Register. This gives a total available range of 32 effective peak transmission rates for entries of each peak rate queue. 3.2.2 Total ALC Peak Rate Control The ALC contains link capacity control logic which is used to ensure that the overall ALC link transmission rate does not exceed a pre-programmed value as specified in the ALC Peak Cell Transmission Rate register. 15 MB86687A Edition 2.0 If the overall required transmission rate exceeds this programmed value, the link capacity controller will mask the lower priority queues. This will cause cell transmission to cease on the low priority queues until the overall peak rate falls below the programmed total ALC value. Note that the queues are masked in the following priority: All four L queues followed by all four M queues. 3.2.3 Per VC Leaky Bucket Traffic Shaping The leaky bucket algorithm is used to shape the transmit data characteristics on a per virtual circuit basis by controlling the average rate of cell transmission and the length of each burst of cells generated. The leaky bucket parameters are determined by the values in the Circuit Reference Table for each active VC. (See section 3.1.3, Transmit Data Structures). The parameters relevant to leaky bucket management are the user programmable parameters, Bucket Capacity, M and the Bucket Utilization, U. The bucket capacity is used to calculate the maximum sustained burst of cells at the specified peak rate. The average rate of emptying the bucket is derived from the utilisation. The utilisation is expressed as a fraction of the peak rate. See section 4 on ALC configuration and control for full details. 16 Two modes of operation are supported: single leaky bucket mode and double leaky bucket mode. In single leaky bucket mode, cells are transmitted in an initial burst as defined by M at the specified peak rate. The burst length may exceed the bucket capacity since tokens are added to the bucket at the same time as tokens are removed. Subsequent cells are transmitted at the average rate as tokens are added to the bucket. In double leaky bucket mode, cell transmission will only occur in bursts at the peak rate when the bucket associated with that VC is full of tokens. 3.2.4 Total ALC Leaky Bucket Traffic Shaping In addition to the traffic shaping applied to the traffic transmitted from each virtual circuit the ALC can manage both the peak and average transmission rate on the total ALC output traffic. A total ALC Leaky bucket size is defined in the ALC Leaky Bucket Capacity Register. This capacity value is used in conjunction with the leaky bucket utilization to limit the ALC output burst length. The total ALC utilisation value is derived from the ALC Peak Cell Rate and ALC Average Cell Rate Register contents. Edition 2.0 MB86687A 3.3 Segmentation and Convergence Sub-layer Controller This block is responsible for managing the transmission of cells according to the specified Adaptation Layer protocol: AAL3/4 or AAL5. 3.3.1 ST, Segment Type The first SAR-PDU generated from a user data packet carries the Beginning of Message (BOM) code 10. Subsequent SAR-PDUs carries the Continuation Of Message (COM) code 00. SAR Sub-layer functions Fig. 6 shows the format of SAR Protocol Data Units (SAR-PDU ) for AAL types 3/4 and 5. The following protocol actions are performed on each SAR-PDU for AAL 3/4: Preservation of SAR service data unit integrity through generation of the segment type field, Error Protection through Sequence Number and CRC generation, Multiplexing/Demultiplexing using the Multiplexing ID, Support of the Abort function. The fields of AAL Type 3/4 are detailed in the following text. The final SAR-PDU carries the End of Message (EOM) code 01. SAR-PDUs which carry entire SAR-SDUs such as those defined for signalling carry the Single Segment Message (SSM) code 11. SN, Sequence Number The four bits of this field are used for modulo 16 numbering of each SAR-PDU. The Sequence Number is set to zero at the start of each SAR-SDU. MID, Multiplexing Identification This field is used for multiplexing multiple CS-PDU (Convergence Sub-layer Protocol Data Units) connections on a single ATM layer connection. When MID mode is selected, this field carries the MID specified in the Circuit Reference Table. The MID field is set to zero when multiplexing is not used. SAR-PDU Header CELL HEADER ST 5 bytes CELL HEADER 5 bytes SN 2 4 bits bits SAR-PDU Trailer MID SAR-PDU Payload LI CRC 10 bits 44 bytes 6 bits 10 bits SAR-PDU (a) (b) 48 bytes Fig. 6 - ATM Protocol Data Units (a) AAL3/4 (b) AAL5 17 MB86687A Edition 2.0 LI, Length Indicator This field indicates the number of bytes contained in the SAR-PDU. The SAR-SDU bytes are left justified within the SAR-PDU payload field and remaining bytes will be set to 0. 3.3.2 Convergence Sub-layer Functions Fig. 7, below, shows how the user data is formatted in the convergence sub-layer before segmentation. The ALC maintains internal tables to manage AAL3/4 sequence numbers and AAL5 CRC results. CRC, Cyclic Redundancy Check This field contains the 10 bit CRC code. It is calculated (as defined in CCITT I.363 for AAL3/4) over the SAR-PDU including header, trailer, payload and length indication. The fields of the CS-PDU header and trailer are listed and described on the following pages. (a) AAL3/4 CS-PDU header CS-PDU trailer CPI Btag BASize CS-PDU Payload PAD AL 1 1 byte byte 2 bytes 0 - 64k bytes 0-3 bytes 1 byte CPI: Btag BASize AL Etag Etag LENGTH 1 byte 2 bytes Common Part Identifier Beginning Tag Buffer Allocation Size Alignment End Tag (b) AAL5 CS-PDU trailer CS-PDU Payload 0 - 64k bytes CONTROL FIELD PAD 0-47 bytes 2 bytes CPCS-UU CPCS-UU: CPI: Length: CRC: LENGTH 2 bytes CRC 32 4 bytes CPI CPCS User to User Indication Common Part Identifier Length of CPCS-SDU Cyclic Redundancy Check Fig. 7 - Convergence Sub-layer Protocol Data Units 18 Edition 2.0 AAL 3/4 HEADER AND TRAILER CPI, Common Part Identifier This field is coded to all zeros to indicate that the values in BASize and Length Fields are measured as unit multiples of bytes. BTAG, ETAG, Beginning & End Tags These Fields are given the same modulo 256 value for each CS-PDU and incremented on successive CS-PDUs. The receiver will check that they are the same value on a CS-PDU to CS-PDU basis but will not check for incrementation over successive CS-PDUs. BASize, Buffer Allocation Size This value will be the size of the CS-PDU payload when Message Mode Service is being run. In Streaming Mode this value may be greater than or equal to the CS-PDU payload size. Its purpose is to inform the receiving entity of the buffering required to accommodate the transmitted data. AL, Alignment No information is conveyed by this field. It merely provides 32 bit alignment in the CS-PDU trailer. The Pad field has the effect of making the CS-PDU an integral multiple of 4 bytes. Length Length of CS-PDU payload. PAD, Padding Field This field complements the CPCS-PDU to an integral multiple of 4 bytes and conveys no information. MB86687A AAL 5 TRAILER For AAL 5 the CS-PDU has no header. The trailer is derived from the data structure and the 32 bit CRC stored in the convergence sub-layer table. The fields of the CS-PDU trailer are listed below. PAD, Padding Field The purpose of the PAD bytes is to align the CS-PDU trailer into the last 8 bytes of a SAR-PDU. If this calculation results in the transmission of an extra cell it is not transmitted back to back with the previous SAR-PDU, as this would compromise the transmission rate and the Traffic Management Controller parameters. Control Field The Control Field comprises 2 fields shown in Fig. 7. These fields are: CPCS-UU This field is used to transparently transfer CPCS user to user information. CPI This field is used to align the CPCS_PDU to 64 bits and should be coded as zero. Length Length of CS-PDU payload. CRC, Cyclic Redundancy Check The CRC field is filled with the value of a CRC calculation (as defined in CCITT I.363 for AAL 5) which is performed over the entire contents of the CS-PDU. This includes the payload, the PAD field, and the first four bytes of the trailer. The initial CRC remainder is preset to all ones before generation and checking. 19 MB86687A 3.3.3 Edition 2.0 Error Recovery & Notification The ALC provides provisions for sending SAR-U-ABORT ATM Cells in streaming mode in accordance with the selected protocol. In accordance with AAL5 protocol the ABORT SAR-PDU is defined as SDU=1, LENGTH FIELD coded to zero and CRC32 correct. In accordance with AAL3/4 protocol the ABORT SAR-PDU is defined by ST= EOM, payload coded to zero, and LI = 63. The CRC-10 and MID field must be valid. 3.3.4 Transparent Modes Transparent Cell Mode In this mode the host provides cells of 52 bytes (4 header and 48 data) in a transmit descriptor to the transmit pending queue. The transmit side generates and includes the HEC byte (if mode register 17 bit D9 = 0) and transmits the resulting 53 byte cell with an optional CRC10 included otherwise no further protocol carried out. On receiving a transparent cell the receive side checks and removes the HEC byte before loading the remaining 52 bytes into the internal receive buffer. The receive side DMA then obtains a descriptor from the buffer free queue, writes all 52 bytes into the buffer and then writes out the descriptor to the buffer ready queue. 20 Note that the only updated field within the receive descriptor is the VCI field (the bytes received is not updated as it is always 52). Transparent Payload Mode In this mode the host provides a multiple of 48 bytes of cell payload data within a single transmit descriptor to the transmit pending queue. The header information is obtained from the Circuit reference table, a HEC byte is generated (if mode register 17, bit 9 = 0) and the cell is transmitted. As with transparent cell mode, apart from including an optional CRC10, no further protocol is performed. The receive operation is also similar to transparent cell mode but with only the 48 payload bytes being transfered by DMA to SAR memory. The CRC 10 can be checked if the cell is detected to be an OAM or Resource management cell. Edition 2.0 3.4 MB86687A Reassembly and Convergence Sub-layer Controller This block is responsible for managing the reception of cells according to the specified Adaptation Layer protocol: AAL3/4 or AAL5. The following adaptation layer functions are performed on a SAR-PDU basis: Preservation of SAR service data unit. Checking the Segment Type Field, Error Detection and Handling. CRC and Sequence Number Integrity Checking, TXD[0-7] Tag (0-3 bytes) Multiplexing / Demultiplexing using the MID field, Support of the Abort Function. The following adaptation layer functions are performed on a CS-PDU basis: Detection of BTag, ETag fields, Detection of Incorrect Length Field, Detection of Alignment errors, Detection of errors using CRC 32 calculation. Tag (0-3 bytes) ATM Cell (52 or 53 bytes) TXSOC TXCLK 52 to 56 clock cycles RXD[0-7] Tag (0-3 bytes) idle period (n clock cycles, n > or = 0) Tag (0-3 bytes) ATM Cell (52 or 53 bytes) RXSOC RXCLK 52 to 56 clock cycles idle period (m clock cycles, n > or = 0) Fig. 8 - Cell Stream Interface 21 MB86687A 3.5 Edition 2.0 Cell Stream Interface The Cell Stream Interface will transmit and receive an asynchronous stream of ATM cells. Cells will be transmitted and received in 8-bit parallel form with separate synchronisation signals used to identify the start of a cell. The ALC cell stream interface may be required to operate in one of two environments either in a Switch Device or a Termination Device. 3.5.1 Termination Device Operation In termination device operation the ALC is intended to connect to the Fujitsu MB86683 Network Termination Controller or equivalent device for physical media interfacing. Cells are transmitted and received header to trailer or with an idle period between each cell, see Fig. 8. The idle period may be of any number of clock cycles including zero. There is no relationship between the transmit and receive sync pulses. 3.5.2 Switch Device Operation In switch device operation, for example in hub and router applications, the ALC can be connected directly to an ATM switch fabric port such as the Fujitsu MB86680 Self-routing ATM Switch Element, or to a proprietary backplane structure. 22 In this environment the ALC will append a programmable routing Tag of up to 3 bytes to the start of each cell. In the receive direction the Tag is removed before protocol processing of the cell commences. In addition, the HEC field can optionally be omitted resulting in a 52 byte cell. Switch Device timing is also shown in Fig. 8. 3.5.3 Cell Stream and UTOPIA The Fujitsu Cell Stream mode has been superceded by the UTOPIA specification from the ATM Forum, but is still supported for backward compatibilty. The mode selection is performed by tying the CS/UT pin high or low as required. By default, Fujitsu cell stream is selected by an internal pull-up resistor. 3.5.4 Utopia Flow Control Forward and backward byte-level flow control is supported in both directions. The forward flow control signal indicates the validity of the current data. The backward flow control signal indicates whether data will be accepted in a particular cycle. Neither flow control signal is directly qualified by the other : they can change state independently. Unused flow control inputs should be tied off to their active levels. All signals are transmitted and sampled on the rising edge of the clock. Timings for UTOPIA are illustrated in Fig. 10 and Fig. 11. Note that all of the flow control signals can change state independently. Edition 2.0 3.5.5 MB86687A Cell Stream Flow Control 3.5.6 In Cell Stream mode the ALC will provide an indication that its receive buffer is full by using the RXEN output signal as shown in Fig. 9. The other flow control signals are not supported in Cell Stream mode. Unused flow control inputs should be tied off to their active levels. Loopback When loopback is enabled (by setting the TSTLP bit in CR16) the transmit data is internally looped back into the receive path. For this operation TXCLK must be present but RXCLK need not be. The transmit data will still appear on the transmit interface. Flow control is handled in loopback only in UTOPIA mode. RXCLK RXD0-7 RXSOC Invalid RXEN Fig. 9 - Cell Stream Receive Interface Timing TXCLK TXD0-7 TXSOC Invalid Invalid Invalid TXEN TXFULL Fig. 10 - UTOPIA Transmit Interface Timing RXCLK RXD0-7 RXSOC Invalid Invalid Invalid RXEMPTY RXEN Fig. 11 - UTOPIA Receive Interface Timing 23 MB86687A 3.5.7 Edition 2.0 Transmit Multiplex Operations and places its TXD and TSN pins in high impedance. A token passing mechanism is used when more than one ALC share the same cell stream interface. In this case the ALC should be wired in a daisy chain configuration using the TIN (Token In) and TOUT (Token Out). This mechanism is illustrated in Fig. 12. TIN should be connected to the TOUT output of an ALC higher up the daisy chain. When the TIN input is inactive (low), the ALC stops transmitting data The ALC will transmit a Token pulse, on TOUT, on the falling edge of TXCLK to indicate that it has completed a cell transfer or that it has no data to transmit. Note that if one ALC is able to transmit cells continuously on this interface (ie. no gaps between cells) TOUT will only pulse at the end of a cell if TIN is inactive one clock period before the last byte in the cell. TOUT timing at the end of a Cell TXCLK TXD Byte 52 Byte 53 TOUT TIN timing at the start of a Cell (2 ALCs Daisy Chained) TXCLK TXD Byte 1 Byte 2 TIN (TOUT ALC2) TOUT TXSOC Fig. 12 - CSI Token In/Out Timing 24 Edition 2.0 3.5.8 MB86687A TXDRV (TX cell stream Drive): Earlier ALC devices needed pull down resistors on the TX cell stream interface because the selection of Cell Stream Daisy Chaining was controlled by a register. Using the TXDRV signal on MB86687 allows these resistors to be omitted. This mode is selected by tying the TXDRV pin low. By default, it is deselected by an internal pull-up resistor and the register controls the operation. 3.5.9 Receive Circuit Reference and VPI/VCI Filter Mechanism The ALC constructs a 10 bit receive circuit value depending on the setting of the RID bit in register 17. RID 0 Receive Circuit Reference value is equal to VPB least significant bits of the VPI field concatenated with (10-VPB) least significant bits of the VCI field where VPB is the value of VPI bits to be used in the receive address mapping, specified by bits VPB2, VPB1 and VPB0 in register 16. AF17-AF14 matched with VPI11-VPI8 for NNI mode. AF17-AF14 are not considered for UNI mode. AF13-AF0 matched with unused VPI bits concatenated with unused VCI bits. For VPI filter inactive (VPF=0) the mask bits for the unused VPI bits must be cleared to zero. RID 1 Receive Circuit Reference is equal to the value in the MID field (AAL3/4 only). The Receive Circuit Reference value should be used during programming register 59 when enabling receive channels. When re-assembling a packet, this value is loaded into the receive circuit reference field in the receive descriptor. The ALC performs filtering on the VPI and VCI bits not used for the receive circuit value. Bits AF17 and AF16 in register 16 together with bits AF15 - AF0 in register 56 make up the mask value to be used to filter incoming cells. Programming of the mask bits AF17-AF0 is dependent on the settings of the UNSEL bit in register 16 and the VPF bit in register 17. 25 MB86687A 3.6 Edition 2.0 Microprocessor Interface The Microprocessor Interface is responsible for supporting the following functions: Providing Host Processor access to all programmable ALC registers, Providing the Host Processor initialisation / test access to the Receive Status / Descriptor Tables, Managing the mechanism. 26 ALCs interrupt 3.6.1 Interrupt Controller The ALC will indicate certain abnormal conditions using the Interrupt signal. The cause of an interrupt is provided in the Interrupt status register. Each interrupt condition can be individually masked to prevent external interrupt signal generation. A full description of each interrupt source is given in Appendix B., Fig. 45 and Fig. 46 as part of the interrupt status register description. Edition 2.0 MB86687A 3.7 Segmentation and Reassembly Memory Interface 3.7.1 Features The SAR interface is responsible for accessing queues, tables and data stored in either dedicated dual port memory or within the host system memory. The SAR interface can support the following features: Motorola or Intel compatible bus cycles Examples of Motorola and Intel Mode Normal Read cycles are shown in Fig. 13 and Fig. 14 respectively. Extended Intel (486) & Motorola (040) modes. These modes allow Single Cycle data bursts. Examples of the Intel extended normal and burst read cycles are shown in Fig. 15 and Fig. 16 respectively. Addressing Schemes Little or Big Endian addressing schemes in Intel mode; Big Endian addressing schemes in Motorola mode. Other Features Direct connection to Dual Port RAM; Bus arbitration as required in DMA mode; DMA burst length limiting in the range 1 to 255 memory cycles. READY/DTACK extended cycles in Ready dependent SAR memory mode. Memory contention interrupt generation in response to READY/DTACK transition when using Fast Cycle Mode. SADRV ( TX cell stream Drive) - Using the SADRV signal on MB86687 allows pull-up resistors to be omitted. Earlier ALC devices needed pull-up resistors on all the address and control signals because the selection of DPR or DMA modes was controlled by a register. This mode is selected by tying the SADRV pin low. By default, it is deselected by an internal pull-up resistor and the register controls the operation. 27 MB86687A Edition 2.0 DCCK A0 - 23 SIZ0-1 **CS R/W AS DS DTACK DATA Fig. 13 - Motorola 32 Bit Mode - Normal Mode Read Timing DCCK A0 - 23 BE0-3 **CS RD BLAST READY DATA Fig. 14 - Intel 32 Bit Mode - Normal Mode Extended Read Timing READY is sampled on the falling edge of DCCK at the end of state 3. The example shown uses a synchronous READY signal. 28 An asynchronous READY signal takes one extra clock cycle to take effect due to internal synchronisation. Edition 2.0 MB86687A DCCK A0 - 23 BE0-3 **CS R/W ADS BLAST READY DATA Fig. 15 - Intel 486 Mode - Normal Reads Timing DCCK ADDR BE0-3 **CSn **CSn+1 R/W ADS BLAST READY DATA Fig. 16 - Intel 486 Mode Single Cycle Burst Timing 29 MB86687A Edition 2.0 3.7.2 Start of Cycle Signals There are four start of cycle signals. They are as follows :- TOCS Transmit Overhead Cycle Start output. TDCS Transmit Data Cycle Start output. ROCS Receive Overhead Cycle Start output. RDCS Receive Data Cycle Start output. These start of cycle signals are asserted before the associated operation. In normal mode, this will be one clock cycle before the next operation. In Ready Dependent mode where cycles are back to back, the signal will be asserted during the second clock of the previous cycle. In shared memory systems, this period may be indeterminate because an active start of cycle may be asserted for an operation that will occur after the bus has first been released and then regained. When stealing or forced bursting is enabled a single start of cycle pulse may precede a group of consecutive operations of the same type. DCCK TDCS TOCS RDCS ROCS ADDRA MRD MWR DATA Memory Data ALC Data Fig. 17 - Start of Cycle Signal Timing - Fast Mode Extended Read Parity Bits Parity generation and detection on a per byte basis is supported on the SAR memory interface using four bi-directional signals. 30 Edition 2.0 MB86687A A register bit determines if the parity generation/ checking is to be odd or even. If a parity error occurs an interrupt is generated. This interrupt cannot be disabled. The ALC does not drop bytes, it purely informs the host that an error has occurred. 3.7.3 DMA Cycle Optimisation The ALC can be programmed to change the cycle ordering on its DMA interface to be optimal for different system configurations This is achieved by progressively setting more bits in the most significant word of the DMA Mode Register. The settings are as follows:- 0H - cycles are compatible with 86A ready dependent cycles. 1H - cycles are compatible with 86A fast cycles with stealing on data cycles only. 7H - cycles are optimised for dual port RAM systems with stealing of data and overhead cycles. 1FH - cycles are optimised for shared memory systems where there may be different memory partitions. The cycles will be grouped according to their type. 3.7.4 Transmit DMA CACHE The ALC uses shared or private memory to create and maintain queues of data packets, packet segmentation information and traffic management data. To reduce the number of overhead cycles used to access these, a caching mechanism may be used whereby the parameters for up to 128 circuits can be stored on-chip. The cache is operated in the following way and requires a small processor overhead to maintain a table of cached entries. The host software assesses the traffic requirements of each circuit and makes a decision about which circuits would benefit being in the cache. The host signals to the ALC that a circuit should be cached via the Circuit Reference Table using the cache start bit and address fields. The host then schedules a packet or packets via the TPQ mechanism. On its first pass through the structures, the ALC fetches appropriate parameters from Circuit Reference Table and current Transmit Descriptor stores them on chip. data the the the and Subsequently the ALC will process the internal copies of its data structures. Further queued packets will cause the ALC to fetch the new Transmit Descriptor information only. 31 MB86687A On completion of the packet, if no more packets are queued, the cache entry will remain valid but idle until a new packet is queued or the entry is overwritten with a new entry. 32 Edition 2.0 Additional codes added to the Buffer Release Queue return codes will notify the host when all packets for a particular circuit have been assembled. At this time the host can choose to re-use the cache entry for another circuit. Edition 2.0 MB86687A 4. DEVELOPERS NOTES 4.1 Configuration Control Issues This section is intended to give an overview of the ALC from a system programmers perspective. The following operations need to be performed by the host to configure the ALC. Set up the shared data structures, Set up queue addresses, Set up queue parameters, service rate Program ALC mode registers. During normal operation the host is also required to perform the following operations. Pass user data buffers to the ALC for transmission, Reclaim used transmit buffers from the ALC for reuse after transmission completes, Allocate receive buffer space for use by the ALC, Receive packets when completion is indicated by the ALC, Activate circuits, and de-activate virtual Respond to exception interrupts as required. These operations are explained in more detail below. 4.2 Transmit Data Structures A diagramatic view of the transmit side data structures is shown in Fig. 18, a detailed view of the pointer mechanism in Fig. 19 and a diagramatic view of the queue structure in Fig. 22. Before data can be transmitted the host has to programme the ALC with the base address of the following transmit data structures: Transmit Descriptor Table, Circuit Reference Table, Transmit Pending Queue and the Transmit Buffer Release Queue. In addition the host has to initialise the appropriate entries in the Transmit Descriptor and Circuit Reference Tables. 4.2.1 Transmit Descriptor Table The Transmit Descriptor Table is composed of a contiguous list of Transmit Descriptors (TDs). The host composes a TD for each packet to be transmitted and adds the TD to the TD table. The table can contain up to 4096 TDs. A TD is composed of the fields shown in Fig. 20 on page 36. Diagrams showing the implementation of transmit queue organisation and calculation of pointer addresses for both TDs and Circuit Reference table entries are given on the following pages. 33 MB86687A Edition 2.0 TRANSMIT PENDING QUEUE Entry 0 1 2 3 4 5 6 7 . . etc. TRANSMIT DESCRIPTORS host write Transmit Descriptors contain packet information including: - length - start of data pointer See Fig. 20 for TD format PACKET BUFFER (PAYLOAD) ALC TRANSMIT BUFFER RELEASE QUEUE Entry 0 1 2 3 4 5 6 7 . . etc. CIRCUIT REFERENCE TABLES host read Circuit Reference Tables include traffic parameters and cell header information See Fig. 21 for CRT entry format SAR MEMORY Fig. 18 - Transmit Data Structures 34 Edition 2.0 MB86687A TRANSMIT BUFFER RELEASE QUEUE TRANSMIT PENDING QUEUE ALC READ PTR HOST WRITE PTR HOST READ PTR ALC WRITE PTR 0000 DESCRIPTOR REFERENCE 0000 DESCRIPTOR REFERENCE PACKET m PACKET n TRANSMIT DESCRIPTOR REFERENCE 00000 TRANSMIT DESCRIPTOR REFERENCE + 00000 + TRANSMIT DESCRIPTOR BASE ADDRESS 00000000 TRANSMIT DESCRIPTOR BASE ADDRESS 00000000 TRANSMIT DESCRIPTOR TABLE ENTRY m ADDRESS POINTER CCT REF ADDRESS POINTER ENTRY n CCT REF CIRCUIT x CIRCUIT y CIRCUIT REFERENCE 0000 CIRCUIT REFERENCE + 0000 + CIRCUIT REFERENCE BASE ADDRESS 00000000 CIRCUIT REFERENCE BASE ADDRESS 00000000 CIRCUIT REFERENCE TABLE ADDRESS POINTER ENTRY x ENTRY y ADDRESS POINTER Fig. 19 - Transmit Data Structures - Address Calculation 35 MB86687A Edition 2.0 31 M 26 25 S CE CS CG PT 24 23 15 ABT MID 13 10 9 IOC CLP RES CBS LBR 0 REMAINING BYTES FOR SEGMENTATION 0 CIRCUIT REFERENCE BA SIZE/LENGTH FIELD RESERVED RESERVED BUFFER START ADDRESS RESERVED AAL5 CONTROL FIELD / NEXT CHAINED DESCRIPTOR REFERENCE TRANSMIT BUFFER SIZE UNUSED AVAILABLE FOR USER SOFTWARE Fig. 20 - Transmit Descriptor M (More) The host sets this bit to 0 to indicate that the transmit buffer associated with this TD contains the End of Message segment of the CS-PDU. The ALC will append a CS-PDU trailer after the end of this buffer. All other TDs associated with the buffer should have M set to 1. S (Segmenting) This bit is set by the ALC to indicate that segmentation is in progress on the transmit buffer. The host sets the S bit to zero before passing the TD to the Transmit Descriptor Table. CE (Chain End) The host sets this bit to 0 to indicate that this is the last TD in the chain. If CE is set, the ALC assumes that the Next Chained Descriptor Reference field is valid. 36 CS (Chain Start) The host sets this bit to indicate that the associated transmit buffer is not the first buffer of a chain or stream of descriptors. This bit is used for AAL3/4 or for AAL5 when using external calculation of Convergence Sublayer parameters. CG (Congestion indication) The host sets this bit to indicate that ATM cells generated from the associated buffer should have the congestion notification bit set in the Payload Type Field. Edition 2.0 PT (Pass Transparent) The host sets this bit to indicate that the ALC should set the CG bit in the PTI field and CLP bit of the ATM cell header directly as coded in the Circuit Reference Table for each cell, otherwise the CG and CLP bits are as programmed in the Transmit Descriptor. MID (Multiplexing Identification) The ALC writes this ten bit field into the ATM cell's MID field. ABT (Abort) The host sets this bit to instruct the ALC to transmit an Abort cell as defined for streaming mode operation. When an abort AAL3/4 or AAL5 cell has been transmitted the following queued descriptor should not have the CS bit set ie. it should be the first descriptor in a new packet. IOC (Interrupt On Completion) The host sets this bit to indicate that the ALC should generate an interrupt when segmentation of the Transmit Descriptor buffer is complete. CLP (Cell Loss Priority bit) The host sets this bit to indicate that ATM cells generated from the associated buffer should have the CLP bit set = 1. CBS (Copy Buffer Size) The host should set this bit if the Transmit Buffer Size field is the initial value for bytes for segmentation. LBR (Leaky Bucket Reset) The host should set this bit if the leaky bucket variable capacity is to be re-initialised the first time data is re-assembled from this TD. MB86687A Circuit Reference This field is a 10 bit index into the Circuit Reference Table. It is shifted left by 4 bits then added to the Circuit Reference Table base address (shifted left by 8 bits ) to generate a pointer to the appropriate entry in the Circuit Reference Table. The circuit reference index could be either the VCI or MID of the connection. Remaining Bytes for Segmentation This field is initially loaded with the total number of bytes in the packet for segmentation. This field is modified by the ALC during packet transmission. In streaming and chaining modes, the length of each buffer can be any number of bytes provided that the next streamed or chained buffer can fill any remaining partially assembled cell. In streaming mode a buffer that does not terminate on a cell boundary will be held by the ALC until a subsequent buffer is linked on. BA Size / Length Field In AAL 3 /4 mode the ALC transmits this value in the BA Size field of the AAL 3/4 CS-PDU header. In AAL5 mode the AAL transmits this value in the AAL5 CS-PDU trailer LENGTH field. Reserved 0 These fields are for internal ALC usage. They should be initialised to 0 and reset to 0 when the host retrieves the transmit descriptor through the transmit buffer release queue but otherwise should not be used by the host. Reserved These fields are for internal ALC usage and should not be used by the host. 37 MB86687A Edition 2.0 Buffer Start Address This 24 bit pointer provides the ALC with the start address of the associated transmit buffer. Any number of header bytes can be read from a user data buffer by writing the correct byte (non 32 bit aligned) address to this location. Transmit Buffer Size This 16 bit value is set by the host. It specifies the number of bytes in the associated transmit buffer. This field is optionally used by the ALC, if the CBS bit is set, as the initial value of bytes for segmentation. AAL5 Control Field / Next Descriptor Reference In chaining mode the host programs the next descriptor reference in the chain into this field. In AAL5 mode, this field contains the Control Field of the CS-PDU trailer only if this is the final TD in the chain. Available for User Software This field is not used by the ALC and will not be used by future ALC devices. This field may be utilised by user software. Re-initialisation of Transmit Descriptors Field Mode Message Chaining Streaming Segmenting (S) bit 0 0 0 AAL5 Control/ Next Chain set AAL5: control in last TD Next chain descriptor Set last TD only Buffer Start Address AAL3/4 BASIZE AAL5 Length Programmed by Host set * Bytes remaining Programmed by Host ** Reserved 0 Program to 0 Note * Note ** In AAL5, if the MAAL5 bit is set, this value is computed automatically by the ALC. If copy buffer size is set, this field will be refreshed by the ALC to the value in the Transmit Buffer Size field. 4.2.2 Circuit Reference Table The Circuit Reference Table is composed of a list of contiguous Circuit Reference entries. There is a Circuit Reference for each active Virtual Circuit. Each Circuit Reference Table entry contains the ATM Cell header and the Leaky Bucket parameters for the relevant VC. The Circuit Reference is composed of the following fields, see Fig. 21. 38 AAL3/4: BASIZE in first TD AAL5: length in last TD * Routing Tag 0 - 3 Optional routing tag appended in applications where the ALC is interfacing directly with a Fujitsu Self Routing Switch Element MB86680 device or any similar device. Up to three octets of routing is supported. GFC - Generic Flow Control, VPI - Virtual Path Identifier, Edition 2.0 MB86687A VCI - Virtual Channel Identifier, The host can select any combination of bits to generate the required average rate. If the ratio is programmed to 1, the peak and average rates will be identical which could be used for constant bit rate traffic. Average rates greater than 1 are not supported. PTI - Payload Type Identifier, CLP - Cell Loss Priority. These form the ATM Header Field as defined by the UNI Specification. The ALC will code the PT bit of the PTI field according to the state of assembly of the SDU. ECS (External Calculation of SPCS) This single bit instruction is used to select the use of external memory for AAL5 CRC32 and AAL3/4 length field and sequence number storage. This set by the host for non-cached entries when internal memory is not available. (Each cache entry uses the storage of 8 equivalent VC entries) U, Leaky Bucket utilisation parameter This field contains the average rate of cell transmission for leaky bucket management expressed as a ratio of the peak rate. The coding is as follows: Bit no. 11 10 9 8 1 1/2 1/4 1/8 Peak Rate Ratio 31 28 27 24 23 00000000 GFC C E C H C H S S S T S 20 19 ROUTING TAG0 Additionally used in transparent cell and transparent payload to indicate to the ALC that the CRC10 should be calculated and placed in the last 10 bits of the payload. 16 15 12 11 ROUTING TAG1 VPI C E V RESERVED RESERVED 8 7 6 5 4 3 2 1 0 ROUTING TAG2 P T I VCI CADDRESS RESERVED LEAKY BUCKET CAPACITY CONSTANT (M) RESERVED SRS SQN C L P AALT UTILISATION LEAKY BUCKET CAPACITY (U) VARIABLE (M*) Fig. 21 - Circuit Reference Table Entry 39 MB86687A Edition 2.0 CHS (Cache Start) Set by HOST. CHSTS (Cache Status) Initialised to '0' by the HOST, set by ALC. SQN (Service Queue Number) The host uses this field to assign the associated Virtual Circuit to one of the 12 peak rate queues. The coding is as follows: CEV (Chain End Valid) Initialised to '0' by the HOST, set by ALC, CADDRESS (Cache Address) (7 bit field): set by HOST; valid if the CHS bit is set. SRS (Sub-Rate Select) These bits are used to select the required sub-rate of the nominal transmit queue peak rate. The coding is as follows. Bit no. 7 6 Sub-rate selected 0 1 25% 1 0 50% 1 1 100% 0 0 see below If the Circuit Reference Table for a circuit is programmed with SRS=00 and AALT=11 (AAL5 only) then the ALC will omit leaky bucket calculations on transmit for that circuit. This reduces transmit overhead accesses for circuits with 100% utilisation. This facility is available on the high and medium priority queues only. 40 Bit no. Peak Rate Queue 5 4 3 0 0 0 1 Queue 1 1 1 0 0 Queue 12 2 Queue 1 corresponds to Low Priority and Queue 12 corresponds to High Priority. AALT (ATM Adaption Layer Type) This field is used to specify the AAL type for the VC. Two transparent modes can also be selected. The coding is as follows: 1 0 AAL Type selected 0 0 AAL 3/4 0 1 Transparent Payload 1 0 Transparent Cell 1 1 AAL 5 Edition 2.0 MB86687A M (Leaky Bucket capacity constant) M in the Circuit Reference Table entry is the bucket capacity used to implement leaky bucket averaging on a per VC basis. The host programmes this field with a Leaky Bucket capacity in the range of 1 - 255. The relationship between the bucket capacity (M), the utilization (U) and the maximum burst length (B) at the selected peak rate is given by: M=(B-1)x(1-U) for single leaky bucket method and by: M* (Leaky Bucket capacity variable) The ALC uses this variable to implement leaky bucket averaging on a per virtual circuit basis. The host initially sets M* to the same value as M, M* is then modified by the ALC as the ALC implements the leaky bucket algorithm for that VC. The ALC uses the constant value M for reference when carrying out leaky bucket calculations. M* may also be refreshed to M when the LBR bit is set in a TD. Reserved These fields are for internal ALC usage and should not be used by the host. M=Bx(1-U) 4.2.3 for double leaky bucket method. Note: If the resulting M value is not an integer then in the single leaky bucket case M should be rounded DOWN to the nearest integer and in the double leaky bucket case M should be rounded UP to the next integer. Also, for the single leaky bucket case a minimum value of B is specified for each utilization value as given below: U = 0.875 minimum allowed B = 9, U = 0.75 minimum allowed B = 5, U = 0.625 minimum allowed B = 4, For all other values of U the minimum value allowed for B is 3. Transmit Pending Queue The transmit pending queue is used by the host to instruct the ALC to queue a transmit packet for segmentation. Each command passed to the queue includes a 12 bit index reference into the Transmit Descriptor table. A Transmit Pending Queue entry is shown in Fig. 23. This queue is defined by registers 2 - 6. The Host Processor must assign values for the Transmit Pending Queue base, start address, end, read and write pointers. The initial values of the read and write pointers should be the start address to reflect an empty queue. To pass a new entry to the TPQ the Host Processor should read the current value of the on-chip write register. This address should be used to store the new TPQ entry. The host should then update the write pointer register, wrapping around to the start address if necessary. 41 MB86687A Edition 2.0 When the DMA Controller has available transmit bandwidth (or once every five segmentation periods), i.e a cycle where cell segmentation is not required, it reads the value of the Transmit Descriptor Reference addressed by its internal read pointer. In addition, the Transmit Pending Queue can be used as follows: D Utilisation adjustment; The U value in the CRT pointed to by the associated TD will be set to the given value. For cached entries, a dummy circuit reference entry should be used to point to the required cached address and the CHS bit set. D Send Express Cell; If an entry is placed on the queue with the 1100 coding then it will not be assigned to a rate queue but will be sent immediately. For streaming mode when transmitting packets using non-integral cell length buffers, the host may queue a last stream transmit descriptor which results in the cell started in the current buffer being the last cell of the packet. For this case, the last stream transmit descriptor must be queued as follows: D TPQ code=1010 if remaining bytes for segmentation is zero; D TPQ code=1001 if remaining bytes for segmentation is non-zero. : REG 41 : REG 3 Write REG 5 Transmit Pending Queue Read Read REG 6 REG 44 : REG 4 H O S T Write REG 43 : REG 42 H O S T ALC Read REG 10 : REG 7 : REG 46 Transmit Buffer Ready Queue Receive Buffer Ready Queue : REG 8 TRW Interrupt : = Start and End addresses 42 Receive Buffer Free Queue Write Write REG 9 REG 48 Read REG 49 : REG 47 RRW Interrupt Fig. 22 - ALC Queue Structures Edition 2.0 MB86687A TPQ Code 15 11 0 TRANSMIT DESCRIPTOR REFERENCE 0000 Queue Packet 0001 Set Utilisation to 0.125 0010 Set Utilisation to 0.25 0011 Set Utilisation to 0.375 0100 Set Utilisation to 0.5 0101 Set Utilisation to 0.625 0110 Set Utilisation to 0.75 0111 Set Utilisation to 0.875 1000 Set Utilisation to 1.0 1001 Queue last cell (streaming - bytes remaining) 1010 Queue last cell (streaming - no bytes remaining) 1100 Queue Express Cell 1111 Set Utilisation to 0 Fig. 23 - Transmit Pending Queue Format 4.2.4 Transmit Buffer Release Queue The ALC returns segmented transmit buffers to the host using the Buffer Release Queue. Each queue entry will contain a 12 bit reference index into the Transmit Descriptor table. A queue entry is shown in Fig. 24. This queue is defined by registers 2 and 7 - 10. The Host Processor must assign values for the Buffer Release Queue base, start address, end, read and write pointers. The initial values of the read and write pointers may be the start address to reflect an empty queue or the write pointer may be set to the read pointer minus 1 to reflect a pool of free buffers. To release a buffer to the host the ALC increments the TBRQ write pointer and, if the IOC bit in the Transmit descriptor is set, generates an interrupt. The host may then choose to immediately acknowledge this action by updating the TBRQ read pointer or if using the queue as a pool of free buffers, only update the pointer when reusing the TD. 43 MB86687A Edition 2.0 BRQ Code 12 11 15 0 TRANSMIT DESCRIPTOR REFERENCE 0000 Default code 0001 Changed Utilisation 0010 Packet complete. No further packets for this circuit 0011 Packet complete. No further packets for this queue 0100 Buffer complete. Moving to next streamed buffer 0101 Changed utilisation to 0 0110 Buffer complete. Awaiting next streamed buffer 0111 Buffer complete. No further packets in this queue. Awaiting next streamed buffer 1000 Buffer complete. Not end of chain 1010 Express Cell Sent 1100 Abort sent 1110 Abort sent. No further packets for this circuit 1111 Abort sent. No further packets in this queue Fig. 24 - Transmit Buffer Release Queue Format 4.2.5 INCWRAP - Wrap and Increment Mechanism When writing to the host-controlled queue registers, if the most significant bit of the control data bus is set, the ALC will automatically increment its internal copy of the pointer being written to regardless of the pointer value specified on the data bus. Two status conditions are available when reading the host-controlled pointers: 44 EMPTY condition If this bit is set, it indicates that the ALC's pointer for the queue is at the same value as the host pointer's value returned by the read and that the queue is empty. FULL condition If this bit is set, it indicates that the host pointer and ALC pointer values are the same and that the queue is full. Edition 2.0 4.3 MB86687A Receive Data Structures A detailed view of the receive data structures is shown in Fig. 25, a detailed view of the pointer mechanism in Fig. 26 and a diagramatic view of the queue structures in Fig. 22. Before data can be received the host has to programme the ALC with the base address of following receive data structures: Receive Descriptor Table, Receive Buffer Free Queue and the Receive Buffer Ready Queue. 4.3.1 descriptors terminates with this descriptor. The host is required to initialise this bit to 0 and also in chaining mode to clear this bit to 0 before returning the receive descriptor to the ALC through the buffer free queue. Next Chain Descriptor Reference When receive buffer chaining is used this 12 bit field is programmed by the ALC with the descriptor reference of the next receive descriptor in the chain. Receive Descriptor Table The Receive Descriptor Table is composed of a contiguous list of Receive Descriptors (RDs). The host is responsible for composing sufficient RDs to handle the expected number of receive packets. Each time a start of packet cell is received the ALC will use the next entry in the Receive Buffer Free Queue to locate the relevant RD in the table. A typical RD is composed of the fields shown in Fig. 27 on page 48. Diagrams showing the implementation of the Receive queue organisation and calculation of pointer addresses for RDs and field entries are given on the following pages. V (Valid) The ALC sets this bit to 1 to indicate that the Next Chain Descriptor field in this descriptor is valid. This is used in chaining mode when the received packet does not terminate in the current receive buffer. When this bit is cleared to 0 it indicates that the chain of receive buffer Reserved These fields are for internal ALC usage and should not be accessed by the host. Receive Circuit Reference This 10 bit field is programmed by the ALC with the receive channel supplying data to the associated receive buffer. This channel number will imply a particular VP/VC according to the programming of VPB2, VPB1 & VPB0 in Register 16. If chaining is used, this value is only valid in the first descriptor of the chain. CLP (Cell Loss Priority) The ALC sets this bit to indicate that the last ATM cell re-assembled into the associated buffer had the CLP bit set = 1. CI (Congestion Indication) The ALC sets this bit to indicate that the last ATM cell re-assembled into the associated buffer had the CI bit set = 1. GFC (Generic Flow Control) The ALC sets this field to the GFC value in the last ATM cell reassembled into the associated buffer. 45 MB86687A Edition 2.0 1000 BUFFER FREE QUEUE Entry 0 1 2 3 4 5 6 7 . . etc. RECEIVE DESCRIPTORS host write Receive descriptors contain reassembled packet information including: - length - start of data pointer See Fig. 27 for descriptor format ALC PACKET BUFFER (PAYLOAD) RECEIVE DESCRIPTOR TABLE BUFFER READY QUEUE Entry 0 1 2 3 4 5 6 7 . . etc. host read SAR MEMORY Fig. 25 - Receive Data Structures 46 Edition 2.0 MB86687A RECEIVE BUFFER READY QUEUE RECEIVE BUFFER FREE QUEUE HOST WRITE ALC READ 15 0000 ALC WRITE HOST READ 15 0 DESCRIPTOR REFERENCE 0000 0 DESCRIPTOR REFERENCE PACKET m PACKET n DESCRIPTOR REFERENCE 00000 + RECEIVE DESCRIPTOR BASE ADDR 00000 DESCRIPTOR REFERENCE + RECEIVE DESCRIPTOR BASE ADDR 00000000 00000000 RECEIVE DESCRIPTOR TABLE ADDRESS POINTER ENTRY m ADDRESS POINTER ENTRY n Fig. 26 - Receive Data Structures - Address Calculation Unused These fields should not be utilized by user software but may be cleared to 0 by the host. Buffer Size If the RDAU bit is set in Register 16, this value is automatically copied into the Remaining Capacity field when the RD is first accessed. The value is not modified by the ALC. Available for User Software This field is not used by the ALC and will not be used by future ALC devices. This field may be utilized by user software. 47 MB86687A 31 Edition 2.0 28 27 24 23 15 14 13 12 11 10 9 UNUSED V NEXT CHAIN DESCRIPTOR REFERENCE RESERVED C C L I P RESERVED UNUSED 0 RECEIVE CIRCUIT REFERENCE GFC BUFFER SIZE RESERVED AVAILABLE FOR USER SOFTWARE BYTES RECEIVED RESERVED AAL5 CONTROL FIELD / AAL3 RESERVED REMAINING CAPACITY BUFFER START ADDRESS TOTAL LENGTH Fig. 27 - Receive Descriptor Bytes Received This 16 bit field is programmed by the ALC with the number of bytes written to the associated receive buffer.This field should be initialized to 0 and reset to 0 before returning the descriptor for reuse through the buffer free queue. This count is always a multiple of 4 bytes and hence, will include up to 3 bytes of pad at the end of a packet. Remaining Capacity This field indicates the number of unused bytes within the associated buffer. This field should be initialized to the buffer capacity and reset to the buffer capacity before returning the descriptor for reuse through the buffer free queue. This count is always a multiple of 4 bytes and hence, will include up to 3 bytes of pad at the end of a packet. Buffer Start Address This 24 bit pointer is programmed by the host with the start address of the receive buffer associated with this descriptor. 48 AAL5 Control Field / AAL3 Reserved When AAL5 is selected this field is used to hold the received AAL5 control value obtained from the incoming CS-PDU trailer. If chaining is enabled then this field is only valid in the initial receive descriptor of the chain. In all other descriptors in the AAL5 chain this field is reserved. In AAL 3 for all descriptors this field is reserved. In chaining mode this field should be initialized to 0 and reset to 0 before returning the descriptor for re-use through the buffer free queue. Total Length This 16 bit value is programmed by the ALC with the total length field received in the CS-PDU trailer. If chaining is used then this field contains the total length only in the initial receive descriptor of the chain. In chaining mode this field should be initialized to 0 and reset to 0 before returning the descriptor for reuse through the buffer free queue. Edition 2.0 MB86687A Re-initialisation of Receive Descriptors Field Mode V & next chain RD Message Chaining Streaming N/R 0 N/R * Bytes Received 0 Remaining Capacity buffer size ** BufferStart Address 0 * buffer size ** 0* buffer size ** Programmed by Host AAL5 Control/AAL3 Reserved 0 0 0 Total Length N/R 0 N/R N/R Note * Reinitialisation not required If RDAU is set in Register 16, Bytes Received is automatically cleared when the RD is first accessed; Reinitialisation is then not required. If RDAU is set in Register 16, Buffer Size is automatically copied into Remaining Capacity when the RD is first accessed. Reinitialisation is then not required. Note ** 4.3.2 Receive Buffer Free Queue The Receive Buffer Free Queue is used by the ALC to locate the next Receive Descriptor each time a new packet is received. Each queue entry contains a reference into the Receive Descriptor table. The format of a queue entry is shown in Fig. 28. 4.3.3 Receive Buffer Ready Queue The ALC passes reassembled packets to the host using the Receive Buffer Ready Queue. Each queue entry contains a reference to the relevant Receive Descriptor. In addition the ALC writes the status of the received packet to the Buffer Ready Queue. The format of each queue entry is shown in Fig. 29. 4.3.4 Increment and Wrap Mechanism This mechanism is similar to that used by the transmit queues and is described in section 4.2.5. UNUSED 15 12 11 0 RECEIVE DESCRIPTOR REFERENCE Fig. 28 - Buffer Free Queue Format 49 MB86687A Edition 2.0 RBRQ Status 15 12 11 0 RECEIVE DESCRIPTOR REFERENCE 0000 Reassembly Complete With No Errors ( M=0 ) 0001 Buffer Complete With No Errors (M = 1) 0010 Reassembly Complete With f5 OAM cell - CRC10 passed 0011 Reassembly Complete With f4 or f5 OAM cell - CRC10 failed 0100 Reassembly Complete With f4 OAM cell - CRC10 passed 0101 Sequence Number Error 0110 Invalid Length Indication 0111 Partial reassembly: Missing EOM 1000 Receive Buffer Overflow 1001 Receive Maximum Length Exceeded 1010 No Chaining buffers Available 1011 AAL3 Trailer Error Indication 1100 Buffer Timed Out Reassembly Aborted 1101 Packet Length Error Indication 1110 RAS Abort Indication (Reassembly Streaming) 1111 AAL5 CRC 32 Error Indication || AAL3 BTag / ETag mismatch Fig. 29 - Receive Buffer Ready Queue Format 50 Edition 2.0 4.3.5 MB86687A Receive Descriptor Table Access Mechanism Writing to the Table The write to RSD table process operates in the following way. The host sets the data intended for the RSD by writing it to the Host Receive Descriptor/Status Table Write Register (Register 58) - (This will normally involve setting the ACT bit when a channel is about to be activated). The host then writes to the Host Receive Descriptor/Status Table Access Register (Register 59). The HOSTR and RD/WR must be set to generate the internal write to the RSD table. The values in Register 58 together with the AAL bits from Register 59 are written into the RSD table at the address specified by the VCI values in Register 59. The TAC interrupt will be generated in response to the write to Register 59 to inform the host that the RSD table has been updated. Reading from the Table The read from RSD table process comprises the following sequence of events. The host writes to Register 59 setting HOSTR and clearing RD/WR. This causes the ALC to carry out an internal read to the RSD table using the address specified by the VCI value in Register 59. The contents of the read are written to the Host Receive Descriptor/Status Table Read Register (Register 57) and the TAC interrupt is generated indicating to the host that Register 57 has been updated. The host then reads the RSD table contents from Register 57. Notes Register 57 is read only. Accesses to Registers 57 and 58 have no effect on the RSD table until Register 59 is written to. During normal operation, Register 59 should not be written to with HOSTR and RD/WR (bits D15 and D14) set after the initialisation stage. 4.3.6 OAM Cell Handling The ALC will flexibly handle incoming OAM cells. The ALC considers a cell to be an F5 OAM cell if the most significant bit of the PTI field is set. This means that resource management cells (PTI field = 110) are also treated as these cells. The ALC considers a cell to be an F4 OAM cell if the cell arrives on a channel which has the RIP bit set and the AAL bits set for Transparent Cell mode (10) in the RSD table. If the DCOAM bit (CR16) is set, only F5 OAM cells are discarded. Discarded OAM cells do not alter the dropped cell counter value. If cleared, the OAMCRC bit (CR16) only disables CRC10 checking on F5 OAM cells. The ALC always performs CRC10 checking on F4 OAM cells. 51 MB86687A APPENDICES A. REGISTER TABLE The ALC register address table is shown on the following pages. Please note that the Register Tables TYPE field indicates the type of host access cycle used to access each register. Abbreviations used are as follows: R/O = Host read access only. W/R = Host read/write access W/O = Host write access only. (T) = After initialisation, these registers are updated using TCLK and have a recovery time dependent on TCLK. CW/R = Host write access only after setting the control write enable bit (CWRE) of the ALC Control Register. 52 Edition 2.0 The Registers listed in Fig. 30 to Fig. 32 are further described in Appendix B. An `x' symbol in a register bit location indicates that that bit is not used by the ALC. These unused bits should be written to `0' when writing to the register and will return '1' when reading the register. All the ALC write registers are initialised to 0 after power-up. Edition 2.0 MB86687A APPENDICES ADDRESS TYPE FUNCTION REF 0 W/O TRANSMIT DESCRIPTOR TABLE BASE ADDRESS REGISTER Fig. 33 1 W/O CIRCUIT REFERENCE TABLE BASE ADDRESS REGISTER Fig. 33 2 W/O TRANSMIT QUEUE BASE ADDRESS REGISTER Fig. 33 3 W/O TRANSMIT PENDING QUEUE START ADDRESS REGISTER Fig. 34 4 W/O TRANSMIT PENDING QUEUE END ADDRESS REGISTER Fig. 34 5 W/R TRANSMIT PENDING QUEUE WRITE POINTER Fig. 34 6 CW / R TRANSMIT PENDING QUEUE READ POINTER Fig. 35 7 W/O TRANSMIT BUFFER RELEASE QUEUE START ADDRESS REG. Fig. 35 8 W/O TRANSMIT BUFFER RELEASE QUEUE END ADDRESS REG. Fig. 35 9 CW / R TRANSMIT BUFFER RELEASE QUEUE WRITE POINTER Fig. 36 Fig. 36 10 W/R TRANSMIT BUFFER RELEASE QUEUE READ POINTER 11 --- RESERVED 12 --- RESERVED 13 R/O GFC/CI STATUS CHANGE REGISTER Fig. 37 14 W/O DMA BURST REGISTER Fig. 36 15 W/O DMA MODE REGISTER Fig. 39 16 W/O CONTROL REGISTER Fig. 41 17 W/O MODE REGISTER 18 R/O INTERRUPT STATUS REGISTER 19 W/R INTERRUPT MASK REGISTER Fig. 43 Fig. 44 Fig. 45 Fig. 46 Fig. 47 Fig. 30 - ALC REGISTER MAP (1 of 3) 53 MB86687A APPENDICES ADDRESS Edition 2.0 FUNCTION TYPE REF 20 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER LOW 1 Fig. 47 21 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER LOW 2 Fig. 47 22 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER LOW 3 Fig. 47 23 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER LOW 4 Fig. 47 24 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 1 Fig. 47 25 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 2 Fig. 47 26 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 3 Fig. 47 27 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 4 Fig. 47 28 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 1 Fig. 47 29 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 2 Fig. 47 30 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 3 Fig. 47 31 W / O(T) TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 4 Fig. 47 32 W / O(T) TRANSMIT QUEUE SERVICE ENABLE REGISTER Fig. 48 33 W / O(T) ALC PEAK CELL TRANSMISSION RATE REGISTER Fig. 49 34 W / O(T) ALC AVERAGE CELL TRANSMISSION RATE REGISTER Fig. 49 35 W / O(T) ALC LEAKY BUCKET CAPACITY REGISTER Fig. 50 36 --- RESERVED 37 --- RESERVED 38 --- RESERVED 39 --- RESERVED Fig. 31 - ALC REGISTER MAP (2 of 3) 54 Edition 2.0 MB86687A APPENDICES ADDRESS TYPE FUNCTION REF 40 W/O RECEIVE QUEUE BASE ADDRESS REGISTER Fig. 51 41 W/O RECEIVE BUFFER FREE QUEUE START ADDRESS REGISTER Fig. 51 42 W/O RECEIVE BUFFER FREE QUEUE END ADDRESS REGISTER Fig. 52 43 W/R RECEIVE BUFFER FREE QUEUE WRITE POINTER Fig. 52 44 CW / R RECEIVE BUFFER FREE QUEUE READ POINTER Fig. 52 45 W/O RECEIVE DESCRIPTOR BASE ADDRESS REGISTER Fig. 51 46 W/O RECEIVE BUFFER READY QUEUE START ADDRESS REGISTER Fig. 53 47 W/O RECEIVE BUFFER READY QUEUE END ADDRESS REGISTER Fig. 53 48 CW / R RECEIVE BUFFER READY QUEUE WRITE POINTER Fig. 54 49 W/R RECEIVE BUFFER READY QUEUE READ POINTER Fig. 54 50 R/O DROPPED PACKET COUNTER Fig. 54 51 W/O RECEIVE BUFFER TIME OUT COUNTER PERIOD REGISTER Fig. 55 52 W/O RECEIVE BUFFER TIME OUT INTERVAL REGISTER Fig. 55 53 R/O RECEIVED BUFFER READY DATA HOLD REGISTER Fig. 56 54 W/O MAXIMUM RECEIVED PACKET LENGTH REGISTER Fig. 56 55 R/O DROPPED CELL COUNTER Fig. 56 56 W/O RECEIVE ADDRESS FILTER REGISTER Fig. 57 57 R/O HOST RECEIVE DESCRIPTOR / STATUS TABLE READ REG. Fig. 58 58 W/O HOST RECEIVE DESCRIPTOR / STATUS TABLE WRITE REG. Fig. 58 59 W/R HOST RECEIVE DESCRIPTOR / STATUS TABLE ACCESS REG. Fig. 59 Fig. 32 - ALC REGISTER MAP (3 of 3) 55 MB86687A APPENDICES B. Edition 2.0 REGISTER MAPS Register 0 - Transmit Descriptor Table Base Address Register D15 TDA15 TDA14 TDA13 TDA12 TDA11 TDA10 TDA9 TDA8 TDA7 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 D0 This base address (shifted left by 8 bits) is added to the 12 bit Transmit Descriptor address (shifted left by 5 bits) from the Transmit Pending or Release Queue to obtain the full 24 bit address of the Transmit Descriptor required to execute a packet transmission. Register 1 - Circuit Reference Table Base Address Register D15 CRA15 CRA14 CRA13 CRA12 CRA11 CRA10 CRA9 CRA8 CRA7 CRA6 CRA5 CRA4 CRA3 CRA2 CRA1 CRA0 D0 This base address (shifted left by 8 bits) is added to the 10 bit circuit reference address (shifted left by 4 bits) from the Transmit Descriptor to obtain the full 24 bit address of the Circuit Reference Table entry describing the circuit to be used when executing the requested transmission. Register 2 - Transmit Queue Base Address Register D15 0 0 X X X TQA7 TQA6 TQA5 TQA4 TQA3 X TQA2 TQA9 TQA8 TQA1 TQA0 D0 This register contains the upper10 bits of both the Transmit Pending and Buffer Release Queue addresses. This base address is concatenated with the start or end address (shifted left by 1 bit) or with the write or read pointers (shifted left by 1 bit) to obtain the upper 23 bits of the system or dual port SAR memory address of the Pending or Release Queue entry. Address bit 0 is always set to 0 by the ALC. Fig. 33 - REGISTERS 0, 1 AND 2 56 Edition 2.0 MB86687A APPENDICES Register 3 - Transmit Pending Queue Start Address Register D15 X X X TPS12 TPS11 TPS10 TPS9 TPS8 TPS7 TPS6 TPS5 TPS4 TPS3 TPS2 TPS1 TPS0 D0 This offset address is shifted left by one bit and concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Transmit Pending Queue start address. This start address indicates the beginning of the Transmit Pending Queue space which is used to pass transmit request buffer descriptor addresses from the Host to the ALC. Address bit 0 is always be set to 0 by the ALC. Register 4 - Transmit Pending Queue End Address Register D15 X X X TPE12 TPE11 TPE10 TPE9 TPE8 TPE7 TPE6 TPE5 TPE4 TPE3 TPE2 TPE1 TPE0 D0 This offset address is shifted left by one bit and concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Transmit Pending Queue end address. This end address indicates the finish of the Transmit Pending Queue space which is used to pass transmit request buffer descriptor addresses from the Host to the ALC. Address bit 0 is always set to 0 by the ALC. Register 5 - Transmit Pending Queue Write Pointer D15 INCWRAP TPW7 EMPTY FULL TPW12 TPW11 TPW10 TPW9 TPW8 TPW6 TPW5 TPW4 TPW3 TPW2 TPW1 TPW0 D0 This offset address is shifted left by 1 bit and concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Transmit Pending Queue write pointer. The Host uses this pointer when entering transmit requests by writing a transmit descriptor reference address to the transmit pending queue. Address bit 0 is always be set to 0 by the ALC. INCWRAP - When writing to the host-controlled queue registers, if the most significant bit of the control data bus is set, the ALC will automatically increment its internal copy of the pointer being written to regardless of the pointer value specified on the data bus. EMPTY - If this bit is set, it indicates that the ALC's pointer for the queue is at the same value as the host pointer's value returned by the read and that the queue is empty. FULL - If this bit is set, it indicates that the host pointer and ALC pointer values are the same and that the queue is full. Fig. 34 - REGISTER 3, 4 AND 5 57 MB86687A APPENDICES Edition 2.0 Register 6 - Transmit Pending Queue Read Pointer D15 X X ASYNCI TPR12 TPR11 TPR10 TPR9 TPR8 TPR7 TPR6 TPR5 TPR4 TPR3 TPR2 TPR1 TPR0 D0 This offset address is shifted left by 1 bit and concatenated to the Transmit Queue Base Address Register contents ( shifted left by 14 bits ) to obtain the upper 23 bits of the Transmit Pending Queue read pointer. The ALC uses this pointer when retrieving transmit requests by reading a transmit descriptor reference address from the Transmit Pending Queue. Address bit 0 is always set to 0 by the ALC. ASYNCI - When set this indicates value was changing during an asynchronous microprocessor read. Since this means an incorrect transitional value may have been recorded the register should be re-read. Register 7 - Buffer Release Queue Start Address Register D15 X X X BRS12 BRS11 BRS10 BRS9 BRS8 BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRS0 D0 This offset address shifted left by 1 bit is concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Transmit Release Queue start address. This start address indicates the beginning of the Transmit Release Queue space used by the ALC to indicate the availability of free transmit descriptors to the host. Address 0 is always set to 0. Register 8 - Buffer Release Queue End Address Register D15 X X X BRE12 BRE11 BRE10 BRE9 BRE8 BRE7 BRE6 BRE5 BRE4 BRE3 BRE2 BRE1 BRE0 D0 This offset address shifted left by 1 bit is concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Transmit Release Queue end address. This end address indicates the finish of the Transmit Release Queue space used by the ALC to indicate the availability of free transmit descriptors to the host. Address 0 is always set to 0. Fig. 35 - REGISTER 6, 7 AND 8 58 Edition 2.0 MB86687A APPENDICES Register 9 - Buffer Release Queue Write Pointer D15 X X ASYNCI BRW12 BRW11 BRW10 BRW9 BRW8 BRW7 BRW6 BRW5 BRW4 BRW3 BRW2 BRW1 BRW0 D0 This offset address is shifted left by one bit and concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Transmit Buffer Release Queue write pointer. The ALC uses this pointer when a packet transmission has been completed to return the transmit descriptor used to the pool of free transmit descriptors for use by the host in future transmit requests. Please refer to Register 6 on page 58 for a description of ASYNCI. Register 10 - Buffer Release Queue Read Pointer D15 INCWRAP BRR7 EMPTY FULL BRR12 BRR11 BRR10 BRR9 BRR8 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 D0 This offset address is shifted left by one bit and concatenated to the Transmit Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Transmit Buffer Release Queue read pointer. The Host uses this read pointer to obtain an available transmit descriptor when a packet is ready for transmission. INCWRAP - When writing to the host-controlled queue registers, if the most significant bit of the control data bus is set, the ALC will automatically increment its internal copy of the pointer being written to regardless of the pointer value specified on the data bus. EMPTY - If this bit is set, it indicates that the ALC's pointer for the queue is at the same value as the host pointer's value returned by the read and that the queue is empty. FULL - If this bit is set, it indicates that the host pointer and ALC pointer values are the same and that the queue is full. Fig. 36 - REGISTERS 9 and 10 59 MB86687A APPENDICES Edition 2.0 Register 13 - CE/GFC Change Indication D15 X RCR7 CE GFC3 GFC2 GFC1 GFC0 RCR9 RCR8 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0 D0 This register shows the status of the latest change in congestion experienced and GFC status with its associated Receive Circuit Reference. CE: Status of Congestion Experienced Bit. GFC3-0: Status of GFC Field (UNI mode only). RCR9-0: Receive Circuit Reference of circuit with changed status. Fig. 37 - REGISTER 13 60 Edition 2.0 MB86687A APPENDICES Register 14 - DMA Burst Length Register D15 RIF3 RIF2 RIF1 RIF0 TIF3 TIF2 TIF1 TIF0 DBL7 DBL6 DBL5 DBL4 DBL3 DBL2 DBL1 DBL0 D0 RIF3-RIF0: Receive Buffer Ready Interrupt Frequency. This count specifies the frequency of receive buffer ready interrupts. This value specifies the number of received buffers that are completed before the ALC generates a service request to the host using the Receive Buffer Ready Queue Write interrupt. TIF3-TIF0: Transmit Buffer Release Interrupt Frequency. This count specifies the frequency of transmit buffer release interrupts. This value specifies the number of transmitted buffers that are completed with the IOC bit set before the ALC generates a service request to the host using the Receive Buffer Ready Queue Write interrupt. DBL7-DBL0: This register may be set to limit the maximum number of ALC, system memory DMA access cycles that may occur in a single block. This burst length is applicable only when the ALC is operating in ready dependent, DMA mode. A burst length limit of 0 indicates unlimited burst length. A burst length limit in the range 1 - 255 indicates the maximum number of ALC DMA cycles that can occur before the bus is released to allow re-arbitration for control of the system bus. Fig. 38 - REGISTER 14 61 MB86687A APPENDICES Edition 2.0 Register 15 - DMA Mode Register D15 SBL PARSEL WMOD RMOD SCE SYN BRSTO CMODE BURSTD MMODE DMAOPT STEALO STEALD ORDER BMODE1 BMODE0 D0 SBL: Single Cycle Burst Length. This selects between 8-transfer (set) and 4-transfer (cleared) data bursts. PARSEL: Parity Select. This bit is set for odd parity and cleared for even parity. SCE: Single Cycle Enable. This bit is set to enable single clock cycle burst data transfers BURSTO: Burst Overhead. If this bit is set then the ALC will finish all control transfers for transmit before switching over to receive and vice versa. BURSTD: Burst Data. If this bit is set then the ALC will finish all data transfers for transmit before switching over to receive and vice versa. DMAOPT: DMA Optimise. Setting ths bit will cause the ALC to optimise the dead cycles between overhead operations. STEALO: Steal Overhead. If this bit is set then the ALC will allow transmit to steal overhead cycles from receive and vice versa. STEALD: Steal Data. If this bit is set then the ALC will allow transmit to steal data cycles from receive and vice versa. Note: Please refer to section 3.7.3 for an explanation of the setting of the BURST and STEAL bits. Fig. 39 - REGISTER 15 62 Edition 2.0 MB86687A APPENDICES Register 15 - DMA Mode Register (Continued) D15 SBL PARSEL WMOD RMOD SCE SYN BRSTO CMODE BURSTD DMAOPT STEALO STEALD ORDER BMODE1 BMODE0 MMODE D0 WMOD: 0 1 WR signal as MB86686 WR signal extended. RMOD: 0 1 Data sampled on falling edge of DCLK, RD signal as MB86686. Data sampled on rising edge RD signal extended. SYN: 0 1 DMA treated as asynchronous. DMA treated as synchronous. CMODE: SAR Memory Cycle Time. This bit is cleared to select ready dependent SAR memory cycles (minimum cycle time = 2 x DCCLK) and set to select fast mode SAR memory cycles (cycle time = 2 x DCCLK). MMODE: SAR Memory Mode. This memory mode bit is set to select dual port RAM use for segmentation and reassembly and cleared to select DMA use of system memory for segmentation and reassembly. ORDER: SAR Memory Byte Ordering Convention. This bit is cleared to select Big Endian (Motorola/SPARC) byte ordering and set to select Little Endian (Intel/DEC Alpha) byte ordering. This byte ordering applies to the transmit and receive buffer data and selected Endian word ordering applies to the queue structures Descriptor data uses the Little Endian ordering convention. The queue data format is configurable as Big Endian or Little Endian, using word swapping. BMODE1-0: SAR Memory Control Signal Mode. 00 Intel / GP Timings 01 Intel 486 Timings 10 Motorola Timings 11 Motorola 68x40 timings Fig. 40 - REGISTER 15 contd. 63 MB86687A APPENDICES Edition 2.0 Register 16 - Control Register D15 MBRQE OAMCRC VPB2 RDAU VPB1 VPB0 AF17 AF16 TSTLP RSTRT INIT SRST UNSEL CWRE DCOAM MAAL5L D0 MBRQE: Enable Buffer Ready Queue Interrupt when M=0. When in streaming mode setting this bit will cause a buffer ready queue interrupt to occur every time a packet is terminated (M=0) irrespective of the setting of the receive buffer Interupt frequency. VPB2-0: Virual Path Detect bits (Valid range 000 - 101). These are used to control how many bits of the VP are used in the receive address mapping. AF17-16: Address Filter Bits 17 -16. These are the 2 msbs of the receive address filter. For a full description of this function see section 3.5.9. UNSEL: UNI/NNI Select. If set this bit uses an NNI address for filtering (uses all 18 bits of Address Filter). If it is cleared it uses a UNI address for filtering (used only 14 lsbs of the Address Filter) DCOAM: Discard OAM. If this bit is set the ALC will discard all cells received (excepting F4 cells) which are not user data cells. Fig. 41 - REGISTER 16 64 Edition 2.0 MB86687A APPENDICES Register 16 - Control Register (Continued) D15 MBRQE OAMCRC VPB0 RDAU VPB1 VPB2 AF17 AF16 TSTLP RSTRT INIT SRST UNSEL CWRE DCOAM MAAL5L D0 OAMCRC: OAM CRC checking. This bit should be set to enable CRC-10 checking on all non-user data cells excepting F4 cells. RDAU: Receive Descriptor Auto Update of Remaining Capacity. Setting this bit enables automatic initialisation of the bytes remaining field in the Receive Descriptor with the Buffer Size field and automatic clearing of the Bytes Received field. TSTLP: Test Loop Enable. When this bit is set the ALC's transmit cell stream interface is internally looped back into the receive cell stream interface using TXCLK. RSTRT: ALC Cell Stream Interface Daisy Chain Restart. When this bit is set a daisy chain token pulse is generated on ALC's TOUT line. This is used to restart the token daisy chain if the token has been lost. INIT: Host Initialisation Complete. This bit is set by the Host when it (the host) has completed all required initialisation of ALC registers and memory structures. SRST: ALC Software Reset. This bit is set to reset all internal ALC circuitry. CWRE: ALC Host Queue Pointer Initialisation Enable. This bit is set to allow the Host to initialise the Transmit Pending Queue Read Pointer, the Transmit Buffer Release Queue Write Pointer, the Receive Buffer Free Queue Read Pointer and the Receive Buffer Ready Queue Write Pointer. This bit should be cleared after initialisation for normal operation. MAAL5L: Maintain AAL5 Length. Setting this bit will cause the ALC to automatically compute the AAL5 length field across multiple chained or streamed transmit buffers. Fig. 42 - REGISTER 16 contd. 65 MB86687A APPENDICES Edition 2.0 Register 17 - Mode Register D15 TRTL1 BCHAIN TRTL0 SMODE AM DCHAIN BAS DMASK VPF HEC2 HEC1 HEC0 0 RID RTL1 RTL0 D0 TRTL1 - TRTL0: Transmit Routing Tag Length. This field specifies the length (if any) of routing tag to be appended to all transmitted cells. 00: No Routing Tag 01: One Octet Routing Tag 10: Two Octet Routing Tag 11: Three Octet Routing Tag. AM: Traffic Rate Averaging Method. This bit is cleared to select the single leaky bucket (trickle) method of traffic rate averaging and set to select the double leaky bucket (burst) method. The method chosen applies to averaging for each individual virtual circuit and also for the total ALC output traffic. BAS: Buffer Ageing Support. This bit is set to support receive buffer ageing. For a full description of this function, please refer to section 3.1.6. VPF: Virtual Path Filter Enable. If this bit is set then only incoming cells whose VPI matches the value specified in the Receive Address Filter Register are processed. If this bit is cleared then the incoming VPI value is ignored. HEC2 - HEC0: Header Error Check Operation. Cell header error check mask byte value. HEC2 = 0 Mask = 0x55. HEC2 = 1 Mask = 0x00. HEC1 = 0 Transmitted cell header check octet included ( 53 byte cell ). HEC1 = 1 Transmitted cell header check octet omitted (52 byte cell ). HEC0 = 0 Cell header error checking enabled. HEC0 = 1 Cell header error checking disabled. Fig. 43 - REGISTER 17 66 Edition 2.0 MB86687A APPENDICES Register 17 - Mode Register (continued) D15 TRTL1 BCHAIN TRTL0 SMODE AM DCHAIN BAS DMASK VPF HEC2 0 RID HEC1 HEC0 RTL1 RTL0 D0 BCHAIN: Receive Buffer Chaining Mode Enable Set to enable chaining mode whereby a single packet may be located in different reassembly buffers each described by a different descriptor but linked using pointers into a single chain. Cleared to disable buffer chaining. SMODE: Receive Streaming Mode Enable Set to enable ALC streaming mode whereby processing of large received packets can begin before all the packet data is available. Cleared to disable streaming mode. DCHAIN: Transmit Cell Stream Daisy Chain Enable Set to allow multiple ALC devices to share a single network interface device by using token passing. Cleared if using a single ALC device per network interface device. DMASK: Disable Transmit Queue Masking Set to disable automatic service request masking from medium and low priority queues when the total ALC data rate limit is exceeded. Cleared to enable masking. ie. DMASK = 0 High Queue Enabled Only DMASK = 1 Low, Medium and High Queues Enabled RID: Reassembly ID Select (applies to entire receive side of the ALC) RID = 0: VCI is used for addressing. RID = 1: MID field is used for addressing. RTL1-RTL0: Receive Routing Tag Length This field specifies the length (if any) of routing tag expected to be appended to received cells. 00: No Routing Tag 01: One Octet Routing Tag 10: Two Octet Routing Tag 11: Three Octet Routing Tag. Fig. 44 - REGISTER 17 (continued) 67 MB86687A APPENDICES Edition 2.0 Register 18 - Interrupt Status / Service Register D15 X TAC PARERR RFE CEC GFCC DTCOM RRCOM TRF TRW RRFL RRFU SRCOM BUSERR RRW INIT D0 On detection of an interrupt condition the ALC sets an interrupt flag in this register. If the corresponding interrupt mask bit in Register 19 is set then the ALC activates the output interrupt pin. The host processor may determine the interrupt cause by reading this register. An interrupt is cleared and disabled by writing a "1" to the associated bit and re-enabled by writing a "0". TAC: Receive Status / Descriptor Table Access Complete. Set when the host read or write access to the receive status/ descriptor table as requested through register 59 has completed. RFE: Receive Buffer Free Queue Empty. Set if no receive buffer descriptors are available for ALC use. Host must service previously received packets. TRF: Transmit Buffer Release Queue Full. Set if the last available location in the transmit buffer release queue has been used by the ALC. The host must respond to previously completed transmissions by reading the transmit release queue entries. TRW: Transmit Buffer Release Queue Write. Set when the ALC has completed the requested packet transmission. Host should acknowledge this by reading the corresponding release queue entry. RRFL: Receive Buffer Ready Queue Write Fail. Set if the ALC attempts to write to an already full receive buffer ready queue. The host must service previously received packets. RRFU: Receive Buffer Ready Queue Full. Set when the receive buffer ready queue is full. The host must service previously received packets. RRW: Receive Buffer Ready Queue Write. Set when the ALC has completed reception of a packet (or number of packets - see register 16). Host must acknowledge reception by reading the associated receive buffer ready queue entry. INIT: Initialisation Complete. Set when the ALC internal initialisation is complete. Fig. 45 - REGISTER 18 68 Edition 2.0 MB86687A APPENDICES Register 18 - Interrupt Status Register (continued) D15 X TAC PARERR RFE CEC GFCC DTCOM RRCOM TRF TRW RRFL RRFU SRCOM BUSERR RRW INIT D0 PARERR: . Parity Error on DMA Interface CEC: Congestion Experienced Change. Circuit Changed in register 13 GFCC: GFC Field Change (UNI Mode only). Circuit changed in register 13 DTCOM: Descriptor Table Test Complete. Set by the ALC to indicate that the ALC's internal RSD memory test has completed. RRCOM: Receive RAM Test Complete. Set by the ALC to indicate that the ALC's internal receive scratch pad memory test has completed. SRCOM: Send RAM Test Complete. Set by the ALC to indicate that the ALC's internal transmit scratch pad memory test has completed. These three fields are used only during the manufacturing phase. BUSERR Set by the ALC in Fast Mode when host activates the DTACK/READY input to indicate a bus error Register 19 - Interrupt Mask Register This interrupt mask register contains one bit for each possible interrupt source as described for the Interrupt Status Register 18. above. Each interrupt condition can be enabled to activate the ALC's output interrupt signal by setting the corresponding interrupt mask bit in this register. Likewise each interrupt source can be prevented from activating the external interrupt pin by clearing the corresponding bit in this register. For each mask location: 0 = Interrupt generation masked. 1 = Interrupt generation enabled. In addition this register, when read indictes the revision of the MB86687A. This is set to 0xXX01h. Fig. 46 - REGISTER 18 (continued) and 19 1 = Interrupt generation enabled 69 MB86687A APPENDICES Edition 2.0 Registers 20 to 31 - Transmit Queue Service Rate Registers D15 X X X SR7 SR6 SR5 X SR4 X X SC1 SC0 SR3 SR2 SR1 SR0 D0 The Service Rate counters are used to implement leaky bucket traffic management on each of the ALC's 12 peak rate queues. Bits SR7 - SR0 are used to specify the rate at which tokens are removed from the leaky buckets of each circuit associated with that queue. In single leaky bucket mode this value determines the rate of cell transmission during the initial burst. In double leaky bucket mode this value determines the rate of cell transmission in each burst. The counter value specified is decremented using a scaled version of the input transmission clock (TCLK). TCLK is divided by the scaling factor specified in bits SC0 and SC1 of this register as shown below. Each time the counter reaches zero it is reloaded to its initial value. SC1 0 0 1 1 Note: SC0 0 1 0 1 Scaling Factor 4 16 64 256 The maximum value which SR0 - SR7 can take is given by: L SCP Where L is cell width in nano-seconds, SCP the selected counter period integer multiple of the system clock period. This maximum value corresponds to a single active Virtual Circuit using the total link capacity. Register 20 = LP1 Register 31 = HP4 Fig. 47 - REGISTERS 20 to 31 70 Edition 2.0 MB86687A APPENDICES Register 32 - Transmit Queue Service Enable Register D15 X ENM3 X ENM4 ENL1 ENL2 ENL3 ENL4 ENM1 ENM2 ENH1 ENH2 ENH3 ENH4 ENAP ENAA D0 Servicing of each of the 12 available transmission descriptor queues can be enabled by setting and disabled by clearing their respective peak cell transmission rate counter enables as shown below. Also the total ALC peak and average rate counters can be individually enabled by setting and disabled by clearing the ENAP and ENAA bits respectively. Low Priority Transmit Queue Service Enables: ENL1: ENL2: ENL3: ENL4: Enable counter for low priority service queue 1 Enable counter for low priority service queue 2 Enable counter for low priority service queue 3 Enable counter for low priority service queue 4 Medium Priority Transmit Queue Service Enables: ENM1: ENM2: ENM3: ENM4: Enable counter for medium priority service queue 1 Enable counter for medium priority service queue 2 Enable counter for medium priority service queue 3 Enable counter for medium priority service queue 4 High Priority Transmit Queue Service Enables: ENH1: ENH2: ENH3: ENH4: Enable counter for high priority service queue 1 Enable counter for high priority service queue 2 Enable counter for high priority service queue 3 Enable counter for high priority service queue 4 Total ALC Traffic Management Counter Enables: ENAP: Enable counter for ALC peak transmission rate. ENAA: Enable counter for ALC average transmission rate. Fig. 48 - REGISTER 32 71 MB86687A APPENDICES Edition 2.0 Register 33 - ALC Peak Cell Transmission Rate Register D15 X X PR7 PR6 X X PR5 PR4 X PR3 X PS1 PS0 PR2 PR1 PR0 D0 This total ALC output peak rate counter is used to implement leaky bucket traffic management on the ALC's transmitted cell stream. Bits PR7 - PR0 are used to specify the rate at which tokens are removed from the leaky bucket. In single leaky bucket mode this value determines the rate of cell transmission during the initial burst. In double leaky bucket mode this value determines the rate of cell transmission in each burst. The counter value specified is decremented using a scaled version of the input transmission clock (TCLK). TCLK is divided by the scaling factor specified in bits PS0 and PS1 of this register as shown below. Each time the counter reaches zero it is reloaded to its initial value. PS1 0 0 1 1 PS0 0 1 0 1 Scaling Factor 1 2 4 8 Register 34 - ALC Average Cell Transmission Rate Register D15 X X AR7 AR6 X X X X AS1 AS0 AR5 AR4 AR3 AR2 AR1 AR0 D0 This total ALC output average rate counter is used to implement leaky bucket traffic management on the ALC's transmitted cell stream. Bits AR7 - AR0 are used to specify the rate at which tokens are removed from the leaky bucket. In single leaky bucket mode this value determines the rate of cell transmission during the initial burst. In double leaky bucket mode this value determines the length of time that the output cell stream is idle between bursts. The counter value specified is decremented using a scaled version of the input transmission clock (TCLK). TCLK is divided by the scaling factor specified in bits AS0 and AS1 of this register as shown below. Each time the counter reaches zero it is reloaded to its initial value. AS1 0 0 1 1 AS0 0 1 0 1 Scaling Factor 1 2 4 8 Fig. 49 - REGISTER 33 AND 34 72 Edition 2.0 MB86687A APPENDICES Register 35 - ALC Leaky Bucket Capacity Register D15 X LBC7 X LBC6 X LBC5 X LBC4 X LBC3 X LBC2 X LBC1 X LBC0 D0 This register specifies the number of tokens held in the ALC total traffic management leaky bucket. This parameter together with the ALC peak transmission rate register setting and the ALC average transmission rate register setting determines the total cell transmission rate at the ALC's output. This capacity value can be used together with the ALC peak cell rate and average cell rate to calculate the maximum burst length of transmitted cells generated by the ALC. For Single Leaky Bucket Mode: M = (B-1) x (1-U) Note that M 0 In this case a minimum allowed value of B is specified for each selected U. U = 0.875 minimum B = 9. U = 0.75 minimum B = 5 U = 0.625 minimum B = 4 All other values of U minimum B = 3. For Double Leaky Bucket Mode: M = B x (1-U) B = maximum number of cells in the output burst. M = leaky bucket capacity as specified in LBC7 - LBC0 U = utilisation = average cell output rate / peak cell output rate = (AR7 - AR0) / (PR7 - PR0) Note: If the resulting value of M is not a positive integer then in the single leaky bucket method it should be rounded DOWN to the nearest positive integer and in the double leaky bucket method it should be rounded UP to the next positive integer. Fig. 50 - REGISTER 35 73 MB86687A APPENDICES Edition 2.0 Register 40 - Receive Queue Base Address Register D15 NAM SIFC ADCCK ARXCLK DMID X RQA7 RQA6 RQA5 RQA4 RQA3 RQA2 RQA9 RQA8 RQA1 RQA0 D0 This register contains the upper10 bits of both the Recieve Buffer Free Queue and Buffer Ready Queue addresses. This base address is concatenated with the start or end address (shifted left by 1 bit) or with the write or read pointers (shifted left by 1 bit) to obtain the upper 23 bits of the system or dual port SAR memory address of the Pending or Release Queue entry. Address bit 0 is always set to 0 by the ALC. NAM: Non Assured Mode - If set the ALC receive will dma out to system memory the AAL5 SAR payload within the trailer cell even if the packet CRC32 check fails. SIFC: Streaming Interrupt First Cell - If set, after writing out the payload from the first cell of a packet the ALC will write the receive descriptor to the RBRQ and generate an RRW interrupt. ADCCK: Set if microprocessor reads are asynchronous to DCCK. ARXCLK: Set if microprocessor reads are asynchronous to RXCLK. DMID: For AAL3/4 receive traffic. If set, the ALC will not discard cells with non-zero MID fields. Register 41 - Receive Buffer Free Queue Start Address Register D15 X X X RBFS12 RBFS11 RBFS10 RBFS9 RBFS8 RBFS7 RBFS6 RBFS5 RBFS4 RBFS3 RBFS2 RBFS1 RBFS0 D0 This offset address is shifted left by one bit and concatenated to the Recieve Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Recieve Pending Queue start address. This start address indicates the beginning of the Recieve Pending Queue space which is used to pass recieve request buffer descriptor addresses from the Host to the ALC. Address bit 0 is always be set to 0 by the ALC. Fig. 51 - REGISTERS 40 and 41 74 Edition 2.0 MB86687A APPENDICES Register 42 - Receive Buffer Free Queue End Address Register D15 X X X RBFE12 RBFE11 RBFE10 RBFE9 RBFE8 RBFE7 RBFE6 RBFE5 RBFE4 RBFE3 RBFE2 RBFE1 RBFE0 D0 This offset address is shifted left by one bit and concatenated to the Recieve Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Recieve Pending Queue end address. This end address indicates the finish of the Receive Pending Queue space which is used to pass Receive request buffer descriptor addresses from the Host to the ALC. Address bit 0 is always set to 0 by the ALC. Register 43 - Receive Buffer Free Queue Write Pointer D15 INCWRAP RBFW7 EMPTY FULL RBFW6 RBFW5 RBFW12 RBFW4 RBFW11 RBFW10 RBFW9 RBFW8 RBFW3 RBFW2 RBFW1 RBFW0 D0 This offset address is shifted left by 1 bit and concatenated to the Receive Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the Receive Pending Queue write pointer. The Host uses this pointer when entering Receive requests by writing a receive descriptor reference address to the Receive pending queue. Address bit 0 is always be set to 0 by the ALC. INCWRAP - When writing to the host-controlled queue registers, if the most significant bit of the control data bus is set, the ALC will automatically increment its internal copy of the pointer being written to regardless of the pointer value specified on the data bus. EMPTY - If this bit is set, it indicates that the ALC's pointer for the queue is at the same value as the host pointer's value returned by the read and that the queue is empty. FULL - If this bit is set, it indicates that the host pointer and ALC pointer values are the same and that the queue is full. Register 44 - Receive Buffer Free Queue Read Pointer D15 X RBFR7 X RBFR6 ASYNCI RBFR12 RBFR11 RBFR10 RBFR9 RBFR8 RBFR5 RBFR4 RBFR3 RBFR2 RBFR1 RBFR0 D0 This offset address is shifted left by 1 bit and concatenated to the Receive Queue Base Address Register contents ( shifted left by 14 bits ) to obtain the upper 23 bits of the Receive Pending Queue read pointer. The ALC uses this pointer when retrieving transmit requests by reading a receive descriptor reference address from the Receive Pending Queue. Address bit 0 is always set to 0 by the ALC. Please refer to Register 6 on page 58 for a description of ASYNCI. Fig. 52 - REGISTER 42, 43 AND 44 75 MB86687A APPENDICES Edition 2.0 Register 45 - Receive Descriptor Table Base Address Register D15 RDA15 RDA14 RDA13 RDA12 RDA11 RDA10 RDA9 RDA8 RDA7 RDA6 RDA5 RDA4 RDA3 RDA2 RDA1 RDA0 D0 This base address (shifted left by 8 bits) is added to the 12 bit receive descriptor address (shifted left by 5 bits) from the Receive Buffer Ready Queue or Receive Buffer Free queue entry to obtain the full 24 bit address of the receive descriptors. Register 46 - Receive Buffer Ready Queue Start Address Register D15 X X X RBRS12 RBRS11 RBRS10 RBRS9 RBRS8 RBRS7 RBRS6 RBRS5 RBRS4 RBRS3 RBRS2 RBRS1 RBRS0 D0 This offset address shifted left by 1 bit is concatenated to the Receive Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Receive Release Queue start address. This start address indicates the beginning of the Receive Release Queue space used by the ALC to indicate the availability of free Receive descriptors to the host. Address 0 is always set to 0. Register 47 - Receive Buffer Ready Queue End Address Register D15 X X X RBRE12 RBRE11 RBRE10 RBRE9 RBRE8 RBRE7 RBRE6 RBRE5 RBRE4 RBRE3 RBRE2 RBRE1 RBRE0 D0 This offset address shifted left by 1 bit is concatenated to the Receive Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Receive Release Queue end address. This end address indicates the finish of the Receive Release Queue space used by the ALC to indicate the availability of free Receive descriptors to the host. Address 0 is always set to 0. Fig. 53 - REGISTER 45, 46 AND 47 76 Edition 2.0 MB86687A APPENDICES Register 48 - Receive Buffer Ready Queue Write Pointer D15 X X ASYNCI RBRW12 RBRW11 RBRW10 RBRW9 RBRW8 RBRW7 RBRW6 RBRW5 RBRW4 RBRW3 RBRW2 RBRW1 RBRW0 D0 This offset address is shifted left by 1 bit and concatenated to the Receive Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Receive Buffer Ready Queue write pointer. The ALC uses this pointer to write the address of the Receive Descriptor for a received packet which has been reassembled and placed in the receive buffer. Address bit 0 is always set to 0. Please refer to Register 6 on page 58 for a description of ASYNCI. Register 49 - Receive Buffer Ready Queue Read Pointer D15 INCWRAP RBRR7 EMPTY FULL RBRR12 RBRR11 RBRR10 RBRR9 RBRR8 RBRR6 RBRR5 RBRR4 RBRR3 RBRR2 RBRR1 RBRR0 D0 This offset address is shifted left by 1 bit and concatenated to the Receive Queue Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the Receive Buffer Ready Queue read pointer. The Host uses this pointer to read the address of the Receive Descriptor for a received packet which has been reassembled and placed in the receive buffer. Address bit 0 is always set to 0. Register 50 - Dropped Packet Counter D15 ASYNCI DPC7 DPC14 DPC13 DPC12 DPC11 DPC10 DPC9 DPC8 DPC6 DPC5 DPC4 DPC3 DPC2 DPC1 DPC0 D0 This counter is incremented each time a received packet is lost due to no receive buffers being available to start reassembly of the incoming data. N.B. This register is not cleared when read unlike previous revisions of the ALC. Please refer to Register 6 on page 58 for a description of ASYNCI. Fig. 54 - REGISTER 48, 49 AND 50 77 MB86687A APPENDICES Edition 2.0 Register 51 - Receive Buffer Time Out Counter Period Register D15 BTC15 BTC14 BTC13 BTC12 BTC11 BTC10 BTC9 BTC8 BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0 D0 The value in this register represents the number of DCCK clock periods required to increment the receive buffer ageing time base counter. this value is used to pre scale the ALC input DCCK clock before clocking the ALC's time base counter. The time base counter is used to check for receive buffer time out conditions. Register 52 - Receive Buffer Time Out Counter Interval Register D15 BTI15 BTI7 BTI14 BTI6 BTI13 BTI12 BTI11 BTI10 BTI9 BTI8 BTI5 BTI4 BTI3 BTI2 BTI1 BTI0 D0 The value written to this register defines the maximum time period allowed between the arrival of a incoming packet and the host servicing the receive buffer. If the time required by the host to service received packets exceeds this value then the Received Buffer Ready Queue Status code of 1100b indicating receive buffer timeout condition is written to the Receive Buffer Ready Queue entry corresponding to that channel. The ALC's time base counter is incremented using the DCCK clock pre-scaled by the value in the Receive Buffer Time Out Counter Period register as described above. Fig. 55 - REGISTERS 51 AND 52 78 Edition 2.0 MB86687A APPENDICES Register 53 - Receive Buffer Ready Data Hold Register D15 DHR15 DHR14 DHR13 DHR12 DHR11 DHR10 DHR9 DHR8 DHR7 DHR6 DHR5 DHR4 DHR3 DHR2 DHR1 DHR0 D0 When the ALC receives an incoming packet while only a single location is available in the Receive Buffer Ready Queue, writing the Receive Buffer entry corresponding to this packet will cause the generation of the Receive Buffer Ready Queue Full Interrupt . If a further packet is received after this interrupt but before the host has serviced the Receive Buffer Ready Queue then no Receive Buffer Ready queue space is available to hold the packet received indication. In this case the ALC instead writes the Receive Buffer Ready Queue entry to this Receive Buffer Ready Data Hold Register and generates the Receive Buffer Ready Queue Write Fail interrupt. Note that if additional packets are received the value in this register will be overwritten with the most recently received packet's Receive Buffer Ready Queue entry data. Register 54 - Maximum Received Packet Length Register D15 MPL15 MPL14 MPL13 MPL12 MPL11 MPL10 MPL9 MPL8 MPL7 MPL6 MPL5 MPL4 MPL3 MPL2 MPL1 MPL0 D0 This register contains the maximum number of bytes of incoming packet data that can be received by the ALC. If the length of the received packet exceeds this number then the ALC will deliver the packet but drop the cells beyond the level programmed. Fig. 56 - REGISTER 53 AND 54 79 MB86687A APPENDICES Edition 2.0 Register 55 - Dropped Cell Counter D15 ASYNCI DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 D0 This counter value is incremented each time a received cell is dropped by the ALC due to: 1) Cell received for a packet which the receive has previously aborted due to: Buffer overflow No buffers available No chaining buffers available Buffer time out Maximum packet length exceeded 2) EOM/COM received with no BOM (for AAL3/4) 3) CRC10 error (with RID=0 CR17, VCI used for addressing) (for AAL3/4) 4) Non-zero MID (with RID=0 CR17, VCI used for addressing and DMID=0) (for AAL3/4) N.B. This register is not cleared when read unlike previous revisions of the ALC. Please refer to Register 6 on page 58 for a description of ASYNCI. Register 56 - Receive Address Filter Register D15 AF15 AF14 AF13 AF12 AF11 AF10 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0 D0 Address Filter These bits, together with AF17 and AF16 in Register 16, are used as a filter for those address bits not covered in the 10 bits of the ALC mapped address. Fig. 57 - REGISTER 55 AND 56 80 Edition 2.0 MB86687A APPENDICES Register 57 - Host Receive Descriptor / Status Table Read Register D15 DP DSC5 RIP DSC11 DSC10 DSC9 DSC8 DSC7 DSC6 DSC4 DSC3 DSC2 DSC1 DSC0 ACT DCRD D0 This register is used by the host to read the Receive Descriptor / Status Table. This table specifies the location and status of specific receive channel descriptors. DSC0 - DSC11: Receive descriptor pointer for this Receive Circuit Reference. DP: Receive descriptor pointer in DSC0 - DSC11 above is valid. RIP: Reception in progress on the Receive Circuit Reference corresponding to this entry. ACT: Active monitoring of the Receive Circuit Reference corresponding to this entry. DCRD: Discard in progress on the channel referenced by this entry. Register 58 - Host Receive Descriptor / Status Table Write Register D15 DP RIP DSC11 DSC10 DSC9 DSC8 DSC7 DSC6 DSC5 DSC4 DSC3 DSC2 DSC1 DSC0 ACT DCRD D0 This register is used in conjunction with the Host Receive Descriptor / Status Table Access Register by the host to write Receive Descriptor / Status Table entries. The host normally accesses this table only during initialisation. DSC0 - DSC11: Receive descriptor pointer for this Receive Circuit Reference. DP: Receive descriptor pointer in DSC0 - DSC11 above is valid. RIP: Set Receive in progress on the Receive Circuit Reference corresponding to this entry. ACT: Activate monitoring of the Receive Circuit Reference corresponding to this entry DCRD: Discard received packets on the channel referenced by this entry. Fig. 58 - REGISTER 57 AND 58 81 MB86687A APPENDICES Edition 2.0 Register 59 - Host Receive Descriptor / Status Table Access Register D15 HOSTR RCR7 RD/WR AAL TYP0 AAL TYP1 RES RES RCR9 RCR8 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0 D0 This register is used, together with registers 57 and 58 to gain read and write access to the ALC's internal Receive Descriptor / Status Table. The tables need to be accessed by the host for initialization, scatter/gather mode and emergency buffer recovery. When the Host Access Request (HOSTR) bit is set and the read/write control (RD/WR) bit is SET, the contents of register 58 and the AAL Type bits are written to the table entry at the address indicated by RCR 0:9. The ALC will generate a TAC interrupt to indicate that the write operation is complete. When the Host Access Request (HOSTR) bit is set and the read/write control bit (RD/WR) is CLEARED, the ALC is configured to read the internal Receive Descriptor / Status Table entry at the address indicated by RCR 0:9. The ALC will generate a TAC interrupt to indicate that the read operation is complete. At this time Register 57 will contain the requested table entry contents. RCR0 -RCR9: This is the Table address Receive Circuit Reference. AAL TYP: 00 01 10 11 HOSTR: Set to 1: Cleared to 0: Host Access Requested Host Access Completed. RD/WR: Set to 1: Cleared to 0: Write Request Read Request. AAL3/4 Transparent Mode Transparent Cell Mode AAL5. Fig. 59 - REGISTER 59 82 Edition 2.0 MB86687A APPENDICES C. AC TIMINGS Parameter Signal g Abbrev Values Min Typical Max Units (ns) Setup time of TDI TDI 1 ns Hold time of TDI TDI 2 ns TDO delay TDO 5 TMS setup TMS 4 ns TMS hold TMS 2 ns 13 ns Table 3 - JTAG Interface Timing DCCK tDCKH tDCKL tDCLK Fig. 60 - System Clock Timing RESET tRST Fig. 61 - Reset Timing Parameter Signal g Abbrev Values Min Typical Max Units (ns) Clock High Time DCCK tDCKH 13 ns Clock Low Time DCCK tDCKL 15 ns Clock Period DCCK tDCLK 30* ns Reset Pulse Width RESET tRST 10 tDCLK ns Table 4 - Miscellaneous - AC Timing Parameters * Note: When the device is configured for Single cycle operation with 0 wait states the clock period is restricted to 40ns Note: On the following pages the following notation is used: RMOD=0/1 means normal/extended read mode - CR15 RMOD bit WMOD=0/1 means normal/extended write mode - CR15 WMOD bit ASYNC/SYNC means asynchronous/synchronous DMA interface - CR15 SYN bit 83 MB86687A APPENDICES Edition 2.0 TXCLK tTCKL tTCKH tTCLK RXCLK tRCKL tRCKH tRCLK Fig. 62 - Cell Stream Clock Timing Parameter Signal g Abbrev Values Min Typical Max Units (ns) Transmit Clock High Time TXCLK tTCKH 18 ns Transmit Clock Low Time TXCLK tTCKL 18 ns Transmit Clock Period TXCLK tTCLK 40* ns Receive Clock High Time RXCLK tRCKH 16 ns Receive Clock Low Time RXCLK tRCKL 17 ns Receive Clock Period RXCLK tRCLK 40* ns Table 5 - Cell Stream Interface clocks - AC Timing Parameters 84 * Note: In Fujitsu Cell Stream Mode the clock period is restricted to 50ns. * Note: The period of TXCLK and RXCLK must be greater or equal to the period of DCCK. Edition 2.0 MB86687A APPENDICES TXCLK tOCI tOC TXD0-7 Output Data Byte 1 Output Data Byte 2 Output Data Byte 3 TXSOC Fig. 63 - Cell Stream Interface Transmit Port (Fujitsu Mode) Timing RXCLK tDS RXD0-7 Input Data tOC tOC tDH Input Data Input Data Input Data RXSOC RXEN Fig. 64 - Cell Stream Interface Receive Port (Fujitsu Mode) Timing Parameter Signal g Abbrev Values Min Typical Max 20 Units (ns) TXSOC, TXD Active Delay TXCLK tOC 10 TXD Inactive Delay TXCLK tOCI 5 ns RXSOC, RXD Setup Time RXCLK tDS 0 ns RXSOC, RXD Hold Time RXCLK tDH 6 ns RXEN Delay RXCLK tOC 14 23 ns ns Table 6 - Cell Stream Interface Fujitsu Mode - AC Timing Parameters 85 MB86687A APPENDICES Edition 2.0 TXCLK tOC tOCI TXD0-7 TXSOC tDS tDH TXFULL tOC tOC TXEN Fig. 65 - Cell Stream Interface Transmit Port (Utopia mode) Timing RXCLK tDS tDH RXD0-7 RXSOC tOC tOC RXEN tDS tDH RXEMPTY Fig. 66 - Cell Stream Interface Receive Port (Utopia mode) Timing Parameter Signal g Abbrev Values Min Typical Max 22 Units (ns) TXSOC, TXD, TXEN Delay TXCLK tOC 8 TXD Inactive Delay TXCLK tOC 5 ns TXFULL Setup Time TXCLK tDS 2 ns TXFULL Hold Time TXCLK tDH 2 ns RXSOC, RXD, RXEMPTY Setup RXCLK tDS 0 ns RXSOC, RXD, RXEMPTY Hold RXCLK tDH 6 ns RXEN Delay RXCLK tOC 15 28 ns ns Table 7 - Cell Stream Interface UTOPIA Mode - AC Timing Parameters 86 Edition 2.0 MB86687A APPENDICES Token Transmit TXCLK tOC II tOC TOUT tDS tDH TIN Token Receive Fig. 67 - CSI Token Transmit and Receive Timing Parameter Signal g Abbrev Values Min Typical Max Units (ns) TIN Setup Time TXCLK tDS 0 ns TIN Hold Time TXCLK tDH 5 ns TOUT Delay TXCLK tOC 11 20 ns Table 8 - Cell Stream Interface Token Passing - AC Timing Parameters 87 MB86687A APPENDICES CS Edition 2.0 NNN tCSRD A1-A6 Valid Address tARD D0-D15 Valid Data tRDD tDRD II I II I RD tAHR NNN NNN tRDCS Fig. 68 - Microprocessor Interface - Read Timing CS NNN tCSWR A1-A6 Valid Address tAWR D0-D15 Valid Data tDS WR II II I tDH NNN NNN tAHW tWRW tWRCS Fig. 69 - Microprocessor Interface - Write Timing 88 Edition 2.0 MB86687A APPENDICES Parameter Signal g Abbrev Values Min Typical Max Units (ns) Address Valid to Read Active RD tARD 0 ns CS Valid to Read Active RD tCSRD 0 ns Read Active to Valid Data RD tRDD 19 Read Inactive to Invalid Data RD tDRD 5 ns Read Active to Invalid Address RD tAHR 6 ns Read Inactive to CS Inactive RD tRDCS 0 ns Address Active to Write Active WR tAWR 0 ns CS Valid to Write Active WR tCSWR 0 ns Write Pulse Width WR tWRW 5 ns Data Setup Time WR tDS 5 ns Data Hold Time WR tDH 1 ns Write Active to Invalid Address WR tAHW 6 ns Write Inactive to CS Inactive WR tWRCS 0 ns 36 ns Table 9 - Microprocessor Interface - AC Timing 89 MB86687A APPENDICES Edition 2.0 tWWD II WR Fig. 70 - Microprocessor Interface - Write to Write Timing DCCK tIRQI tIRQA IRQ tIRQDEL RD tWRIRQI WR Fig. 71 - Microprocessor Interface - Interrupt Timing Parameter Signal g Abbrev Values Min Typical Max Units (ns) Write to Write Delay - DCCK WR tWWD 4DCCK ns Write to Write Delay - TXCLK WR tWWT 4TXCLK* ns IRQ Active Delay IRQ tIRQA 9 16 ns 3DCCK 4DCCK ns 40 ns WR Inactive to IRQ Inactive WR IRQ tWRIRQI IRQ Inactive Delay IRQ tIRQI IRQ Inactive to Active IRQ tIRQDEL 2DCCK ns Table 10 - Microprocessor Interface - AC Timing *Note: 90 See Fig. 30 - ALC Register Map, registers marked (T) denotes TXCLK write recovery. Edition 2.0 MB86687A APPENDICES DCLK tHOLDI tHOLDA HOLD tHLDAS tHLDAH HLDA BGACK tADDRAZ A2-A23 BE0-3 RD & WR tADDRIZ u processor ALC bus valid u processor Fig. 72 - Microprocessor Interface - Intel DMA Access Timing (SYNC) DCLK tHOLDI tHOLDA HOLD tHLDAS HLDA tHLDAH BGACK tADDRAZ A2-A23 BE0-3 RD & WR u processor tADDRIZ ALC bus valid u processor Fig. 73 - Microprocessor Interface - Intel DMA Access Timing (ASYNC) 91 MB86687A APPENDICES Edition 2.0 DCLK tHOLDA tHOLDA HOLD tHLDAS tHLDAS tHOLDI HLDA tHLDAH BGACK tADDRIZ tADDRAZ A2-A23 BE0-3 RD & WR u processor ALC bus valid Fig. 74 - Microprocessor Interface - Intel DMA Access Control Override Timing Parameter Signal g Values Abbrev Min 8 Typical Max Units (ns) HOLD Active Delay HOLD tHOLDA 14 ns HOLD Inactive Delay - ASYNC HOLD tHOLDI 75 ns HOLD Inactive Delay -SYNC HOLD tHOLDI 10 22 ns Setup Time of HLDA Active - ASYNC HLDA tHLDAS 1 ns Setup Time of HLDA Active - SYNC HLDA tHLDAS 7 ns Hold Time of HLDA Invalid - ASYNC HLDA tHLDAH 1 ns Hold Time of HLDA Invalid - SYNC HLDA tHLDAH 2 ns ALC Bus Active Delay A2-A23, BE3-0, MRD, MWR, tADDRAZ 5 ALC Bus Inactive Delay A2-A23, BE3-0, MRD, MWR tADDRIZ 16 ns 75 ns Table 11 - Microprocessor Interface - Intel DMA Access AC Timing 92 Edition 2.0 MB86687A APPENDICES DCLK tBRA tBRI BR tBGH tBGS BG tADDRA BGACK A2-A23, SIZ0-1, DS, AS & R/W tADDRIZ u processor u processor ALC bus valid Fig. 75 - Microprocessor Interface - Motorola DMA Access Timing (SYNC) DCLK tBRI tBRA BR tBGS tBGH BG tADDRIZ BGACK tADDRA A2-A23, SIZ0-1, DS, AS & R/W u processor ALC bus valid u processor Fig. 76 - Microprocessor Interface - Motorola DMA Access Timing (ASYNC) 93 MB86687A APPENDICES Parameter Edition 2.0 Signal g Abbrev Values Min Max BR Active Delay BR tBRA BR Inactive Delay - ASYNC BR tBRI BR Inactive Delay - SYNC BR tBRI 10 Setup Time of BG, AS & BGACK Active - ASYNC BG tBGS 1 ns Setup Time of BG, AS & BGACK Active - SYNC BG tBGS 8 ns Hold Time of BG, AS & BGACK Invalid - ASYNC BG tBGH 1 ns Hold Time of BG, AS & BGACK Invalid - SYNC BG tBGH 0 ns 5 ALC Bus Active Delay A2-A23, SIZ0-1, DS, AS, R/W tADDRAZ ALC Bus Inactive Delay A2-A23, SIZ0-1, DS, AS, R/W tADDRIZ 8 Typical Units (ns) 14 ns 75 ns 22 ns 16 ns 75 ns Table 12 - Microprocessor Interface - Motorola DMA Access AC Timing 94 Edition 2.0 MB86687A APPENDICES DCCK tADDRA tADDRI tRDA A2-A23 tRDW BE0 BE1 BE2 BE3 tDATS tRDI RD tDATH D0-D31 DATA tRDYH READY tRDYS tCSA tCSI **CS (TOCS etc) Fig. 77 - DPR / DMA Interface - Intel Read Cycle (SYNC) DCCK tADDRA tADDRI tRDA A2-A23 tRDW BE0 BE1 BE2 BE3 tRDI RD tDATS tDATH DATA D0-D31 tRDYS tRDYH READY tCSA tCSI **CS (TOCS etc) Fig. 78 - DPR / DMA Interface - Intel Read Cycle (ASYNC) 95 MB86687A APPENDICES Edition 2.0 DCCK tADDRA tADDRI A2-A23 BE0 BE1 BE2 BE3 tWRW tWRA tWRI WR tDATI tDATA D0-D31 DATA tRDYS READY tRDYH Fig. 79 - DPR / DMA Interface - Intel Write Cycle (SYNC) DCCK tADDRA tADDRI A2-A23 BE0 BE1 BE2 BE3 tWRW tWRA tWRI WR tDATI tDATA D0-D31 DATA tRDYS tRDYH READY Fig. 80 - DPR / DMA Interface - Intel Write Cycle (ASYNC) 96 Edition 2.0 MB86687A APPENDICES Parameter Signal g Abbrev Values Min Address Active Delay Typical Max Units (ns) A2-A23 tADDRA 15 28 ns BE Active Delay - non burst BE0-BE3 tADDRA 13 22 ns BE Active Delay - burst BE0-BE3 tADDRA 15 24 ns A2-A23 tADDRI 5 Address BE Inactive Delay ns Read Active Delay RD tRDA 10 17 ns Read Inactive Delay - RMOD=0 RD tRDI 9 16 ns Read Inactive Delay - RMOD=1 RD tRDI 9 16 ns Setup Time of Ready - ASYNC READY tRDYS 1 ns Setup Time of Ready - SYNC READY tRDYS 2 ns Hold Time of Ready - ASYNC READY tRDYH 2 ns Hold Time of Ready - SYNC READY tRDYH 1 ns Read Active Width (RMOD=0) RD tRDW tDCCK - 1ns ns Setup Time of Data - RMOD=0 D0-D31 tDATS 0 ns Setup Time of Data - RMOD=1 D0-D31 tDATS 6 ns Hold Time of Data - RMOD=0 D0-D31 tDATH 10 ns Hold Time of Data - RMOD=1 D0-D31 tDATH 7 ns Write Active Delay WR tWRA 10 17 ns Write Inactive Delay - WMOD=0 WR tWRI 9 16 ns Write Inactive Delay - WMOD=1 WR tWRI 9 16 ns Write Active Width (WMOD=0) WR tWRW tDCCK - 1ns Write Data Active Delay D0-D31 tDATA 13 Write Data Inactive delay D0-D31 tDATI 5 Parity Active delay PRTY 0-3 ns 22 ns ns 15 24 ns Cycle Start Active delay **CS tCSA 11 20 ns Cycle State Inactive delay **CS tCSI 9 17 ns Table 13 - DPR / DMA Interface - Intel Cycle AC Timing 97 MB86687A APPENDICES Edition 2.0 DCCK tADDRA tADDRI tASDSA A0-A23 SIZ0, SIZ1 tASDSW AS tASDSI DS tDATH tDATS D0-D31 DATA tDTKH DTACK tDTKS Fig. 81 - DPR / DMA Interface - Motorola Read Cycle (SYNC) DCCK tADDRA tADDRI tASDSA A0-A23 SIZ0, SIZ1 AS tASDSW tASDSI DS tDATH tDATS D0-D31 DATA tDTKS tDTKH DTACK Fig. 82 - DPR / DMA Interface - Motorola Read Cycle (ASYNC) 98 Edition 2.0 MB86687A APPENDICES DCCK tADDRI tADDRA tDSA A0-A23 SIZ0, SIZ1 R/W tDATA tASA tASDSI AS tASW DS tDSW tDATI DATA D0-D31 tDTKH DTACK tDTKS Fig. 83 - DPR / DMA Interface - Motorola Write Cycle (SYNC) DCCK tADDRI tADDRA tDSA A0-A23 SIZ0, SIZ1 R/W tDATA tASA tASDSI AS tASW tDSW DS tDATI D0-D31 DTACK DATA tDTKS tDTKH Fig. 84 - DPR / DMA Interface - Motorola Write Cycle (ASYNC) 99 MB86687A APPENDICES Edition 2.0 Parameter Signal g Abbrev Values Min Address Active delay Typical Max Units (ns) A2-A23 tADDRA 15 28 ns SIZ0/1 Active Delay - non burst SIZ0/1 tADDRA 13 22 ns SIZ0/1 Active Delay - burst SIZ0/1 tADDRA 15 24 ns A2-A23 tADDRI 5 Address SIZ0/1 Inactive Delay R/W Delay R/W ns 15 24 ns Read AS Active Delay AS tASDSA 11 17 ns Read DS Active Delay DS tASDSA 9 16 ns Read AS Inactive Delay - RMOD=0 AS tASDSI 10 17 ns Read DS Inactive Delay - RMOD=0 DS tASDSI 9 16 ns Read AS Inactive Delay - RMOD=1 AS 8 14 ns Setup Time of DTACK - ASYNC DTACK tDTKS 1 ns Setup Time of DTACK - SYNC DTACK tDTKS 2 ns Hold Time of DTACK - ASYNC DTACK tDTKH 2 ns Hold Time of DTACK - SYNC DTACK tDTKH 1 ns DS tDSW tDCCK - 1ns ns Setup Time of Data - RMOD=0 D0-D31 tDATS 0 ns Setup Time of Data - RMOD=1 D0-D31 6 ns Hold Time of Data - RMOD=0 D0-D31 10 ns Hold Time of Data - RMOD=1 D0-D31 7 ns Read DS Active Width tDATH Write AS Active Delay AS tASA 11 17 ns Write DS Active Delay DS tDSA 9 16 ns Write AS Inactive Delay AS tASDSI 10 17 ns Write DS Inactive Delay DS tASDSI 9 16 ns Write AS Active Width AS tASW tDCCK - 1ns ns DS tDSW 1/ t 2 DCCK - 1ns ns Write Data Active Delay D0-D31 tDATA 13 Write Data Inactive Delay D0-D31 tDATI 5 Write DS Active Width 22 ns ns Table 14 - DPR / DMA Interface - Motorola Cycle AC Timing 100 Edition 2.0 MB86687A APPENDICES Fig. 85 - Single Cycle Burst - Intel Extended Cycle (SBL=0, SYNC) Fig. 86 - Single Cycle Burst - Intel Extended Cycle (SBL=0, ASYNC) 101 MB86687A APPENDICES Parameter Edition 2.0 Signal g Abbrev Values Min Address Active Delay Write/Read Active Delay BE Active Delay Address BE Write/Read Inactive Delay Typical Max Units (ns) A23-2 tADDRA 15 28 ns W/R tADDRA 16 26 ns BE3-0 tADDRA 15 24 ns A23-2, tADDRI BE3-0 W/R 5 ns ADS Active Delay ADS tADSA 13 22 ns ADS Inactive Delay ADS tADSI 11 19 ns BLAST Active Delay BLAST tBLSTA 17 29 ns BLAST Inactive Delay BLAST tBLSTI 7 14 ns Setup Time of Data (Data Burst no parity) SRD31-0 tDATS 0 ns Hold Time of Data SRD31-0 tDATH 7 ns Write Active Delay1 SRD31-0 tDATA1 13 22 ns Write Active Delay2 SRD31-0 tDATA2 17 28 ns Write Inactive Delay SRD31-0 tDATI 5 ns Setup Time of SYNC READY READY tSRDYS 2 ns Hold Time of SYNC READY READY tSRDYH 1 ns Setup Time of ASYNC READY READY tARDYS 1 ns Hold Time of ASYNC READY READY tARDYH 2 ns Table 15 - Single Cycle Burst - Intel Extended Cycle Timing 102 Edition 2.0 MB86687A APPENDICES Fig. 87 - Single Cycle Burst - Motorola Extended Cycle (SBL=0, SYNC) Fig. 88 - Single Cycle Burst - Motorola Extended Cycle (SBL=0, ASYNC) 103 MB86687A APPENDICES Parameter Edition 2.0 Signal g Abbrev Values Min Address Active Delay Typical Max Units (ns) A23-2 tADDRA 15 28 ns R/W tADDRA 15 24 ns SIZ0, SIZ1 Active Delay SIZ0, SIZ1 tADDRA 15 24 ns Address BE Write/Read Inactive Delay A23-2, tADDRI SIZ0, SIZ1, W/R 5 R/W Active Delay ns TS Active Delay TS tTSA 13 22 ns TS Inactive Delay TS tTSI 11 19 ns TIP Active Delay TIP tTIPA 12 20 ns TIP Inactive Delay TIP tTIPI 10 18 ns Setup Time of Data (Data Burst no parity) SRD31-0 tDATS 0 ns Hold Time of Data SRD31-0 tDATH 7 ns Write Active Delay1 SRD31-0 tDATA1 13 22 ns Write Active Delay2 SRD31-0 tDATA2 17 28 ns Write Inactive Delay SRD31-0 tDATI 5 ns Setup Time of SYNC DTACK DTACK tSDTKS 2 ns Hold Time of SYNC DTACK DTACK tSDTKH 1 ns Setup Time of ASYNC DTACK DTACK tADTKS 1 ns Hold Time of ASYNC DTACK DTACK tADTKH 2 ns Table 16 - Single Cycle Burst - Motorola Extended Cycle Timing 104 Edition 2.0 D. MB86687A APPENDICES RATINGS D.1 Absolute Maximum Ratings Rating g Symbol y Units Values Min Max Positive Supply Voltage +VDD -0.5 6.0 V Input Voltage VDIN -0.5 +VDD + 0.5 V Output Voltage VO1 -0.5 +VDD + 0.5 V Input Current IMAX -10.0 125 Storage Temperature TSTG -40 125 oC NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this datasheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.2 DC Characteristics Parameter Symbol y Pin Test Condition Unit Value Min. Typ. Max. +4.75 +5.0 +5.25 V - - 100 mA Positive Supply Voltage VDD +4.75 Positive Supply Current +IVS Static no load Input High Voltage (TTL) VIH 2.2 - +VDD V Input Low Voltage (TTL) VIL 0 - 0.8 V IL 0<=VI<=+VDD -10 - 10 A Pull-up Input Leakage Current ILUL2 0<=VI<=+VDD -190 - -38 A Input Leakage Current ILZH1 0<=VI<=+VDD -10 - 10 A Output Low Voltage VOL IOL=3.2mA VSS - 0.4 V Output High Voltage VOH IOH=-2mA 4.2 - VDD V Output Off Leakage Current ILO -10 - 10 mA Input Pin Capacitance Cin - - 8 pF Output Pin Capacitance Cout - - 16 pF I/O Pin Capacitance Ci/o - - 21 pF Loading capacitance Cl 60 pF Operating Temperature TA +70 oC Power Dissipation (operating) PO Input Leakage Current 0 - 1000 mW 105 MB86687A APPENDICES E. JTAG E.1 JTAG Cells Edition 2.0 The Boundary Scan Register (BSR) consists of 123 registers, which form a serial shift register starting from pin 83, moving in a generally anti-clockwise direction around the chip to finish at pin 24. It should be noted that none of the internal D-types which form the BSR are reset, and hence are initially undefined. A valid pattern needs to be shifted into the register prior to any testing. However, while the JTAG TAP controller is reset, the I/O pins are connected through to the system logic. 106 I / O Pin Type: I = Input C = Clock input O = Output B = Bidirectional T = Tristate Iu = Input with pull-up resistor. BSR Cell Type: BSI 1 allows capture of device input pin and control of logic input pin. BSI 3 allows capture of device input pin only. BSO allows capture of logic output pin and control of device output pin ( = BSI1 ). BSOE allows control of tristate-able output pin (preset-able). BSDI allows control of bidirectional pin (= BSOE). BSBI allows capture and control of bidirectional input and output pin ( = BSI 1 + BSO ). Control Group No.: Denotes a JTAG BSR cell which controls a (group of) tristate-able output(s) or bidirectional pin(s). Controlled Group No.: Denotes a JTAG BSR cell which connects to a tristate-able output or bidirectional pin which is controlled by the JTAG BSR cell numbered in the previous column. Edition 2.0 1 2 3 4 5&6 7 8 9 10 11 12 & 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 & 30 31 & 32 33 & 34 35 & 36 37 & 38 39 & 40 41 & 42 43 & 44 45 & 46 47 & 48 49 & 50 51 & 52 53 & 54 55 & 56 57 & 58 59 & 60 MB86687A APPENDICES BSI1 BSOE BSO BSDI BSBI BSO BSOE BSO BSI1 BSDI BSBI BSI1 BSI1 BSI1 BSOE BSO BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSDI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI Iu 83 TXDRV 1 T 88 DS/BLAST/TIP 2 1 B T 93 94 MRD / AS/ ASD MWR / R/W R/W 3 T I 95 98 HOLD / BR HLDA / BG 4 B I I I 99 100 101 102 BGACK DTACK / READY RESET CS 5 T I I I I I I I I I 103 104 105 106 108 109 110 111 112 113 IRQ RD WR A1 A2 A3 A4 A5 A6 TEST 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 B B B B B B B B B B B B B B B B 115 116 117 118 121 122 123 125 126 127 128 133 134 135 136 138 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 1 2 3 4 5 6 107 MB86687A APPENDICES 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 108 BSI3 BSO BSI1 BSOE BSDI BSO BSI3 BSO BSO BSO BSO BSO BSO BSO BSO BSO BSI1 BSI3 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSI1 BSO BSI1 BSI1 BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO Edition 2.0 C O I 139 140 155 DCCK TOUT TIN T C T T T T T T T T O I C I I I I I I I I Iu T Iu Iu T T T T T T T T T T 143 144 145 146 148 149 150 151 152 153 156 157 158 159 160 161 162 163 166 168 169 167 55 56 57 89 90 91 92 87 197 199 202 203 204 TXSOC TXCLK TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 RXEN RXSOC RXCLK RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 TXFULL TXEN RXEMPTY CS / UT BE0 / SRA0 BE1 / SRA1 BE2 / SIZ0 BE3 / SIZ1 SRA2 SRA3 SRA4 SRA5 SRA6 SRA7 7 8 7 7 7 7 7 7 7 7 7 7 1 1 1 1 1 1 1 1 1 1 Edition 2.0 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 & 122 123 & 124 125 & 126 127 & 128 129 130 & 131 132 & 133 134 & 135 136 &137 138 & 139 140 & 141 142 & 143 144 & 145 146 & 147 148 & 149 150 & 151 MB86687A APPENDICES BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSO BSBI BSBI BSBI BSBI BSI1 BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 T T T T T T T T T T T T T T T T O O O O B B B B Iu B B B B B B B B B B B 8 9 11 12 13 37 39 40 41 59 62 63 64 66 67 68 44 45 46 47 29 31 32 33 35 170 172 173 175 178 179 181 185 187 190 192 SRA8 SRA9 SRA10 SRA11 SRA12 SRA13 SRA14 SRA15 SRA16 SRA17 SRA18 SRA19 SRA20 SRA21 SRA22 SRA23 TOCS TDCS ROCS RDCS PRTY0 PRTY1 PRTY2 PRTY3 SADRV SRD0 SRD1 SRD2 SRD3 SRD4 SRD5 SRD6 SRD7 SRD8 SRD9 SRD10 109 MB86687A APPENDICES 152 & 153 154 & 155 156 & 157 158 & 159 160 & 161 162 & 163 164 & 165 166 & 167 168 & 169 170 & 171 172 & 173 174 & 175 176 & 177 178 & 179 180 & 181 182 & 183 184 & 185 186 & 187 188 & 189 190 & 191 192 & 193 110 BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI BSBI Edition 2.0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 B B B B B B B B B B B B B B B B B B B B B 193 195 196 205 206 207 208 1 2 4 5 6 7 14 16 17 18 20 21 22 24 SRD11 SRD12 SRD13 SRD14 SRD15 SRD16 SRD17 SRD18 SRD19 SRD20 SRD21 SRD22 SRD23 SRD24 SRD25 SRD26 SRD27 SRD28 SRD29 SRD30 SRD31 C I I T 73 75 77 81 TCK TMS TDI TDO Edition 2.0 MB86687A APPENDICES PIN DESCRIPTION F.1 Physical Pin Diagram RXEN TIN VSS TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 VDD TXD1 TXD0 TXCLK TXSOC VSS N/C TOUT DCCK DATA15 N/C DATA14 DATA13 DATA12 DATA11 N/C VDD VSS N/C DATA10 DATA9 DATA8 DATA7 N/C DATA6 DATA5 DATA4 N/C VSS DATA3 DATA2 DATA1 DATA0 VDD TEST A6 A5 A4 A3 A2 VSS A1 WR F. 156 157 130 105 104 MB86687A 182 ALC 78 (TOP VIEW) 208 1 53 26 RD IRQ CS RESET DTACK/READY/BERR BGACK HLDA/BG VDD VSS HOLD/BR MWR / R/W / R/W MRD/AS/ADS/TS BE3/SIZ1 BE2/SIZ0 BE1/SRA1 BE0/SRA0 DS/ TIP/ BLAST SRA2 N/C VSS N/C TXDRV N/C TDO N/C VDD N/C TDI N/C TMS N/C TCK VSS N/C RESERVED N/C SRA23 SRA22 SRA21 N/C SRA20 SRA19 SRA18 VDD VSS SRA17 N/C CS/UT RXEMPTY TXEN N/C N/C 52 SRD18 SRD19 VSS SRD20 SRD21 SRD22 SRD23 SRA8 SRA9 VDD SRA10 SRA11 SRA12 SRD24 VSS SRD25 SRD26 SRD27 N/C SRD28 SRD29 SRD30 N/C SRD31 N/C VSS VDD N/C PRTY0 N/C PRTY1 PRTY2 PRTY3 N/C SADRV N/C SRA13 VSS SRA14 SRA15 SRA16 N/C VDD TOCS TDCS ROCS RDCS N/C N/C VSS N/C N/C RXSOC RXCLK RXD0 RXD1 RXD2 RXD3 RXD4 VSS VDD RXD5 TXFULL RXD6 RXD7 SRD0 N/C SRD1 SRD2 N/C SRD3 VSS N/C SRD4 SRD5 N/C SRD6 N/C VDD N/C SRD7 N/C SRD8 N/C VSS SRD9 N/C SRD10 SRD11 N/C SRD12 SRD13 SRA3 N/C SRA4 VSS VDD SRA5 SRA6 SRA7 SRD14 SRD15 SRD16 SRD17 Fig. 89 - ALC Pin Assignment 111 MB86687A APPENDICES F.2 Edition 2.0 Pin Description Table Pin No. Pin Name Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SRD18 SRD19 VSS SRD20 SRD21 SRD22 SRD23 SRA8 SRA9 VDD SRA10 SRA11 SRA12 SRD24 VSS SRD25 SRD26 SRD27 N/C SRD28 SRD29 SRD30 N/C SRD31 N/C VSS VDD N/C PRTY0 N/C PRTY1 PRTY2 PRTY3 N/C SADRV N/C SRA13 VSS SRA14 SRA15 I/O I/O - I/O I/O I/O I/O O (3-state) O (3-state) - O (3-state) O (3-state) O (3-state) I/O - I/O I/O I/O - I/O I/O I/O - I/O - - - - I/O - I/O I/O I/O - I - O (3-state) - O (3-state) O (3-state) Function SAR Memory data bus bit 18 SAR Memory data bus bit 19 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII SAR Memory data bus bit 20 SAR Memory data bus bit 21 SAR Memory data bus bit 22 SAR Memory data bus bit 23 SAR Memory address bit 8 SAR Memory address bit 9 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII SAR Memory address bit 10 SAR Memory address bit 11 SAR Memory address bit 12 SAR Memory data bus bit 24 SAR Memory data bus bit 25 SAR Memory data bus bit 26 SAR Memory data bus bit 27 Not Connected SAR Memory data bus bit 28 SAR Memory data bus bit 29 SAR Memory data bus bit 30 Not Connected SAR Memory data bus bit 31 Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected Parity for SRD7 - SRD0 Not Connected Parity for SRD15 - SRD8 Parity for SRD23 - SRD16 Parity for SRD31 - SRD24 Not Connected SAR Memory constant drive Not Connected SAR Memory address bit 13 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII 112 SAR Memory address bit 14 SAR Memory address bit 15 Edition 2.0 MB86687A APPENDICES Pin No. Pin Name Type 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SRA16 N/C VDD TOCS TDCS ROCS RDCS N/C N/C VSS N/C N/C N/C N/C TXEN RXEMPTY CS/UT N/C SRA17 VSS VDD SRA18 SRA19 SRA20 N/C SRA21 SRA22 SRA23 N/C N/C N/C VSS TCK N/C TMS N/C TDI N/C VDD N/C O (3-state) - - O O O O - - - - - - - O (high-Z) I I - O (3-state) - - O (3-state) O (3-state) O (3-state) - O (3-state) O (3-state) O (3-state) - - - - I - I - I - - - Function SAR Memory address bit 16 Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Transmit Overhead Start of Cycle Transmit Data Start of Cycle Receive Overhead Start of Cycle Receive Data Start of Cycle Not Connected Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected Not Connected Not Connected Not Connected UTOPIA Transmit Enable UTOPIA Receive Empty Fujitsu Cell Stream / UTOPIA Select Not Connected SAR Memory address bit 53 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII SAR Memory address bit 18 SAR Memory address bit 19 SAR Memory address bit 20 Not Connected SAR Memory address bit 21 SAR Memory address bit 22 SAR Memory address bit 23 Not Connected Reserved Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII JTAG Port Clock Not Connected JTAG Test Mode Select Not Connected JTAG Data Input Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected 113 MB86687A APPENDICES Edition 2.0 Pin No. Pin Name Type 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 TDO N/C TXDRV N/C VSS N/C SRA2 DS / BLAST / TIP BE0 BE1 BE2 BE3 MRD/AS/ ADS / TS MWR/ R/W/ R/W HOLD/BR VSS VDD HLDA/BG BGACK DTACK/READY/BERR RESET CS IRQ RD WR A1 VSS A2 A3 A4 A5 A6 TEST VDD DATA0 DATA1 DATA2 DATA3 VSS N/C O - I - - - O (high-Z) O (3-state) O (3-state) O (3-state) O (3-state) O (3-state) I/O O (3-state) O (high-Z) - - I O (high-Z) I I I O (high-Z) I I I - I I I I I I - I/O I/O I/O I/O - - Function JTAG Data Output Not Connected Cell Stream Constant Drive Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected SAR Memory data bus bit 62 Data Strobe / Burst Last / Transfer in Progress SAR Memory BE0/SRA0 SAR Memory BE1/SRA1 SAR Memory BE2/SIZ0 SAR Memory BE3/SIZ1 SAR Memory MRD/AS/ADS / TS SAR Memory MWR/R/W / R/W SAR Memory HOLD/BR IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII SAR Memory HLDA/BG SAR Memory BGACK SAR Memory DTACK/READY or Bus Error ALC Master Reset input p Chip Select Interrupt Request p Read p Write Microprocessor Address bit 1 Microprocessor Address bit 2 Microprocessor Address bit 3 Microprocessor Address bit 4 Microprocessor Address bit 5 Microprocessor Address bit 6 Test Input - connect to Vss Microprocessor Data Bus bit 0 Microprocessor Data Bus bit 1 Microprocessor Data Bus bit 2 Microprocessor Data Bus bit 3 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII 114 Not Connected Edition 2.0 MB86687A APPENDICES Pin No. Pin Name Type 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 DATA4 DATA5 DATA6 N/C DATA7 DATA8 DATA9 DATA10 N/C VSS VDD N/C DATA11 DATA12 DATA13 DATA14 N/C DATA15 DCCK TOUT N/C VSS TXSOC TXCLK TXD0 TXD1 VDD TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 VSS TIN RXEN RXSOC RXCLK RXD0 RXD1 I/O I/O I/O - I/O I/O I/O I/O - - - - I/O I/O I/O I/O - I/O I O - - O (3-state) I O (3-state) O (3-state) - O (3-state) O (3-state) O (3-state) O (3-state) O (3-state) O (3-state) - - O I I I I Function Microprocessor Data Bus bit 4 Microprocessor Data Bus bit 5 Microprocessor Data Bus bit 6 Not Connected Microprocessor Data Bus bit 7 Microprocessor Data Bus bit 8 Microprocessor Data Bus bit 9 Microprocessor Data Bus bit 10 Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected Microprocessor Data Bus bit 11 Microprocessor Data Bus bit 12 Microprocessor Data Bus bit 13 Microprocessor Data Bus bit 14 Not Connected Microprocessor Data Bus bit 15 DMA Cycle Clock input Token Out output Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Cell Stream Interface Transmit Sync Cell Stream Interface Transmit Cell Stream Interface Transmit data bit 0 Cell Stream Interface Transmit data bit 1 Cell Stream Interface Transmit data bit 2 Cell Stream Interface Transmit data bit 3 Cell Stream Interface Transmit data bit 4 Cell Stream Interface Transmit data bit 5 Cell Stream Interface Transmit data bit 6 Cell Stream Interface Transmit data bit 7 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Token In input Indicates ALC receive buffers full Cell Stream Interface Receive Sync Cell Stream Interface Receive Cell Stream Interface Receive data bit 0 Cell Stream Interface Receive data bit 1 115 MB86687A APPENDICES Edition 2.0 Pin No. Pin Name Type 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 RXD2 RXD3 RXD4 VSS VDD RXD5 TXFULL RXD6 RXD7 SRD0 N/C SRD1 SRD2 N/C SRD3 VSS N/C SRD4 SRD5 N/C SRD6 N/C VDD N/C SRD7 N/C SRD8 N/C VSS SRD9 N/C SRD10 SRD11 N/C SRD12 SRD13 SRA3 N/C SRA4 VSS VDD SRA5 SRA6 SRA7 SRD14 SRD15 SRD16 SRD17 I I I - - I I I I I/O - I/O I/O - I/O - - I/O I/O - I/O - - - I/O - I/O - - I/O - I/O I/O - I/O I/O O (3-state) - O (3-state) - - O (3-state) O (3-state) O (3-state) I/O I/O I/O I/O Function Cell Stream Interface Receive data bit 2 Cell Stream Interface Receive data bit 3 Cell Stream Interface Receive data bit 4 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Cell Stream Interface Receive data bit 5 UTOPIA Transmit Full Cell Stream Interface Receive data bit 6 Cell Stream Interface Receive data bit 7 SAR Memory data bus bit 0 Not Connected SAR Memory data bus bit 1 SAR Memory data bus bit 2 Not Connected SAR Memory data bus bit 3 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected SAR Memory data bus bit 4 SAR Memory data bus bit 5 Not Connected SAR Memory data bus bit 6 Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII Not Connected SAR Memory data bus bit 7 Not Connected SAR Memory data bus bit 8 Not Connected IIIII IIIIIIII IIII IIIIIIIIIIIIIIII SAR Memory data bus bit 9 Not Connected SAR Memory data bus bit 10 SAR Memory data bus bit 11 Not Connected SAR Memory data bus bit 12 SAR Memory data bus bit 13 SAR Memory address bit 3 Not Connected SAR Memory address bit 4 IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII IIIII IIIIIIII IIII IIIIIIIIIIIIIIII 116 SAR Memory address bit 5 SAR Memory address bit 6 SAR Memory address bit 7 SAR Memory data bus bit 14 SAR Memory data bus bit 15 SAR Memory data bus bit 16 SAR Memory data bus bit 17 Edition 2.0 G. MB86687A APPENDICES PACKAGE DIMENSIONS FPT-208P-M01 208-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-208P-M01) 1.205 .008 SQ (30.60 0.20) 1.102 .004 SQ (28.00 0.10) 156 157 .152 (3.85) MAX (MOUNTING HEIGHT) 0 (0) MIN (STAND OFF HEIGHT) 105 104 1.165 (29.60) NOM 1.004 (25.50) REF INDEX "A" 53 208 1 LEAD No. .0197 (0.50) TYP .008 .004 (0.20 0.10) 52 .003 (0.08) "B" .004 (0.10) M .006 .002 (0.15 0.05) Details of "A" part .010 (0.25) .008 (0.20) .006 (0.15) MAX .016 (0.40) MAX 1992 FUJITSU LIMITED F208001S-3C Details of "B" part 0 to 10 .020 .008 (0.50 0.20) Dimensions in inches (millimeters) All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical applications. Complete information sufficient for construction purposes is not necessarily given. This information contained in this document does not convey any license under copyrights, patent rights, software rights or trademarks claimed by Fujitsu. The information contained in this document has been carefully checked and believed to be reliable. However Fujitsu assumes no responsibility for inaccuracies. Fujitsu reserves the right to change the product specifications without notice. No part of this publication may be copied or reproduced in any form without the prior written consent of Fujitsu. 117 Microelectronics Worldwide Headquarters Japan Tel: ++81 44 754 3753 Fax: ++81 44 754 3332 Fujitsu Limited Asia 1015 Kamiodanaka Nakahara-ku Kawasaki 211 Japan Fujitsu Microelectronics Asia PTE Limited Tel: ++65-336 1600 Fax: ++65-336 1609 http://www.fujitsu.co.jp/ http://www.fsl.com.sg/ U.S.A Tel: ++1 408 922 9000 Fax: ++1 408 922 9179 No. 51 Bras Basah Road Plaza by the Park #06-04/07 Singapore 0718 Fujitsu Microelectronics Inc. 3545 North First Street San Jose CA 95134-1804 USA Tel: ++1 800 866 8608 Customer Response Center Fax: ++1 408 922 9179 Mon-Fri: 7am-5pm Europe Tel: +49 (0) 6103 6900 Fujitsu Mikroelektronik GmbH Fax:+49 (0) 6103 690122 Am Siebenstein 6-10 (PST) D-63303 Dreieich-Buchschlag Germany http://www.fujitsumicro.com/ http://www.fujitsu.ede.com/ ATM-DS-20357-8/96