MB86687A - Fujitsu - Datasheet.Live

Adaptation Layer Controller

The FUJITSU MB86687A is an ATM protocol controller

which autonomously terminates ATM Adaptation Layer

standards Type 3/4 and Type 5. The device is ideally suited

to applications in a variety of customer premises equipment

such as ATM workstation Adaptor Cards and ATM Hubs.

The device supports simultaneous segmentation and

reassembly on up to 1024 virtual circuits (VCs).

FEATURES

Supports Broadband ISDN Adaptation Layer standards T ype

3/4 and Type 5.

Supports simultaneous segmentation and reassembly on up

to 1024 VCs.

Supports up to 12 peak segmentation rates with leaky bucket

averaging on a per VC basis with optional bucket fill before

segmentation continues.

Programmable peak and average rates and leaky bucket

averaging on total ALC cell stream output.

Support for scatter / gather mode.

Transparent ATM cell and cell payload modes including

support for OAM and Resource Management cells.

UTOPIA Level 1 v2.01 functionally compatible cell stream

interface with optional HEC checking on receive.

Flexible routing tag append / remove mode for direct ATM

Switch connection.

Supports buffer chaining and buffer streaming.

Supports buffer ageing time-out.

Separate 32 bit data and 16 bit control ports with optimized

DMA interface including 128 circuit cache to reduce DMA bus

occupancy.

Supports JTAG to IEEE1149.1

Fabricated in sub–micron CMOS technology with CMOS/TTL

compatible I/O and single +5V power supply.

This device contains circuitry to protect the inputs

against damage due to high static voltages or

electric fields. However, it is advised that normal

precautions be taken to avoid application of any

voltage higher than maximum rated voltages to

this high impedance circuit.

PLASTIC PACKAGE

SQFP208

PIN ASSIGNMENT

156

157

208 52

104

105

INDEX

Adaptation Layer Controller (ALC)

DATA SHEET

Edition 2.0

April 1996

MB86687A



1996 BY FUJITSU LIMITED

TABLE OF CONTENTS

MB86687A Edition 2.0

CONTENTS

1. OVERVIEW 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2. EXTERNAL INTERFACES 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Logical Outline 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Detailed Description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3. FUNCTIONAL DESCRIPTION 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 DMA Controller and SAR Memory Interface 9. . . . . . . . . . .

3.2 Traffic Management Controller 15. . . . . . . . . . . . . . . . . . . . . .

3.3 Segmentation and Convergence Sub-layer Controller 17.

3.4 Reassembly and Convergence Sub-layer Controller 21. .

3.5 Cell Stream Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Microprocessor Interface 26. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Segmentation and Reassembly Memory Interface 27. . . . .

4. DEVELOPERS NOTES 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Configuration Control Issues 33. . . . . . . . . . . . . . . . . . . . . . . .

4.2 Transmit Data Structures 33. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Receive Data Structures 45. . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPENDICES

A. REGISTER TABLE 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B. REGISTER MAPS 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C. RA TINGS 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.1 Absolute Maximum Ratings 83. . . . . . . . . . . . . . . . . . . . . . . . .

C.2 DC Characteristics 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D. AC TIMINGS 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E. JT AG 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E.1 JTAG Cells 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F. PIN DESCRIPTION 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.1 Physical Pin Diagram 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.2 Pin Description Table 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G. PACKAGE DIMENSIONS 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TABLE OF CONTENTS MB86687AEdition 2.0

TABLES

Table 1 – Pull Values 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2 – Single Buffer, Chaining and Streaming Modes 13. . . . . . . . . . . . . . . . . . . . .

Table 3 – JTAG Interface Timing 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4 – Miscellaneous – AC Timing Parameters 84. . . . . . . . . . . . . . . . . . . . . . . . . .

Table 5 – Cell Stream Interface clocks – AC Timing Parameters 85. . . . . . . . . . . . . .

Table 6 – Cell Stream Interface Fujitsu Mode – AC Timing Parameters 86. . . . . . . .

Table 7 – Cell Stream Interface UTOPIA Mode – AC Timing Parameters 87. . . . . . .

Table 8 – Cell Stream Interface Token Passing – AC Timing Parameters 88. . . . . . .

Table 9 – Microprocessor Interface – AC Timing 90. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 10 – Microprocessor Interface – AC Timing 91. . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 11 – Microprocessor Interface – Intel DMA Access AC Timing 93. . . . . . . . . .

Table 12 – Microprocessor Interface – Motorola DMA Access AC Timing 95. . . . . .

Table 13 – DPR / DMA Interface – Intel Cycle AC Timing 98. . . . . . . . . . . . . . . . . . . .

Table 14 – DPR / DMA Interface – Motorola Cycle AC Timing 101. . . . . . . . . . . . . . . .

Table 15 – Single Cycle Burst – Intel Extended Cycle Timing 103. . . . . . . . . . . . . . . . .

Table 16 – Single Cycle Burst – Motorola Extended Cycle Timing 105. . . . . . . . . . . . .

FIGURES

Fig. 1 – Possible System Configurations 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 2 – ALC External Interfaces 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 3 – ALC Block Diagram 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 4 – Shared Data Structures 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 5 – Transmit Queue Structure 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 6 – ATM Protocol Data Units (a) AAL3/4 (b) AAL5 17. . . . . . . . . . . . . . . . . . . . . .

Fig. 7 – Convergence Sub-layer Protocol Data Units 18. . . . . . . . . . . . . . . . . . . . . . . .

Fig. 8 – Cell Stream Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 9 – Cell Stream Receive Interface Timing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 10 – UTOPIA Transmit Interface Timing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 11 – UTOPIA Receive Interface Timing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 12 – CSI Token In/Out Timing 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 13 – Motorola 32 Bit Mode – Normal Mode Read Timing 28. . . . . . . . . . . . . . . . .

Fig. 14 – Intel 32 Bit Mode – Normal Mode Extended Read Timing 28. . . . . . . . . . . .

Fig. 15 – Intel 486 Mode – Normal Reads Timing 29. . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 16 – Intel 486 Mode Single Cycle Burst Timing 29. . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 17 – Start of Cycle Signal Timing – Fast Mode Extended Read 30. . . . . . . . . . .

Fig. 18 – Transmit Data Structures 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 19 – Transmit Data Structures – Address Calculation 35. . . . . . . . . . . . . . . . . . .

Fig. 20 – Transmit Descriptor 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 21 – Circuit Reference Table Entry 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TABLE OF CONTENTS

MB86687A Edition 2.0

iii

FIGURES (CONTINUED)

Fig. 22 – ALC Queue Structures 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 23 – Transmit Pending Queue Format 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 24 – Transmit Buffer Release Queue Format 44. . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 25 – Receive Data Structures 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 26 – Receive Data Structures – Address Calculation 47. . . . . . . . . . . . . . . . . . . .

Fig. 27 – Receive Descriptor 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 28 – Buffer Free Queue Format 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 29 – Receive Buffer Ready Queue Format 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 30 – ALC REGISTER MAP (1 of 3) 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 31 – ALC REGISTER MAP (2 of 3) 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 32 – ALC REGISTER MAP (3 of 3) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 33 – REGISTERS 0, 1 AND 2 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 34 – REGISTER 3, 4 AND 5 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 35 – REGISTER 6, 7 AND 8 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 36 – REGISTERS 9 and 10 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 37 – REGISTER 13 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 38 – REGISTER 14 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 39 – REGISTER 15 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 40 – REGISTER 15 contd. 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 41 – REGISTER 16 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 42 – REGISTER 16 contd. 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 43 – REGISTER 17 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 44 – REGISTER 17 (continued) 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 45 – REGISTER 18 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 46 – REGISTER 18 (continued) and 19 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 47 – REGISTERS 20 to 31 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 48 – REGISTER 32 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 49 – REGISTER 33 AND 34 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 50 – REGISTER 35 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 51 – REGISTERS 40 and 41 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 52 – REGISTER 42, 43 AND 44 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 53 – REGISTER 45, 46 AND 47 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 54 – REGISTER 48, 49 AND 50 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 55 – REGISTERS 51 AND 52 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 56 – REGISTER 53 AND 54 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 57 – REGISTER 55 AND 56 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 58 – REGISTER 57 AND 58 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 59 – REGISTER 59 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 60 – System Clock Timing 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TABLE OF CONTENTS MB86687AEdition 2.0

FIGURES (CONTINUED)

Fig. 61 – Reset Timing 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 62 – Cell Stream Clock Timing 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 63 – Cell Stream Interface Transmit Port (Fujitsu Mode) Timing 86. . . . . . . . . .

Fig. 64 – Cell Stream Interface Receive Port (Fujitsu Mode) Timing 86. . . . . . . . . .

Fig. 65 – Cell Stream Interface Transmit Port (Utopia mode) Timing 87. . . . . . . . . . .

Fig. 66 – Cell Stream Interface Receive Port (Utopia mode) Timing 87. . . . . . . . . . .

Fig. 67 – CSI Token Transmit and Receive Timing 88. . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 68 – Microprocessor Interface – Read Timing 89. . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 69 – Microprocessor Interface – Write Timing 89. . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 70 – Microprocessor Interface – Write to Write Timing 91. . . . . . . . . . . . . . . . . . .

Fig. 71 – Microprocessor Interface – Interrupt Timing 91. . . . . . . . . . . . . . . . . . . . . . .

Fig. 72 – Microprocessor Interface – Intel DMA Access Timing (SYNC) 92. . . . . . . .

Fig. 73 – Microprocessor Interface – Intel DMA Access Timing (ASYNC) 92. . . . . .

Fig. 74 – Microprocessor Interface – Intel DMA Access Control Override Timing 93

Fig. 75 – Microprocessor Interface – Motorola DMA Access Timing (SYNC) 94. . . .

Fig. 76 – Microprocessor Interface – Motorola DMA Access Timing (ASYNC) 94. .

Fig. 77 – DPR / DMA Interface – Intel Read Cycle (SYNC) 96. . . . . . . . . . . . . . . . . . .

Fig. 78 – DPR / DMA Interface – Intel Read Cycle (ASYNC) 96. . . . . . . . . . . . . . . . .

Fig. 79 – DPR / DMA Interface – Intel Write Cycle (SYNC) 97. . . . . . . . . . . . . . . . . . .

Fig. 80 – DPR / DMA Interface – Intel Write Cycle (ASYNC) 97. . . . . . . . . . . . . . . . .

Fig. 81 – DPR / DMA Interface – Motorola Read Cycle (SYNC) 99. . . . . . . . . . . . . . .

Fig. 82 – DPR / DMA Interface – Motorola Read Cycle (ASYNC) 99. . . . . . . . . . . . .

Fig. 83 – DPR / DMA Interface – Motorola Write Cycle (SYNC) 100. . . . . . . . . . . . . . .

Fig. 84 – DPR / DMA Interface – Motorola Write Cycle (ASYNC) 100. . . . . . . . . . . . .

Fig. 85 – Single Cycle Burst – Intel Extended Cycle (SBL=0, SYNC) 102. . . . . . . . . .

Fig. 86 – Single Cycle Burst – Intel Extended Cycle (SBL=0, ASYNC) 102. . . . . . . . .

Fig. 87 – Single Cycle Burst – Motorola Extended Cycle (SBL=0, SYNC) 104. . . . . .

Fig. 88 – Single Cycle Burst – Motorola Extended Cycle (SBL=0, ASYNC) 104. . . . .

Fig. 89 – ALC Pin Assignment 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Edition 2.0 MB86687A

1. OVERVIEW

The ALC simultaneously supports

autonomous segmentation and

reassembly of user data packets on up to

1024 virtual circuits (VCs).

User data packets are transferred to and

from shared data structure memory

using a high speed intelligent DMA

controller with a 32 bit data bus.

Shared data structures are stored in SAR

(Segmentation and Reassembly)

memory which can be either dual port

memory or a partition of system memory .

Packets for segmentation and packets

being reassembled are stored in the SAR

memory together with external data

structures. These are accessed using the

ALC’s high speed intelligent DMA

controller. In non-demanding

applications, system memory can be

used as SAR memory. When dual port

memory is used the ALC’s DMA

controller has full access to the SAR

memory bus. When system memory is

used the DMA controller will negotiate

access to a portion of the system bus

bandwidth. The ALC provides the user

with the facility to partition the shared

data structures into dual port memory

and user data into shared memory.

The DMA controller supports

autonomous traffic shaping functions.

Up to twelve different peak rate queues

can be configured for packet

segmentation. In addition each VC can

be assigned to either 100%, 50% or 25%

of the nominal peak rate.

In this way the user can select from one of

36 possible peak rates. Average rate

management is in accordance with either

the single or double leaky bucket

averaging algorithms.

Fig. 1 shows three possible system

configurations.

Adaptation Layer Support

The ALC autonomously terminates the

protocols involved in segmenting and

reassembling data streams conforming

to Adaptation Layer Types 3/4 and 5. AAL

3/4 and AAL 5 traffic can be handled

simultaneously . Streaming and Message

Modes as defined for AAL 3/4 and AAL5

are supported.

In Message Mode, the Convergence

Sublayer payload (Service Data Unit) is

considered to be the user data

transmitted from or received into a single

entity. A single entity being regarded as

one user data buffer or linked chain of

user data buffers.

In Streaming Mode, the Convergence

Sublayer payload is considered to be the

user data transmitted from or received

into multiple entities separated in time.

This allows a partial segmentation or

reassembly. In Streaming Mode the

chaining of buffers is not supported.

The ALC Device supports two

transparent modes. In transparent

payload mode the 48 byte ATM cell

payload is received or transmitted

transparently into or from SAR Memory.

In transparent cell mode the ATM cell is

received or transmitted transparently into

or from SAR Memory.

Edition 2.0MB86687A

System Configurations

In adaptor card applications, the ALC

interfaces to the Fujitsu MB86683

Network Termination Controller Device

(NTC) (or compatible CCITT I.432

device) via a full duplex 8-bit wide

UTOPIA compliant cell stream interface

for connection to the transmission

medium.

In Hub or Router applications, the ALC

connects directly to the Fujitsu MB86680

Self-routing Switch Element (SRE) for

autonomous routing. In this case a

programmable Tag of 3 bytes must be

appended to each cell.

Alternatively, it may be connected to a

proprietary backplane architecture. To

support this application the ALC can be

configured to transmit and receive ATM

cells with a four byte header minus the

HEC field.

Fig. 1 – Possible System Configurations

Host

CPU

Host

CPU

SAR

Memory

System

Memory

ALC

ALC NTC

SRE

NTC

SRE

Host

CPU

System

Memory ALC NTC

SRE

SAR

Memory

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Edition 2.0 MB86687A

2. EXTERNAL INTERFACES

2.1 Logical Outline

A logical view of the ALC’s external pins is illustrated in Fig. 2, and a physical pin

assignment is shown in Appendix F.

SRD0–SRD31

SRA2–SRA23

ALC

D0–D15

TXD0–TXD7

TXSOC

TXCLK

RXD0–RXD7

RXSOC

RXCLK

DCCK

TIN

TOUT

IRQ RD WR

BGACK

DTACK / READY / BERR

HOLD / BR

HLDA / BG

MRD / AS / ADS / TS

MWR / R/W / R/W

DS / BLAST / TIP

RXEN

RESET

Fig. 2 – ALC External Interfaces

CSA1–A6

SAR

Memory

Interface

Cell

Stream

Interface

Microprocessor

Interface

TXEN

TDI TCKTDO TMS

JTAG Test Port

TOCS

TDCS

ROCS

RDCS

TXDRV

SADRV

BE0 / A0

BE1 / A1

BE2 / SIZ0

BE3 / SIZ1

TXFULL

RXEMPTY

PRTY0–PRTY3

Edition 2.0MB86687A

2.2 Detailed Description

2.2.1 SAR Memory Interface

This interface provides the ALC DMA

controller with access to external dual

port memory or shared access to system

memory.

The interface comprises the following

signals:

SRD0 – SRD31

Bi–directional SAR memory data bus.

PRTY0 – PRTY3

Bi–directional SAR memory data bus

parity protection.

SRA2 – SRA23

Most significant 22 bits of the SAR

memory address bus. All bits are tri-state

outputs.

SADRV

This input allows the SAR memory

interface to be permanently driven.

BE0 / SRA0

Multifunction tri-state output. Functions

are as follows:

Intel mode: BE0

Byte Enable 0

Enables data byte on SRD0 – SRD7,

Motorola mode: SRA0

SAR Memory Address bus bit 0.

BE1 / SRA1

Multifunction tri-state output. Functions

are as follows:

Intel mode: BE1

Byte Enable 1

Enables data byte on SRD8 – SRD15.

Motorola mode: SRA1

SAR Memory Address bus bit 1.

BE2 / SIZ0

Multifunction tri-state output. Functions

are as follows:

Intel mode: BE2

Byte Enable 2

Enables data byte on

SRD16 – SRD23.

Motorola mode: SIZ0.

BE3 / SIZ1

Multifunction tri-state output. Functions

are as follows:

Intel mode:

BE3: Byte Enable 3

Enables data byte on

SRD24 – SRD31,

Motorola mode: SIZ1.

The coding of the SIZ signals has the

following meaning:

SIZ1 SIZ0 Meaning

0 1 Burst of 8

1 0 Word

1 1 Burst of 4

0 0 Long Word

MRD / AS / ADS / TS

Bi-function tri-state bi-directional signal.

SAR memory read signal (Intel mode),

SAR memory address strobe (Motorola

mode). This signal is used as an input

during Motorola mode bus arbitration

and is the ADS signal in extended modes.

In extended modes for Intel, it is ADS and

Motorola (TS).

Edition 2.0 MB86687A

MWR / R/W/ R/W

Multifunction tri-state output. SAR

Memory write signal (Intel mode), SAR

Memory read/write signal (Motorola

modes) and read/write (Intel Extended

mode).

DS / BLAST / TIP

Multifunction tri-state output. Data Strobe

in Motorola mode; BLAST (last in burst) in

Intel extended mode; TIP (transmission

in progress) in extended Motorola mode.

TOCS

Transmit Overhead Cycle Start output.

This is asserted before any transmit cycle

that is not a data cycle.

TDCS

T ransmit Data Cycle Start output. This is

asserted before a transmit data cycle.

ROCS

Receive Overhead Cycle Start output.

This is asserted before any receive cycle

that is not a data cycle.

RDCS

Receive Data Cycle Start output. This is

asserted before a receive data cycle.

HOLD / BR

Tri-state Hold/Bus request output used to

request bus access for ALC DMA

controller.

HLDA / BG

Hold/Bus Grant input used to pass

control of the bus to the ALC DMA

controller.

BGACK

Bus Grant Acknowledge output indicates

ALC DMA controller is assuming control

of the bus.

READY / DTACK / BERR

Ready/Data Transfer Acknowledge

input. In standard mode used to

terminate DMA / DPR cycles. In FAST

mode used to generate an ALC interrupt

indicating memory access conflict (Bus

error).

DCCK, DMA CYCLE CLOCK

Clock input used to drive the ALC DMA

cycles.

2.2.2 Microprocessor Interface

The microprocessor interface comprises

the following signals:

A1–A6

Microprocessor address bus inputs.

DATA0–DATA15

Bi-directional microprocessor data bus

signals DATA 0–15.

Microprocessor bus chip select input.

Microprocessor bus read input.

Microprocessor bus write input.

IRQ

Interrupt request output.

RESET

ALC master reset input.

Edition 2.0MB86687A

2.2.3 Cell Stream Interface

This interface comprises the following

signals:

TXD0–TXD7

These tri–state output signals provide 8

bit parallel transmit data which is cell

aligned and asynchronous. To enable

daisy chaining of ALCs these signals are

tri-state.

TXSOC

Transmit start of cell sync output. This tri

–state output indicates that the first byte

of an ATM cell or routing tag is available

on the TXD0 – TXD7 data lines. The

frequency of this signal depends on the

cell transmission rate from the ALC. To

enable daisy chaining this pin is tri-state.

TXCLK

This input signal is used to clock transmit

data out of the ALC. The signal can be of

arbitrary frequency but should be

sufficient to support the bandwidth

specified by the ALC traffic shaping

parameters. No phase relationship is

assumed with RXCLK.

TXEN

This tri–state output signal is asserted in

UTOPIA mode when the cell stream

transmit is outputting valid data.

TXFULL

This input is used in UTOPIA mode to halt

the ALC transmit cell stream data.

RXD0–RXD7

These 8 input pins provide the ALC with 8

bit parallel, cell aligned receive data.

RXSOC

Receive start of cell sync input. This

signal indicates when the first byte of an

ATM cell or routing tag is available on the

RXD0 – RXD 7 pins.

RXCLK

This input signal is used to clock received

data into the ALC. No phase relationship

is assumed with TXCLK.

RXEN

This output signal is used in UTOPIA

mode to control the flow of receive cells

when using an external FIFO. The signal

indicates that the ALC receive buffers are

full.

RXEMPTY

This input signal is used to control the

flow of receive cells when using an

external FIFO. The signal indicates that

the FIFO is empty.

TOUT

Token out output. This signal is used to

enable daisy chaining. The ALC

transmits a ‘token’ pulse on the falling

edge of TXCLK to indicate that it has

completed a cell transfer or has no data

to transmit. The output is held low during

cell transmission.

TIN

Token In input. This input should be wired

to the TOUT output of other ALC devices

to form a daisy chain. If unused this pin

should be pulled high.

TXDRV

This input allows the ALC to permanently

drive the transmit cell stream interface

Edition 2.0 MB86687A

2.2.4 JTAG Test Port

TCK

JTAG test clock input

TMS

JTAG test mode input

TDI

JTAG test data input

TDO

JTAG test data output

SIGNAL PULL VALUE COMMENT

The following are essential for correct operation

BGACK High 2K7 DMA mode

High 10K Dual Port Memory mode

IRQ High 2K7

TXSOC Low 10K Only when TXDRV is not asserted

TXEN High 10K Only when TXDRV is not asserted

HOLD/BR Low 2K7 Only in Intel DMA mode

High 2K7 Only in Motorola DMA mode

MRD/AS High 10K DMA mode *

High 100K Dual Port Memory mode

HLDA/BG High 10K

DS High 100K

The following are not essential, but are advisable

TXD0–7 High/Low 100K Only when TXDRV is not asserted

SRD0–31 High 100K Only when SADRV is not asserted

The following can be omitted if the data bus can be guaranteed not to float

between 2.2v and 0.8v.

MWR/R/W High 100K *

BE0/A0 High 100K *

BE1/A1 High 100K *

BE2/SIZ0 High 100K *

BE3/SIZ1 High 100K *

A2–21 High 100K *

Note: * – These signals are continuously driven when Dual Port Ram mode is selected

or SADRV is asserted.

Table 1 – Pull Values

Edition 2.0MB86687A

3. FUNCTIONAL DESCRIPTION

This section describes the behaviour of

each major functional block within the

ALC, as illustrated in Fig. 3. The

descriptions in this section are from a

user’s perspective and are intended to

give a detailed description of device

functionality and modes of operation.

The ALC comprises the following major

components:

High Speed DMA Controller,

Traffic Management Controller,

Transmit and Receive Buffers,

Segmentation and Convergence

Sub-layer Controller,

Reassembly and Convergence

Sub-layer Controller,

Cell Stream Interface,

Microprocessor Interface,

Segmentation and Reassembly

Memory Interface.

Fig. 3 – ALC Block Diagram

SAR

Memory

Interface

High

Speed

DMA

Controller

Traffic Management

Controller

ALC Internal Registers

Cell

Stream

Interface

Cell

Stream Interface

Processor Interface

ATM

Cell

Transmitter

Transmit

Buffer

( 3 Cells )

Receive

Buffer

( 2 Cells )

Segmentation &

Convergence

Sub-layer

Controller

Reassembly and

Convergence

Sub-layer

Controller

ATM

Cell

Receiver

VCI Status/

Descriptor

Table

Edition 2.0 MB86687A

3.1 DMA Controller and SAR Memory Interface

3.1.1 General

The ALC contains an intelligent DMA

Controller to manage the segmentation

and reassembly of user data packets

using the minimum of host processor

intervention. Communication with the

host processor is mainly through shared

data structures in either dual port or

system memory.

The system implications of a dual port or

system memory approach are largely

performance related.

3.1.2 Shared Data Structures

The shared data structures used to

control the segmentation and

reassembly of user data are shown in

Fig. 4 on page 10. The transmit side is

controlled via the Transmit Pending

Queue, the Transmit Descriptor Table,

the Circuit Reference Table and the

Transmit Buffer Release Queue. The

ALC uses reserved fields in the T ransmit

Descriptor to compose peak rate queues

for segmentation at the specified peak

rate and for leaky bucket averaging. The

host can program up to 12 peak rates for

the ALC.

The receive side is controlled by the

Receive Buffer Free Queue, the Receive

Descriptor Table and the Receive Buffer

Ready Queue. In addition the DMA

Controller uses an internal RAM table,

the Receive Status / Descriptor Table to

store receive VCI status and descriptor

identifiers. The purpose of each of these

tables is described below.

3.1.3 Transmit Data Structures

The host writes commands to the

Transmit Pending Queue to instruct the

ALC to queue a data packet for

segmentation. The packet can be

queued for transmission on one of 12

peak rate queues. Each Transmit

Pending Queue entry contains a pointer

to a Transmit Descriptor in the Transmit

Descriptor Table.

The Transmit Descriptor Table is

composed of up to 4096 descriptors.

Each descriptor contains a pointer to

data for segmentation. The reserved

fields in the Transmit Descriptor are used

by the ALC to construct queues of

transmit packets for each selected peak

rate. The Transmit Descriptor also

contains a pointer to an entry in the

Circuit Reference Table (CRT).

The CRT is composed of up to 1024

entries, one entry for each active Virtual

Circuit. Each entry contains fields for the

ATM cell header, an optional routing tag,

and the leaky bucket parameters for the

virtual circuit. The ALC reads the cell

header and the leaky bucket parameters

from the CRT each time a cell is

segmented from a transmit buffer.

Management of the Peak Rate

segmentation queues is handled

autonomously by the ALC. The only host

intervention required is on a per packet

basis. To queue a packet the host

constructs the relevant descriptor and

writes the pointer to the descriptor into

the Transmit Pending Queue. Transmit

descriptors are recovered by the host by

reading the Transmit Buffer Release

Queue.

Edition 2.0MB86687A

Fig. 4 – Shared Data Structures

CR = b CR = b

ALC

QUEUE H1

QUEUE H2

QUEUE L3

QUEUE L4

CR = z

Packets Queued

For Segmentation

At Peak Service

Rate H1

Packets Queued

For Segmentation

At Peak Service

SAR MEMORY

Rate L4

CR = x

CIRCUIT REFERENCE TABLE TRANSMIT PENDING QUEUE

RECEIVE VCI STATUS TABLE

DMA

ALC

SEGMENTING WAITING

ENTRY 0

ENTRY 1023

HOST WRITE

ALC READ

ADDRESS

DATA

CR = Circuit Reference

ENTRY 0

1023

TRANSMIT DESCRIPTOR TABLE

TRANSMIT BUFFER

RECEIVE BUFFER READY QUEUE RECEIVE BUFFER FREE QUEUE

HOST WRITE

ALC READ

ENTRY 0

1023

RECEIVE DESCRIPTOR TABLE

RECEIVE BUFFER

Private ALC working space

for Peak Rate Management

and Leaky Bucket Averaging

ALC WRITE

HOST READ

TX BUFFER RELEASE QUEUE

CR = a

CR = n

CR = x

CR = z

ALC WRITE

HOST READ

Edition 2.0 MB86687A

After a packet has been transmitted, the

ALC will return the Transmit Descriptor

used to the host via the Transmit Buffer

Release Queue. Each entry in this queue

contains a pointer to the relevant

descriptor in the Transmit Descriptor

Table.

3.1.4 Receive Data Structures

At the start of reassembly for each new

packet the ALC finds a new Receive

Descriptor (RD) by reading the Receive

Buffer Free Queue. Each entry contains a

pointer to a RD in the Receive Descriptor

Table.

The Receive Descriptor Table is

composed of up to 4096 RDs. Each RD

contains a pointer to a receive buffer . The

RD also contains fields to support receive

buffer chaining and the received VCI or

MID fields. A reserved field in the RD is

used by the ALC to support a receive

buffer ageing timeout.

After reception is complete, the ALC

passes the receive descriptor to the host

using the Receive Buffer Ready Queue.

Each entry in the queue contains a

pointer to the appropriate RD and the

status of the receive buffer.

A more detailed description of the shared

data structures is provided in Section 4,

Developers Notes, of this datasheet.

3.1.5 Packet Segmentation

The DMA Controller is responsible for

linking transmit descriptors into one of

the 12 service rate queues. The queues

are composed of a linked list of TDs. The

structure of each of the service rate

queues is shown in Fig. 5.

When the ALC reads a transmit packet

command from the Transmit Pending

Queue, it links the packet into the service

rate queue specified in the appropriate

Circuit Reference Table entry (see

Fig. 20 on page 36).

VCI = N VCI = N VCI = N

VCI = L VCI = L

VCI = M

Fig. 5 – Transmit Queue Structure

Vertical

Queue

(Different

VCs)

Horizontal

Queue

(Same VCs)

Edition 2.0MB86687A

Packets with the same circuit reference,

ie same VPI/VCI or MID are queued

horizontally. Packets with different circuit

references for transmission on the same

service rate queue are queued vertically.

Horizontally queued packets will be

serviced when the packet at the front of

the queue is completed.

Each service rate queue is serviced

vertically at the specified peak rate under

the control of the Traffic Management

Controller. A queue entry has been

serviced when a complete SAR–PDU

payload of either 44 or 48 bytes has been

read from the packet. The queue has

been serviced when each queue entry

linked vertically has been serviced.

Message Mode Operation

In Message Mode, the user data buffer

associated with a Transmit Descriptor will

contain the full CS–PDU payload to

which the CS–PDU header and trailer will

be added to terminate the protocol.

Alternatively, the CS–PDU payload may

be spread across several user data

buffers when the host passes a chain of

TDs to the ALC. The CS–PDU header will

be added to the first user data buffer in

the chain. The ALC will work through the

chain until the CHAIN END bit is cleared

(CE = 0) and then the CS–PDU trailer will

be added.

Streaming Mode Operation

In Streaming Mode, a partial

segmentation can be accomplished. This

allows the user data unit to be partially

received into SAR memory and for

segmentation to commence before the

whole unit is received.

Table 2 describes single buffer, chaining

and streaming modes for the ALC. It

should be noted that the transmit and

receive sides work independently.

Transmit operation is controlled by the

Transmit Descriptor on a packet by

packet basis. The whole receive side is

controlled by Control Register17 (see

Fig. 43 in Appendix B.).

3.1.6 Packet Reassembly

The DMA Controller maintains the status

of each receive connection using the

internal Receive Descriptor / Status

table. This table is accessible to the host

for initialisation purposes, diagnostics

and support for scatter/gather mode.

The host must activate each connection

using the host access registers 57 to 59

(Fig. 58 & Fig. 59). The AAL type and

ACT bits must be initialised to the

required value.

Message Mode Operation

In Message Mode, the user data buffer

associated with a Receive Descriptor will

contain the full reassembled CS–PDU

payload.

If the size of this payload exceeds the

buffer size the buffer will be returned to

the host with a buffer overflow indication.

Alternatively, the CS–PDU payload may

be spread across several user data

buffers when the host programs the ALC

for receive buffer chaining operation. The

head of the chain of buffers will be passed

back to the host when the end of

message is received.

Edition 2.0 MB86687A

Streaming Mode Operation (PR)

The size of the CS–PDU payload may be

much greater than the size of one receive

data buffer. In addition, the memory

resource as a whole may be limited or the

user may require that sections of the

CS–PDU be forwarded to the host as

soon as they fill each buffer.

This partial reassembly is accomplished

by programming the ALC for streaming

mode operation.

Buffer Chaining is not possible when the

streaming mode register bit has been

programmed.

MESSAGE MODE STREAMING MODE

OPERATION DIR SINGLE BUFFER CHAINING

Queue

Packet Tx M=0, CS=0, CE=0

Whole packet in

single buffer

M=0

CS 1st buffer=0

CS other buffers=1

CE last buffer=0

CE other buffers=1

M=1, CS=0 in first

buffer

CE=0

Add buffers

via TPQ

Tx NA NA M=1 in extra buffers

M=0 in last buffer

CE=0

Release

buffer Tx When packet Tx

complete Released on a buffer

by buffer basis

(–> TRBQ)

Released on a buffer

by buffer basis

(–> TRBQ)

Start

Re-assembly Rx BCHAIN=O,

SMODE=O

Get next BFQ entry

BCHAIN=1,

SMODE=0

Get next BFQ entry

BCHAIN=O,

SMODE=1

Get next BFQ entry

Buffer full Rx Error buffer overflow Get next BFQ entry

Link buffers Get next BFQ entry

Release buffer to

host (–> RBRQ)

Packet

complete Rx Release buffer to

host Release first buffer

to host (–> RBRQ)

Release buffer to

host (–> RBRQ)

Notes:

* In Transmit Streaming mode the host must queue all current packet buffers on any given

circuit before starting a new packet.

** In Receive Chaining the host will be given the descriptor reference of the first buffer in

the chain. The host must follow the chain until the condition V=0 is set in the descriptor.

Table 2 – Single Buffer, Chaining and Streaming Modes

Edition 2.0MB86687A

Buffer Ageing Support

Buffer Ageing support is programmed by

setting bit D12 (BAS) in Register 17. If

set, upon reassembling the first cell of a

packet, the ALC stamps a time base in

the RD.

On reassembly of further cells for the

same packet, the ALC compares the time

elapsed against the value programmed

in Register 52 – Receive Buffer Timeout

Counter Register.

If the difference is greater than the value

in this register, the RD is returned to the

Buffer Ready Queue with a code ‘1100’

indicating Buffer Timed Out –

Reassembly Aborted. The rest of the

packet will be discarded by the ALC.

For a greater time range, Register 51 –

Receive Buffer Timeout Counter Period

scales the DCCK used to increment the

time base counter . For example, a DCCK

at 25MHz provides a time range up to 170

seconds.

Buffer Ageing Support is only available in

Message Non–Chaining mode.

Maximum Packet Length

At the start of cell reassembly, the ALC

compares the value of Bytes Received

accumulated in the RD with the value

programmed in Register 54 – Maximum

Received Packet length Register.

If the register value is exceeded, the ALC

writes out the RD to the Buffer Ready

Queue with a code ‘1001’ indicating

Receive Maximum Length Exceeded.

For Message Chaining mode, the ALC

compares the accumulated value of

Bytes Received to date across the chain

at the moment of adding a further RD to

the chain.

Maximum Packet Length checking is not

supported in Streaming mode.

Edition 2.0 MB86687A

3.2 Traffic Management Controller

The Traffic Management Controller is

responsible for the following functions:

Initiate periodic packet segmentation

from one of the 12 Peak Rate Queues

at intervals specified in the Queue

Service Rate registers. The queues

are grouped into three priority

classes: high, medium and low , with 4

queues in each priority class.

Manage total ALC peak transmission

rate. If the total peak transmission rate

exceeds a specified threshold, the

traffic management controller will

service the queues according to their

priority until the total peak rate falls

below the threshold. This feature can

be used to ensure that the ALC will not

exceed the negotiated quality of

service for the overall link connection.

Manage average rate shaping of

transmit traffic on a per virtual circuit

basis using the leaky bucket

algorithm. The leaky bucket

parameters for this are supplied from

the Circuit Reference Table

referenced in the Transmit Descriptor.

Manage average rate shaping on the

total ALC transmission according to

the leaky bucket algorithm. The leaky

bucket parameters for this averaging

are determined by the ALC Peak Cell

Transmission and ALC Average Cell

Transmission registers. This feature

is also used to ensure that the ALC will

not exceed the quality of service for

the overall connection.

3.2.1 Peak Rate Queue Service

Requests

The ALC peak rate queue service control

logic is responsible for requesting the

transmission of cells queued to the peak

rate queues on a per virtual circuit basis.

Twelve programmable counters are used

to specify the peak transmission rate for

each queue.

The twelve counter values are

programmed using the Queue Service

Rate Registers and enabled using the

Queue Enable Registers. The counter is

clock TXCLK (for TXCLK period, see

Appendix C.) which can be pre-scaled to

increase it’s dynamic range. The peak

service rate value is used to determine

the frequency of access to the respective

peak rate queue. Each time the queue is

accessed one cell may be transmitted for

each queued entry (one per VC) if a leaky

bucket token is available for that queue

entry.

Each Circuit Reference Table contains a

sub rate select field which can be used to

further reduce the peak cell transmission

rate to 50% or 25% of the nominal peak

rate specified in the Queue Service Rate

range of 32 effective peak transmission

rates for entries of each peak rate queue.

3.2.2 Total ALC Peak Rate Control

The ALC contains link capacity control

logic which is used to ensure that the

overall ALC link transmission rate does

not exceed a pre-programmed value as

specified in the ALC Peak Cell

Transmission Rate register.

Edition 2.0MB86687A

If the overall required transmission rate

exceeds this programmed value, the link

capacity controller will mask the lower

priority queues. This will cause cell

transmission to cease on the low priority

queues until the overall peak rate falls

below the programmed total ALC value.

Note that the queues are masked in the

following priority: All four L queues

followed by all four M queues.

3.2.3 Per VC Leaky Bucket Traffic

Shaping

The leaky bucket algorithm is used to

shape the transmit data characteristics

on a per virtual circuit basis by controlling

the average rate of cell transmission and

the length of each burst of cells

generated. The leaky bucket parameters

are determined by the values in the

Circuit Reference Table for each active

VC. (See section 3.1.3, Transmit Data

Structures).

The parameters relevant to leaky bucket

management are the user

programmable parameters, Bucket

Capacity , M and the Bucket Utilization, U.

The bucket capacity is used to calculate

the maximum sustained burst of cells at

the specified peak rate. The average rate

of emptying the bucket is derived from

the utilisation.

The utilisation is expressed as a fraction

of the peak rate. See section 4 on ALC

configuration and control for full details.

Two modes of operation are supported:

single leaky bucket mode and double

leaky bucket mode.

In single leaky bucket mode, cells are

transmitted in an initial burst as defined

by M at the specified peak rate. The burst

length may exceed the bucket capacity

since tokens are added to the bucket at

the same time as tokens are removed.

Subsequent cells are transmitted at the

average rate as tokens are added to the

bucket.

In double leaky bucket mode, cell

transmission will only occur in bursts at

the peak rate when the bucket

associated with that VC is full of tokens.

3.2.4 Total ALC Leaky Bucket

Traffic Shaping

In addition to the traffic shaping applied to

the traffic transmitted from each virtual

circuit the ALC can manage both the

peak and average transmission rate on

the total ALC output traffic.

A total ALC Leaky bucket size is defined

in the ALC Leaky Bucket Capacity

conjunction with the leaky bucket

utilization to limit the ALC output burst

length. The total ALC utilisation value is

derived from the ALC Peak Cell Rate and

ALC Average Cell Rate Register

contents.

Edition 2.0 MB86687A

3.3 Segmentation and Convergence Sub-layer Controller

This block is responsible for managing

the transmission of cells according to the

specified Adaptation Layer protocol:

AAL3/4 or AAL5.

3.3.1 SAR Sub-layer functions

Fig. 6 shows the format of SAR Protocol

Data Units (SAR–PDU ) for AAL types 3/4

and 5. The following protocol actions are

performed on each SAR–PDU for AAL 3/4:

Preservation of SAR service data unit

integrity through generation of the

segment type field,

Error Protection through Sequence

Number and CRC generation,

Multiplexing/Demultiplexing using the

Multiplexing ID,

Support of the Abort function.

The fields of AAL T ype 3/4 are detailed in

the following text.

ST, Segment Type

The first SAR–PDU generated from a

user data packet carries the Beginning of

Message (BOM) code 10. Subsequent

SAR–PDUs carries the Continuation Of

Message (COM) code 00.

The final SAR–PDU carries the End of

Message (EOM) code 01. SAR–PDUs

which carry entire SAR–SDUs such as

those defined for signalling carry the

Single Segment Message (SSM) code 1 1.

SN, Sequence Number

The four bits of this field are used for

modulo 16 numbering of each

SAR–PDU. The Sequence Number is set

to zero at the start of each SAR–SDU.

MID, Multiplexing Identification

This field is used for multiplexing multiple

CS–PDU (Convergence Sub-layer

Protocol Data Units) connections on a

single ATM layer connection. When MID

mode is selected, this field carries the

MID specified in the Circuit Reference

Table. The MID field is set to zero when

multiplexing is not used.

ST SN MID SAR–PDU Payload LI CRC

SAR–PDU

CELL HEADER

(a)

(b)

Fig. 6 – ATM Protocol Data Units (a) AAL3/4 (b) AAL5

SAR–PDU Header SAR–PDU Trailer

bits 4

bits 10 44 bytes 6

bits 10

bits

5 bytes 48 bytes

bytes bits

Edition 2.0MB86687A

LI, Length Indicator

This field indicates the number of bytes

contained in the SAR–PDU. The

SAR–SDU bytes are left justified within

the SAR–PDU payload field and

remaining bytes will be set to 0.

CRC, Cyclic Redundancy Check

This field contains the 10 bit CRC code. It

is calculated (as defined in CCITT I.363

for AAL3/4) over the SAR–PDU including

header, trailer, payload and length

indication.

3.3.2 Convergence Sub-layer

Functions

Fig. 7, below , shows how the user data is

formatted in the convergence sub-layer

before segmentation. The ALC maintains

internal tables to manage AAL3/4

sequence numbers and AAL5 CRC

results.

The fields of the CS–PDU header and

trailer are listed and described on the

following pages.

CRC 32LENGTH

CONTROL

FIELD

PADCS–PDU Payload

(b) AAL5

(a) AAL3/4

4 bytes2 bytes2 bytes0–47 bytes

CS–PDU trailer

CPI Btag BASize PAD AL Etag LENGTHCS–PDU Payload

CS–PDU trailerCS–PDU header

0–3 2 2

Fig. 7 – Convergence Sub-layer Protocol Data Units

11bytesbytebyte 0 – 64k bytes bytes 11

byte byte

1bytes

0 – 64k bytes

CPCS–UU CPI

CPCS–UU: CPCS User to User Indication

CPI: Common Part Identifier

Length: Length of CPCS–SDU

CRC: Cyclic Redundancy Check

CPI: Common Part Identifier

Btag Beginning Tag

BASize Buffer Allocation Size

AL Alignment

Etag End Tag

Edition 2.0 MB86687A

AAL 3/4 HEADER AND TRAILER

CPI, Common Part Identifier

This field is coded to all zeros to indicate

that the values in BASize and Length

Fields are measured as unit multiples of

bytes.

BTAG, ETAG, Beginning & End Tags

These Fields are given the same modulo

256 value for each CS–PDU and

incremented on successive CS–PDUs.

The receiver will check that they are the

same value on a CS–PDU to CS–PDU

basis but will not check for

incrementation over successive

CS–PDUs.

BASize, Buffer Allocation Size

This value will be the size of the CS–PDU

payload when Message Mode Service is

being run. In Streaming Mode this value

may be greater than or equal to the

CS–PDU payload size. Its purpose is to

inform the receiving entity of the buffering

required to accommodate the

transmitted data.

AL, Alignment

No information is conveyed by this field. It

merely provides 32 bit alignment in the

CS–PDU trailer. The Pad field has the

effect of making the CS–PDU an integral

multiple of 4 bytes.

Length

Length of CS–PDU payload.

PAD, Padding Field

This field complements the CPCS–PDU

to an integral multiple of 4 bytes and

conveys no information.

AAL 5 TRAILER

For AAL 5 the CS–PDU has no header.

The trailer is derived from the data

structure and the 32 bit CRC stored in the

convergence sub-layer table. The fields

of the CS–PDU trailer are listed below.

PAD, Padding Field

The purpose of the PAD bytes is to align

the CS–PDU trailer into the last 8 bytes of

a SAR–PDU. If this calculation results in

the transmission of an extra cell it is not

transmitted back to back with the

previous SAR–PDU, as this would

compromise the transmission rate and

the Traffic Management Controller

parameters.

Control Field

The Control Field comprises 2 fields

shown in Fig. 7. These fields are:

CPCS–UU

This field is used to transparently

transfer CPCS user to user

information.

CPI

This field is used to align the

CPCS_PDU to 64 bits and should be

coded as zero.

Length

Length of CS–PDU payload.

CRC, Cyclic Redundancy Check

The CRC field is filled with the value of a

CRC calculation (as defined in CCITT

I.363 for AAL 5) which is performed over

the entire contents of the CS–PDU. This

includes the payload, the PAD field, and

the first four bytes of the trailer . The initial

CRC remainder is preset to all ones

before generation and checking.

Edition 2.0MB86687A

3.3.3 Error Recovery & Notification

The ALC provides provisions for sending

SAR–U–ABORT ATM Cells in streaming

mode in accordance with the selected

protocol. In accordance with AAL5

protocol the ABORT SAR–PDU is

defined as SDU=1, LENGTH FIELD

coded to zero and CRC32 correct. In

accordance with AAL3/4 protocol the

ABORT SAR–PDU is defined by ST=

EOM, payload coded to zero, and LI = 63.

The CRC–10 and MID field must be valid.

3.3.4 Transparent Modes

Transparent Cell Mode

In this mode the host provides cells of 52

bytes (4 header and 48 data) in a

transmit descriptor to the transmit

pending queue. The transmit side

generates and includes the HEC byte (if

mode register 17 bit D9 = 0) and

transmits the resulting 53 byte cell with an

optional CRC10 included otherwise no

further protocol carried out.

On receiving a transparent cell the

receive side checks and removes the

HEC byte before loading the remaining

52 bytes into the internal receive buffer.

The receive side DMA then obtains a

descriptor from the buffer free queue,

writes all 52 bytes into the buffer and then

writes out the descriptor to the buffer

ready queue.

Note that the only updated field within the

receive descriptor is the VCI field (the

bytes received is not updated as it is

always 52).

Transparent Payload Mode

In this mode the host provides a multiple

of 48 bytes of cell payload data within a

single transmit descriptor to the transmit

pending queue. The header information

is obtained from the Circuit reference

table, a HEC byte is generated (if mode

transmitted. As with transparent cell

mode, apart from including an optional

CRC10, no further protocol is performed.

The receive operation is also similar to

transparent cell mode but with only the 48

payload bytes being transfered by DMA

to SAR memory. The CRC 10 can be

checked if the cell is detected to be an

OAM or Resource management cell.

Edition 2.0 MB86687A

3.4 Reassembly and Convergence Sub-layer Controller

This block is responsible for managing

the reception of cells according to the

specified Adaptation Layer protocol:

AAL3/4 or AAL5.

The following adaptation layer functions

are performed on a SAR–PDU basis:

Preservation of SAR service data unit.

Checking the Segment Type Field,

Error Detection and Handling.

CRC and Sequence Number

Integrity Checking,

Multiplexing / Demultiplexing using

the MID field,

Support of the Abort Function.

The following adaptation layer functions

are performed on a CS–PDU basis:

Detection of BTag, ETag fields,

Detection of Incorrect Length Field,

Detection of Alignment errors,

Detection of errors using CRC 32

calculation.

Fig. 8 – Cell Stream Interface

Tag

(0–3 bytes) ATM Cell (52 or 53 bytes) Tag

(0–3 bytes)

52 to 56 clock cycles idle period

(n clock cycles,

n > or = 0)

TXD[0–7]

TXSOC

TXCLK

Tag

(0–3 bytes) ATM Cell (52 or 53 bytes) Tag

(0–3 bytes)

52 to 56 clock cycles idle period

(m clock cycles,

n > or = 0)

RXD[0–7]

RXSOC

RXCLK

Edition 2.0MB86687A

3.5 Cell Stream Interface

The Cell Stream Interface will transmit

and receive an asynchronous stream of

ATM cells. Cells will be transmitted and

received in 8-bit parallel form with

separate synchronisation signals used to

identify the start of a cell.

The ALC cell stream interface may be

required to operate in one of two

environments either in a Switch Device or

a Termination Device.

3.5.1 Termination Device

Operation

In termination device operation the ALC

is intended to connect to the Fujitsu

MB86683 Network Termination

Controller or equivalent device for

physical media interfacing. Cells are

transmitted and received header to trailer

or with an idle period between each cell,

see Fig. 8.

The idle period may be of any number of

clock cycles including zero. There is no

relationship between the transmit and

receive sync pulses.

3.5.2 Switch Device Operation

In switch device operation, for example in

hub and router applications, the ALC can

be connected directly to an ATM switch

fabric port such as the Fujitsu MB86680

Self–routing A TM Switch Element, or to a

proprietary backplane structure.

In this environment the ALC will append a

programmable routing Tag of up to 3

bytes to the start of each cell. In the

receive direction the Tag is removed

before protocol processing of the cell

commences. In addition, the HEC field

can optionally be omitted resulting in a 52

byte cell. Switch Device timing is also

shown in Fig. 8.

3.5.3 Cell Stream and UTOPIA

The Fujitsu Cell Stream mode has been

superceded by the UTOPIA specification

from the A TM Forum, but is still supported

for backward compatibilty. The mode

selection is performed by tying the CS/UT

pin high or low as required. By default,

Fujitsu cell stream is selected by an

internal pull–up resistor.

3.5.4 Utopia Flow Control

Forward and backward byte-level flow

control is supported in both directions.

The forward flow control signal indicates

the validity of the current data. The

backward flow control signal indicates

whether data will be accepted in a

particular cycle. Neither flow control

signal is directly qualified by the other :

they can change state independently.

Unused flow control inputs should be tied

off to their active levels. All signals are

transmitted and sampled on the rising

edge of the clock.

Timings for UTOPIA are illustrated in

Fig. 10 and Fig. 11. Note that all of the

flow control signals can change state

independently.

Edition 2.0 MB86687A

3.5.5 Cell Stream Flow Control

In Cell Stream mode the ALC will provide

an indication that its receive buffer is full

by using the RXEN output signal as

shown in Fig. 9. The other flow control

signals are not supported in Cell Stream

mode.

Unused flow control inputs should be tied

off to their active levels.

3.5.6 Loopback

When loopback is enabled (by setting the

TSTLP bit in CR16) the transmit data is

internally looped back into the receive

path. For this operation TXCLK must be

present but RXCLK need not be. The

transmit data will still appear on the

transmit interface. Flow control is

handled in loopback only in UTOPIA

mode.

Fig. 9 – Cell Stream Receive Interface Timing

RXCLK

RXEN

RXD0–7

RXSOC

Fig. 10 – UTOPIA Transmit Interface Timing

TXCLK

TXFULL

TXD0–7

TXSOC

TXEN

Invalid Invalid

Fig. 11 – UTOPIA Receive Interface Timing

RXCLK

RXEMPTY

RXEN

RXD0–7

RXSOC Invalid

Invalid

Edition 2.0MB86687A

3.5.7 Transmit Multiplex

Operations

A token passing mechanism is used

when more than one ALC share the same

cell stream interface. In this case the ALC

should be wired in a daisy chain

configuration using the TIN (Token In)

and TOUT (Token Out). This mechanism

is illustrated in Fig. 12.

TIN should be connected to the TOUT

output of an ALC higher up the daisy

chain. When the TIN input is inactive

(low), the ALC stops transmitting data

and places its TXD and TSN pins in high

impedance.

The ALC will transmit a Token pulse, on

TOUT, on the falling edge of TXCLK to

indicate that it has completed a cell

transfer or that it has no data to transmit.

Note that if one ALC is able to transmit

cells continuously on this interface (ie. no

gaps between cells) TOUT will only pulse

at the end of a cell if TIN is inactive one

clock period before the last byte in the

cell.

Fig. 12 – CSI Token In/Out Timing

Byte 52 Byte 53

TXD

TXCLK

TOUT

TXCLK

TXD

TIN (TOUT

ALC2)

TOUT

TXSOC

TOUT timing at the end of a Cell

TIN timing at the start of a Cell (2 ALCs Daisy Chained)

Byte 2Byte 1

Edition 2.0 MB86687A

3.5.8 TXDRV (TX cell stream Drive):

Earlier ALC devices needed pull down

resistors on the TX cell stream interface

because the selection of Cell Stream

Daisy Chaining was controlled by a

MB86687 allows these resistors to be

omitted.

This mode is selected by tying the

TXDRV pin low. By default, it is

deselected by an internal pull–up resistor

and the register controls the operation.

3.5.9 Receive Circuit Reference

and VPI/VCI Filter Mechanism

The ALC constructs a 10 bit receive

circuit value depending on the setting of

the RID bit in register 17.

RID 0

Receive Circuit Reference value is equal

to VPB least significant bits of the VPI

field concatenated with (10–VPB) least

significant bits of the VCI field where VPB

is the value of VPI bits to be used in the

receive address mapping, specified by

bits VPB2, VPB1 and VPB0 in register 16.

AF17–AF14 matched with VPI11–VPI8

for NNI mode.

AF17–AF14 are not considered for UNI

mode.

AF13–AF0 matched with unused VPI bits

concatenated with unused VCI bits.

For VPI filter inactive (VPF=0) the mask

bits for the unused VPI bits must be

cleared to zero.

RID 1

Receive Circuit Reference is equal to the

value in the MID field (AAL3/4 only).

The Receive Circuit Reference value

should be used during programming

channels. When re–assembling a

packet, this value is loaded into the

receive circuit reference field in the

receive descriptor.

The ALC performs filtering on the VPI and

VCI bits not used for the receive circuit

value. Bits AF17 and AF16 in register 16

together with bits AF15 – AF0 in register

56 make up the mask value to be used to

filter incoming cells. Programming of the

mask bits AF17–AF0 is dependent on the

settings of the UNSEL bit in register 16

and the VPF bit in register 17.

Edition 2.0MB86687A

3.6 Microprocessor Interface

The Microprocessor Interface is

responsible for supporting the following

functions:

Providing Host Processor access to

all programmable ALC registers,

Providing the Host Processor

initialisation / test access to the

Receive Status / Descriptor Tables,

Managing the ALCs interrupt

mechanism.

3.6.1 Interrupt Controller

The ALC will indicate certain abnormal

conditions using the Interrupt signal. The

cause of an interrupt is provided in the

Interrupt status register.

Each interrupt condition can be

individually masked to prevent external

interrupt signal generation. A full

description of each interrupt source is

given in Appendix B., Fig. 45 and Fig. 46

as part of the interrupt status register

description.

Edition 2.0 MB86687A

3.7 Segmentation and Reassembly Memory Interface

3.7.1 Features

The SAR interface is responsible for

accessing queues, tables and data

stored in either dedicated dual port

memory or within the host system

memory. The SAR interface can support

the following features:

Motorola or Intel compatible bus

cycles

Examples of Motorola and Intel Mode

Normal Read cycles are shown in Fig. 13

and Fig. 14 respectively.

Extended Intel (486) & Motorola (040)

modes.

These modes allow Single Cycle data

bursts. Examples of the Intel extended

normal and burst read cycles are shown

in Fig. 15 and Fig. 16 respectively.

Addressing Schemes

Little or Big Endian addressing

schemes in Intel mode;

Big Endian addressing schemes in

Motorola mode.

Other Features

Direct connection to Dual Port RAM;

Bus arbitration as required in DMA

mode;

DMA burst length limiting in the range

1 to 255 memory cycles.

READY/DTACK extended cycles in

Ready dependent SAR memory

mode.

Memory contention interrupt

generation in response to

READY/DTACK transition when using

Fast Cycle Mode.

SADRV ( TX cell stream Drive) –

Using the SADRV signal on MB86687

allows pull–up resistors to be omitted.

Earlier ALC devices needed pull–up

resistors on all the address and

control signals because the selection

of DPR or DMA modes was controlled

by a register.

This mode is selected by tying the

SADRV pin low. By default, it is

deselected by an internal pull–up resistor

and the register controls the operation.

Edition 2.0MB86687A

**CS

A0 – 23

R/W

DATA

Fig. 13 – Motorola 32 Bit Mode – Normal Mode Read Timing

SIZ0–1

DTACK

DCCK

**CS

A0 – 23

BLAST

DATA

Fig. 14 – Intel 32 Bit Mode – Normal Mode Extended Read Timing

BE0–3

READY

DCCK

READY is sampled on the falling edge of

DCCK at the end of state 3. The example

shown uses a synchronous READY

signal.

An asynchronous READY signal takes

one extra clock cycle to take effect due to

internal synchronisation.

Edition 2.0 MB86687A

**CS

A0 – 23

BLAST

R/W

DATA

Fig. 15 – Intel 486 Mode – Normal Reads Timing

BE0–3

ADS

READY

DCCK

**CSn

**CSn+1

ADDR

BLAST

R/W

DATA

Fig. 16 – Intel 486 Mode Single Cycle Burst Timing

BE0–3

ADS

READY

DCCK

Edition 2.0MB86687A

3.7.2 Start of Cycle Signals

There are four start of cycle signals. They

are as follows :–

TOCS

Transmit Overhead Cycle Start output.

TDCS

Transmit Data Cycle Start output.

ROCS

Receive Overhead Cycle Start output.

RDCS

Receive Data Cycle Start output.

These start of cycle signals are asserted

before the associated operation. In

normal mode, this will be one clock cycle

before the next operation. In Ready

Dependent mode where cycles are back

to back, the signal will be asserted during

the second clock of the previous cycle. In

shared memory systems, this period may

be indeterminate because an active start

of cycle may be asserted for an operation

that will occur after the bus has first been

released and then regained. When

stealing or forced bursting is enabled a

single start of cycle pulse may precede a

group of consecutive operations of the

same type.

DCCK

TDCS

TOCS

RDCS

ROCS

ADDRA

MRD

MWR

DATA

Memory Data ALC Data

Fig. 17 – Start of Cycle Signal Timing – Fast Mode Extended Read

Parity Bits

Parity generation and detection on a per byte basis is supported on the SAR memory

interface using four bi–directional signals.

Edition 2.0 MB86687A

A register bit determines if the parity

generation/ checking is to be odd or

even. If a parity error occurs an interrupt

is generated. This interrupt cannot be

disabled. The ALC does not drop bytes, it

purely informs the host that an error has

occurred.

3.7.3 DMA Cycle Optimisation

The ALC can be programmed to change

the cycle ordering on its DMA interface to

be optimal for different system

configurations This is achieved by

progressively setting more bits in the

most significant word of the DMA Mode

0H – cycles are compatible with 86A

ready dependent cycles.

1H – cycles are compatible with 86A

fast cycles with stealing on data

cycles only.

7H – cycles are optimised for dual port

RAM systems with stealing of data

and overhead cycles.

1FH – cycles are optimised for shared

memory systems where there may be

different memory partitions. The

cycles will be grouped according to

their type.

3.7.4 Transmit DMA CACHE

The ALC uses shared or private memory

to create and maintain queues of data

packets, packet segmentation

information and traffic management

data.

To reduce the number of overhead cycles

used to access these, a caching

mechanism may be used whereby the

parameters for up to 128 circuits can be

stored on–chip.

The cache is operated in the following

way and requires a small processor

overhead to maintain a table of cached

entries.

The host software assesses the traffic

requirements of each circuit and

makes a decision about which circuits

would benefit being in the cache.

The host signals to the ALC that a

circuit should be cached via the

Circuit Reference Table using the

cache start bit and address fields.

The host then schedules a packet or

packets via the TPQ mechanism.

On its first pass through the data

structures, the ALC fetches the

appropriate parameters from the

Circuit Reference Table and the

current Transmit Descriptor and

stores them on chip.

Subsequently the ALC will process

the internal copies of its data

structures.

Further queued packets will cause the

ALC to fetch the new Transmit

Descriptor information only.

Edition 2.0MB86687A

On completion of the packet, if no

more packets are queued, the cache

entry will remain valid but idle until a

new packet is queued or the entry is

overwritten with a new entry.

Additional codes added to the Buffer

Release Queue return codes will

notify the host when all packets for a

particular circuit have been

assembled. At this time the host can

choose to re-use the cache entry for

another circuit.

Edition 2.0 MB86687A

4. DEVELOPERS NOTES

4.1 Configuration Control Issues

This section is intended to give an

overview of the ALC from a system

programmers perspective. The following

operations need to be performed by the

host to configure the ALC.

Set up the shared data structures,

Set up queue addresses,

Set up queue service rate

parameters,

Program ALC mode registers.

During normal operation the host is also

required to perform the following

operations.

Pass user data buffers to the ALC for

transmission,

Reclaim used transmit buffers from

the ALC for reuse after transmission

completes,

Allocate receive buffer space for use

by the ALC,

Receive packets when completion is

indicated by the ALC,

Activate and de-activate virtual

circuits,

Respond to exception interrupts as

required.

These operations are explained in more

detail below.

4.2 Transmit Data Structures

A diagramatic view of the transmit side

data structures is shown in Fig. 18, a

detailed view of the pointer mechanism in

Fig. 19 and a diagramatic view of the

queue structure in Fig. 22. Before data

can be transmitted the host has to

programme the ALC with the base

address of the following transmit data

structures: Transmit Descriptor Table,

Circuit Reference Table, Transmit

Pending Queue and the Transmit Buffer

Release Queue.

In addition the host has to initialise the

appropriate entries in the Transmit

Descriptor and Circuit Reference Tables.

4.2.1 Transmit Descriptor Table

The Transmit Descriptor Table is

composed of a contiguous list of Transmit

Descriptors (TDs). The host composes a

TD for each packet to be transmitted and

adds the TD to the TD table. The table

can contain up to 4096 TDs. A TD is

composed of the fields shown in Fig. 20

on page 36.

Diagrams showing the implementation of

transmit queue organisation and

calculation of pointer addresses for both

TDs and Circuit Reference table entries

are given on the following pages.

Edition 2.0MB86687A

TRANSMIT

PENDING

QUEUE

TRANSMIT

BUFFER

RELEASE

QUEUE

Entry 0

etc.

ALC

CIRCUIT REFERENCE TABLES

TRANSMIT DESCRIPTORS

PACKET

BUFFER

(PAYLOAD)

host write

host read

See Fig. 21 for CRT entry format

See Fig. 20 for TD format

Fig. 18 – Transmit Data Structures

Transmit Descriptors contain

packet information including:

– length

– start of data pointer

Circuit Reference Tables

include traffic parameters

and cell header information

Entry 0

etc.

SAR MEMORY

Edition 2.0 MB86687A

Fig. 19 – Transmit Data Structures – Address Calculation

00000

TRANSMIT PENDING QUEUE TRANSMIT BUFFER RELEASE QUEUE

ALC READ PTR

HOST WRITE PTR

TRANSMIT DESCRIPTOR BASE ADDRESS

TRANSMIT DESCRIPTOR REFERENCE

DESCRIPTOR REFERENCE0000

ALC WRITE PTR HOST READ PTR

CIRCUIT REFERENCE BASE ADDRESS

00000000 TRANSMIT DESCRIPTOR BASE ADDRESS 00000000

00000000

00000TRANSMIT DESCRIPTOR REFERENCE +

TRANSMIT DESCRIPTOR TABLE

ENTRY m

ENTRY n

CIRCUIT REFERENCE 0000

CIRCUIT REFERENCE TABLE

PACKET m PACKET n

CIRCUIT REFERENCE BASE ADDRESS 00000000

CIRCUIT REFERENCE 0000

CIRCUIT yCIRCUIT x

ENTRY x

ENTRY y

ADDRESS

POINTER

ADDRESS

POINTER

ADDRESS

POINTER

ADDRESS

POINTER

DESCRIPTOR REFERENCE0000

CCT REF

Edition 2.0MB86687A

CIRCUIT REFERENCEMID

031

Fig. 20 – Transmit Descriptor

CS CG

UNUSED

AVAILABLE FOR USER SOFTWARE

RESERVED

TRANSMIT BUFFER SIZE

BUFFER START ADDRESS

AAL5 CONTROL FIELD /

NEXT CHAINED DESCRIPTOR REFERENCE

REMAINING BYTES FOR SEGMENTATION

91326 25 10

RESERVED

2324

CBS LBRABT IOC CLP RES

BA SIZE/LENGTH FIELD

M (More)

The host sets this bit to 0 to indicate that

the transmit buffer associated with this

TD contains the End of Message

segment of the CS–PDU. The ALC will

append a CS–PDU trailer after the end of

this buffer. All other TDs associated with

the buffer should have M set to 1.

S (Segmenting)

This bit is set by the ALC to indicate that

segmentation is in progress on the

transmit buffer. The host sets the S bit to

zero before passing the TD to the

Transmit Descriptor Table.

CE (Chain End)

The host sets this bit to 0 to indicate that

this is the last TD in the chain. If CE is set,

the ALC assumes that the Next Chained

Descriptor Reference field is valid.

CS (Chain Start)

The host sets this bit to indicate that the

associated transmit buffer is not the first

buffer of a chain or stream of descriptors.

This bit is used for AAL3/4 or for AAL5

when using external calculation of

Convergence Sublayer parameters.

CG (Congestion indication)

The host sets this bit to indicate that ATM

cells generated from the associated

buffer should have the congestion

notification bit set in the Payload Type

Field.

Edition 2.0 MB86687A

PT (Pass Transparent)

The host sets this bit to indicate that the

ALC should set the CG bit in the PTI field

and CLP bit of the ATM cell header

directly as coded in the Circuit Reference

Table for each cell, otherwise the CG and

CLP bits are as programmed in the

Transmit Descriptor.

MID (Multiplexing Identification)

The ALC writes this ten bit field into the

ATM cell’s MID field.

ABT (Abort)

The host sets this bit to instruct the ALC to

transmit an Abort cell as defined for

streaming mode operation. When an

abort AAL3/4 or AAL5 cell has been

transmitted the following queued

descriptor should not have the CS bit set

ie. it should be the first descriptor in a new

packet.

IOC (Interrupt On Completion)

The host sets this bit to indicate that the

ALC should generate an interrupt when

segmentation of the Transmit Descriptor

buffer is complete.

CLP (Cell Loss Priority bit)

The host sets this bit to indicate that ATM

cells generated from the associated

buffer should have the CLP bit set = 1.

CBS (Copy Buffer Size)

The host should set this bit if the Transmit

Buffer Size field is the initial value for

bytes for segmentation.

LBR (Leaky Bucket Reset)

The host should set this bit if the leaky

bucket variable capacity is to be

re–initialised the first time data is

re–assembled from this TD.

Circuit Reference

This field is a 10 bit index into the Circuit

Reference Table. It is shifted left by 4 bits

then added to the Circuit Reference

Table base address (shifted left by 8 bits )

to generate a pointer to the appropriate

entry in the Circuit Reference Table. The

circuit reference index could be either the

VCI or MID of the connection.

Remaining Bytes for Segmentation

This field is initially loaded with the total

number of bytes in the packet for

segmentation. This field is modified by

the ALC during packet transmission. In

streaming and chaining modes, the

length of each buffer can be any number

of bytes provided that the next streamed

or chained buffer can fill any remaining

partially assembled cell. In streaming

mode a buffer that does not terminate on

a cell boundary will be held by the ALC

until a subsequent buffer is linked on.

BA Size / Length Field

In AAL 3 /4 mode the ALC transmits this

value in the BA Size field of the AAL 3/4

CS–PDU header . In AAL5 mode the AAL

transmits this value in the AAL5 CS–PDU

trailer LENGTH field.

Reserved 0

These fields are for internal ALC usage.

They should be initialised to 0 and reset

to 0 when the host retrieves the transmit

descriptor through the transmit buffer

release queue but otherwise should not

be used by the host.

Reserved

These fields are for internal ALC usage

and should not be used by the host.

Edition 2.0MB86687A

Buffer Start Address

This 24 bit pointer provides the ALC with

the start address of the associated

transmit buffer. Any number of header

bytes can be read from a user data buffer

by writing the correct byte (non 32 bit

aligned) address to this location.

AAL5 Control Field /

Next Descriptor Reference

In chaining mode the host programs the

next descriptor reference in the chain into

this field. In AAL5 mode, this field

contains the Control Field of the CS–PDU

trailer only if this is the final TD in the

chain.

Transmit Buffer Size

This 16 bit value is set by the host. It

specifies the number of bytes in the

associated transmit buffer. This field is

optionally used by the ALC, if the CBS bit

is set, as the initial value of bytes for

segmentation.

Available for User Software

This field is not used by the ALC and will

not be used by future ALC devices. This

field may be utilised by user software.

Re–initialisation of Transmit Descriptors

Field Mode

Message Chaining Streaming

Segmenting (S) bit 0 0 0

AAL5 Control/

Next Chain set AAL5: control in last TD

Next chain descriptor Set last TD only

Buffer

Start Address Programmed by Host

AAL3/4 BASIZE

AAL5 Length set * AAL3/4: BASIZE in first TD

AAL5: length in last TD *

Bytes remaining Programmed by Host **

Reserved 0 Program to 0

Note * In AAL5, if the MAAL5 bit is set, this value is computed automatically by the ALC.

Note ** If copy buffer size is set, this field will be refreshed by the ALC to the value in the Transmit Buffer Size field.

4.2.2 Circuit Reference Table

The Circuit Reference T able is composed

of a list of contiguous Circuit Reference

entries. There is a Circuit Reference for

each active Virtual Circuit. Each Circuit

Reference Table entry contains the ATM

Cell header and the Leaky Bucket

parameters for the relevant VC. The

Circuit Reference is composed of the

following fields, see Fig. 21.

Routing Tag 0 – 3

Optional routing tag appended in

applications where the ALC is interfacing

directly with a Fujitsu Self Routing Switch

Element MB86680 device or any similar

device. Up to three octets of routing is

supported.

GFC – Generic Flow Control,

VPI – Virtual Path Identifier,

Edition 2.0 MB86687A

VCI – Virtual Channel Identifier,

PTI – Payload Type Identifier,

CLP – Cell Loss Priority.

These form the ATM Header Field as

defined by the UNI Specification. The

ALC will code the PT bit of the PTI field

according to the state of assembly of the

SDU.

U, Leaky Bucket utilisation parameter

This field contains the average rate of cell

transmission for leaky bucket

management expressed as a ratio of the

peak rate. The coding is as follows:

891011

1 1/2 1/4 1/8

Bit no.

Peak Rate

Ratio

The host can select any combination of

bits to generate the required average

rate. If the ratio is programmed to 1, the

peak and average rates will be identical

which could be used for constant bit rate

traffic. Average rates greater than 1 are

not supported.

ECS (External Calculation of SPCS)

This single bit instruction is used to select

the use of external memory for AAL5

CRC32 and AAL3/4 length field and

sequence number storage. This set by

the host for non–cached entries when

internal memory is not available. (Each

cache entry uses the storage of 8

equivalent VC entries)

Additionally used in transparent cell and

transparent payload to indicate to the

ALC that the CRC10 should be

calculated and placed in the last 10 bits of

the payload.

LEAKY BUCKET CAPACITY

031

VPIGFC

ROUTING TAG0 ROUTING TAG1 ROUTING TAG2

VCI

Fig. 21 – Circuit Reference Table Entry

SRS SQN AALT

RESERVED VARIABLE (M*)

347811121516192023242728

LEAKY BUCKET CAPACITY

CONSTANT (M)

1256

00000000

RESERVED UTILISATION

(U)

RESERVED

VCADDRESSRESERVED

Edition 2.0MB86687A

CHS (Cache Start)

Set by HOST.

CHSTS (Cache Status)

Initialised to ’0’ by the HOST, set by ALC.

CEV (Chain End Valid)

Initialised to ’0’ by the HOST, set by ALC,

CADDRESS (Cache Address)

(7 bit field): set by HOST; valid if the CHS

bit is set.

SRS (Sub-Rate Select)

These bits are used to select the required

sub-rate of the nominal transmit queue

peak rate. The coding is as follows.

Bit no. Sub-rate

selected

25%

50%

100%

0 0 see below

If the Circuit Reference Table for a circuit

is programmed with SRS=00 and

AALT=11 (AAL5 only) then the ALC will

omit leaky bucket calculations on

transmit for that circuit. This reduces

transmit overhead accesses for circuits

with 100% utilisation. This facility is

available on the high and medium priority

queues only.

SQN (Service Queue Number)

The host uses this field to assign the

associated Virtual Circuit to one of the 12

peak rate queues. The coding is as

follows:

Bit no. Peak Rate Queue

1010

Queue 1

Queue 12

Queue 1 corresponds to Low Priority and

Queue 12 corresponds to High Priority.

AALT (ATM Adaption Layer Type)

This field is used to specify the AAL type

for the VC. Two transparent modes can

also be selected. The coding is as

follows:

AAL Type selected

AAL 3/4

Transparent Payload

Transparent Cell

AAL 5

Edition 2.0 MB86687A

M (Leaky Bucket capacity constant)

M in the Circuit Reference Table entry is

the bucket capacity used to implement

leaky bucket averaging on a per VC

basis. The host programmes this field

with a Leaky Bucket capacity in the range

of 1 – 255. The relationship between the

bucket capacity (M), the utilization (U)

and the maximum burst length (B) at the

selected peak rate is given by:

M = ( B – 1 ) x ( 1 – U )

for single leaky bucket method and by:

M = B x ( 1 – U )

for double leaky bucket method.

Note:

If the resulting M value is not an integer

then in the single leaky bucket case M

should be rounded DOWN to the nearest

integer and in the double leaky bucket

case M should be rounded UP to the next

integer.

Also, for the single leaky bucket case a

minimum value of B is specified for each

utilization value as given below:

U = 0.875 minimum allowed B = 9,

U = 0.75 minimum allowed B = 5,

U = 0.625 minimum allowed B = 4,

For all other values of U the minimum

value allowed for B is 3.

M* (Leaky Bucket capacity variable)

The ALC uses this variable to implement

leaky bucket averaging on a per virtual

circuit basis. The host initially sets M* to

the same value as M, M* is then modified

by the ALC as the ALC implements the

leaky bucket algorithm for that VC. The

ALC uses the constant value M for

reference when carrying out leaky bucket

calculations. M* may also be refreshed to

M when the LBR bit is set in a TD.

Reserved

These fields are for internal ALC usage

and should not be used by the host.

4.2.3 Transmit Pending Queue

The transmit pending queue is used by

the host to instruct the ALC to queue a

transmit packet for segmentation. Each

command passed to the queue includes

a 12 bit index reference into the T ransmit

Descriptor table. A Transmit Pending

Queue entry is shown in Fig. 23.

This queue is defined by registers 2 – 6.

The Host Processor must assign values

for the Transmit Pending Queue base,

start address, end, read and write

pointers. The initial values of the read

and write pointers should be the start

address to reflect an empty queue.

To pass a new entry to the TPQ the Host

Processor should read the current value

of the on-chip write register . This address

should be used to store the new TPQ

entry. The host should then update the

write pointer register , wrapping around to

the start address if necessary.

Edition 2.0MB86687A

When the DMA Controller has available

transmit bandwidth (or once every five

segmentation periods), i.e a cycle where

cell segmentation is not required, it reads

the value of the Transmit Descriptor

Reference addressed by its internal read

pointer.

In addition, the T ransmit Pending Queue

can be used as follows:

DUtilisation adjustment;

The U value in the CRT pointed to by the

associated TD will be set to the given

value.

For cached entries, a dummy circuit

reference entry should be used to point to

the required cached address and the

CHS bit set.

DSend Express Cell;

If an entry is placed on the queue with the

1 100 coding then it will not be assigned to

a rate queue but will be sent immediately .

For streaming mode when transmitting

packets using non–integral cell length

buffers, the host may queue a last stream

transmit descriptor which results in the

cell started in the current buffer being the

last cell of the packet. For this case, the

last stream transmit descriptor must be

queued as follows:

DTPQ code=1010 if remaining bytes for

segmentation is zero;

DTPQ code=1001 if remaining bytes for

segmentation is non–zero.

Transmit

Buffer

Ready

Queue

Transmit

Pending

Queue

Receive

Buffer

Ready

Queue

Receive

Buffer

Free

Queue

Read

Write

REG 5

: REG 3

: = Start and End addresses

: REG 4

REG

6REG

REG

9REG

REG 10

: REG 7

: REG 8

Read

Read Write

REG 43

Read

REG 49

WriteWrite

: REG 46

: REG 47

: REG 41

: REG 42

Fig. 22 – ALC Queue Structures

ALC

TRW Interrupt RRW Interrupt

Edition 2.0 MB86687A

0 0 0 0 Queue Packet

Fig. 23 – Transmit Pending Queue Format

TPQ Code

01115 TRANSMIT DESCRIPTOR REFERENCE

0 0 0 1 Set Utilisation to 0.125

0 0 1 0 Set Utilisation to 0.25

0 0 1 1 Set Utilisation to 0.375

0 1 0 0 Set Utilisation to 0.5

0 1 1 0 Set Utilisation to 0.75

0 1 1 1 Set Utilisation to 0.875

1 0 0 0 Set Utilisation to 1.0

0 1 0 1 Set Utilisation to 0.625

1 0 0 1 Queue last cell (streaming – bytes remaining)

1 0 1 0 Queue last cell (streaming – no bytes remaining)

1 1 0 0 Queue Express Cell

1 1 1 1 Set Utilisation to 0

4.2.4 Transmit Buffer Release

Queue

The ALC returns segmented transmit

buffers to the host using the Buffer

Release Queue. Each queue entry will

contain a 12 bit reference index into the

T ransmit Descriptor table. A queue entry

is shown in Fig. 24.

This queue is defined by registers 2 and

7 – 10. The Host Processor must assign

values for the Buffer Release Queue

base, start address, end, read and write

pointers.

The initial values of the read and write

pointers may be the start address to

reflect an empty queue or the write

pointer may be set to the read pointer

minus 1 to reflect a pool of free buffers.

To release a buffer to the host the ALC

increments the TBRQ write pointer and, if

the IOC bit in the Transmit descriptor is

set, generates an interrupt. The host may

then choose to immediately

acknowledge this action by updating the

TBRQ read pointer or if using the queue

as a pool of free buffers, only update the

pointer when reusing the TD.

Edition 2.0MB86687A

Fig. 24 – Transmit Buffer Release Queue Format

01115

0 0 0 0 Default code

0 0 0 1 Changed Utilisation

TRANSMIT DESCRIPTOR REFERENCE

0 0 1 0 Packet complete. No further packets for this circuit

0 0 1 1 Packet complete. No further packets for this queue

BRQ Code

0 1 0 0 Buffer complete. Moving to next streamed buffer

0 1 1 0 Buffer complete. Awaiting next streamed buffer

0 1 0 1 Changed utilisation to 0

0 1 1 1 Buffer complete. No further packets in this queue. Awaiting next streamed buffer

1 0 0 0 Buffer complete. Not end of chain

1 0 1 0 Express Cell Sent

1 1 0 0 Abort sent

1 1 1 1 Abort sent. No further packets in this queue

1 1 1 0 Abort sent. No further packets for this circuit

4.2.5 INCWRAP – Wrap and

Increment Mechanism

When writing to the host–controlled

queue registers, if the most significant bit

of the control data bus is set, the ALC will

automatically increment its internal copy

of the pointer being written to regardless

of the pointer value specified on the data

bus.

T wo status conditions are available when

reading the host–controlled pointers:

EMPTY condition

If this bit is set, it indicates that the ALC’s

pointer for the queue is at the same value

as the host pointer’s value returned by

the read and that the queue is empty.

FULL condition

If this bit is set, it indicates that the host

pointer and ALC pointer values are the

same and that the queue is full.

Edition 2.0 MB86687A

4.3 Receive Data Structures

A detailed view of the receive data

structures is shown in Fig. 25, a detailed

view of the pointer mechanism in Fig. 26

and a diagramatic view of the queue

structures in Fig. 22. Before data can be

received the host has to programme the

ALC with the base address of following

receive data structures: Receive

Descriptor Table, Receive Buffer Free

Queue and the Receive Buffer Ready

Queue.

4.3.1 Receive Descriptor Table

The Receive Descriptor Table is

composed of a contiguous list of Receive

Descriptors (RDs). The host is

responsible for composing sufficient RDs

to handle the expected number of receive

packets.

Each time a start of packet cell is received

the ALC will use the next entry in the

Receive Buffer Free Queue to locate the

relevant RD in the table. A typical RD is

composed of the fields shown in Fig. 27

on page 48.

Diagrams showing the implementation of

the Receive queue organisation and

calculation of pointer addresses for RDs

and field entries are given on the

following pages.

V (Valid)

The ALC sets this bit to 1 to indicate that

the Next Chain Descriptor field in this

descriptor is valid. This is used in

chaining mode when the received packet

does not terminate in the current receive

buffer. When this bit is cleared to 0 it

indicates that the chain of receive buffer

descriptors terminates with this

descriptor. The host is required to

initialise this bit to 0 and also in chaining

mode to clear this bit to 0 before returning

the receive descriptor to the ALC through

the buffer free queue.

Next Chain Descriptor Reference

When receive buffer chaining is used this

12 bit field is programmed by the ALC

with the descriptor reference of the next

receive descriptor in the chain.

Reserved

These fields are for internal ALC usage

and should not be accessed by the host.

Receive Circuit Reference

This 10 bit field is programmed by the

ALC with the receive channel supplying

data to the associated receive buffer.

This channel number will imply a

particular VP/VC according to the

programming of VPB2, VPB1 & VPB0 in

is only valid in the first descriptor of the

chain.

CLP (Cell Loss Priority)

The ALC sets this bit to indicate that the

last ATM cell re–assembled into the

associated buffer had the CLP bit set = 1.

CI (Congestion Indication)

The ALC sets this bit to indicate that the

last ATM cell re–assembled into the

associated buffer had the CI bit set = 1.

GFC (Generic Flow Control)

The ALC sets this field to the GFC value

in the last ATM cell reassembled into the

associated buffer.

Edition 2.0MB86687A

BUFFER

FREE

QUEUE

BUFFER

READY

QUEUE

Entry 0

etc.

ALC

RECEIVE DESCRIPTORS

PACKET

BUFFER

(PAYLOAD)

host write

host read

See Fig. 27 for descriptor format

Fig. 25 – Receive Data Structures

Receive descriptors contain

reassembled packet

information including:

– length

– start of data pointer

Entry 0

etc. SAR MEMORY

RECEIVE

DESCRIPTOR

TABLE

1000

Edition 2.0 MB86687A

RECEIVE BUFFER FREE QUEUE RECEIVE BUFFER READY QUEUE

ALC READHOST WRITE HOST READALC WRITE

Fig. 26 – Receive Data Structures – Address Calculation

DESCRIPTOR REFERENCE

RECEIVE DESCRIPTOR BASE ADDR

+00000

DESCRIPTOR REFERENCE0000

00000000

1515 0

DESCRIPTOR REFERENCE

RECEIVE DESCRIPTOR BASE ADDR

+00000

00000000

PACKET m PACKET n

RECEIVE DESCRIPTOR TABLE

ENTRY m

ENTRY n

ADDRESS

POINTER

ADDRESS

POINTER

DESCRIPTOR REFERENCE0000

Unused

These fields should not be utilized by

user software but may be cleared to 0 by

the host.

Buffer Size

If the RDAU bit is set in Register 16, this

value is automatically copied into the

Remaining Capacity field when the RD is

first accessed. The value is not modified

by the ALC.

Available for User Software

This field is not used by the ALC and will

not be used by future ALC devices. This

field may be utilized by user software.

Edition 2.0MB86687A

NEXT CHAIN

RECEIVE CIRCUIT

031

Fig. 27 – Receive Descriptor

RESERVED

BUFFER START ADDRESS

TOTAL LENGTH

UNUSED

RESERVED

REMAINING CAPACITY

UNUSED

AVAILABLE FOR USER SOFTWARE

BYTES RECEIVED

AAL5 CONTROL FIELD /

DESCRIPT OR REFERENCE

REFERENCE

12 91013

RESERVED

23242728

AAL3 RESERVED

RESERVED

BUFFER SIZE

GFC

Bytes Received

This 16 bit field is programmed by the

ALC with the number of bytes written to

the associated receive buffer.This field

should be initialized to 0 and reset to 0

before returning the descriptor for reuse

through the buffer free queue. This count

is always a multiple of 4 bytes and hence,

will include up to 3 bytes of pad at the end

of a packet.

Remaining Capacity

This field indicates the number of unused

bytes within the associated buffer. This

field should be initialized to the buffer

capacity and reset to the buffer capacity

before returning the descriptor for reuse

through the buffer free queue. This count

is always a multiple of 4 bytes and hence,

will include up to 3 bytes of pad at the end

of a packet.

Buffer Start Address

This 24 bit pointer is programmed by the

host with the start address of the receive

buffer associated with this descriptor.

AAL5 Control Field /

AAL3 Reserved

When AAL5 is selected this field is used

to hold the received AAL5 control value

obtained from the incoming CS–PDU

trailer. If chaining is enabled then this field

is only valid in the initial receive

descriptor of the chain. In all other

descriptors in the AAL5 chain this field is

reserved. In AAL 3 for all descriptors this

field is reserved. In chaining mode this

field should be initialized to 0 and reset to

0 before returning the descriptor for

re–use through the buffer free queue.

Total Length

This 16 bit value is programmed by the

ALC with the total length field received in

the CS–PDU trailer. If chaining is used

then this field contains the total length

only in the initial receive descriptor of the

chain. In chaining mode this field should

be initialized to 0 and reset to 0 before

returning the descriptor for reuse through

the buffer free queue.

Edition 2.0 MB86687A

Re–initialisation of Receive Descriptors

Field Mode

Message Chaining Streaming

V & next chain RD N/R 0 N/R

Bytes Received 0 *0 *0 *

Remaining Capacity buffer size ** buffer size ** buffer size **

BufferStart Address Programmed by Host

AAL5 Control/AAL3 Reserved 0 0 0

Total Length N/R 0 N/R

N/R Reinitialisation not required

Note * If RDAU is set in Register 16, Bytes Received is automatically cleared when the RD is first accessed;

Reinitialisation is then not required.

Note ** If RDAU is set in Register 16, Buffer Size is automatically copied into Remaining Capacity when the RD

is first accessed. Reinitialisation is then not required.

4.3.2 Receive Buffer Free Queue

The Receive Buffer Free Queue is used

by the ALC to locate the next Receive

Descriptor each time a new packet is

received.

Each queue entry contains a reference

into the Receive Descriptor table. The

format of a queue entry is shown in

Fig. 28.

4.3.3 Receive Buffer Ready Queue

The ALC passes reassembled packets to

the host using the Receive Buffer Ready

Queue. Each queue entry contains a

reference to the relevant Receive

Descriptor . In addition the ALC writes the

status of the received packet to the Buffer

Ready Queue. The format of each queue

entry is shown in Fig. 29.

4.3.4 Increment and Wrap

Mechanism

This mechanism is similar to that used by

the transmit queues and is described in

section 4.2.5.

Fig. 28 – Buffer Free Queue Format

UNUSED

01115

RECEIVE DESCRIPTOR REFERENCE

Edition 2.0MB86687A

Fig. 29 – Receive Buffer Ready Queue Format

RBRQ Status

01115

0 0 0 0 Reassembly Complete With No Errors ( M=0 )

0 0 0 1 Buffer Complete With No Errors (M = 1)

RECEIVE DESCRIPTOR REFERENCE

0 0 1 0 Reassembly Complete With f5 OAM cell – CRC10 passed

0 0 1 1 Reassembly Complete With f4 or f5 OAM cell – CRC10 failed

0 1 0 0 Reassembly Complete With f4 OAM cell – CRC10 passed

0 1 0 1 Sequence Number Error

0 1 1 0 Invalid Length Indication

0 1 1 1 Partial reassembly: Missing EOM

1 0 0 0 Receive Buffer Overflow

1 0 0 1 Receive Maximum Length Exceeded

1 0 1 0 No Chaining buffers Available

1 0 1 1 AAL3 Trailer Error Indication

1 1 0 0 Buffer Timed Out Reassembly Aborted

1 1 0 1 Packet Length Error Indication

1 1 1 0 RAS Abort Indication (Reassembly Streaming)

1 1 1 1 AAL5 CRC 32 Error Indication || AAL3 BTag / ETag mismatch

Edition 2.0 MB86687A

4.3.5 Receive Descriptor Table

Access Mechanism

Writing to the Table

The write to RSD table process operates

in the following way. The host sets the

data intended for the RSD by writing it to

the Host Receive Descriptor/Status

T able Write Register (Register 58) – (This

will normally involve setting the ACT bit

when a channel is about to be activated).

The host then writes to the Host Receive

Descriptor/Status Table Access Register

(Register 59). The HOSTR and RD/WR

must be set to generate the internal write

to the RSD table. The values in Register

58 together with the AAL bits from

at the address specified by the VCI

values in Register 59.

The TAC interrupt will be generated in

response to the write to Register 59 to

inform the host that the RSD table has

been updated.

Reading from the Table

The read from RSD table process

comprises the following sequence of

events. The host writes to Register 59

setting HOSTR and clearing RD/WR.

This causes the ALC to carry out an

internal read to the RSD table using the

address specified by the VCI value in

The contents of the read are written to the

Host Receive Descriptor/Status Table

Read Register (Register 57) and the T AC

interrupt is generated indicating to the

host that Register 57 has been updated.

The host then reads the RSD table

contents from Register 57.

Notes

Accesses to Registers 57 and 58 have no

effect on the RSD table until Register 59

is written to.

During normal operation, Register 59

should not be written to with HOSTR and

RD/WR (bits D15 and D14) set after the

initialisation stage.

4.3.6 OAM Cell Handling

The ALC will flexibly handle incoming

OAM cells.

The ALC considers a cell to be an F5

OAM cell if the most significant bit of the

PTI field is set. This means that resource

management cells (PTI field = 110) are

also treated as these cells.

The ALC considers a cell to be an F4

OAM cell if the cell arrives on a channel

which has the RIP bit set and the AAL bits

set for T ransparent Cell mode (10) in the

RSD table.

If the DCOAM bit (CR16) is set, only F5

OAM cells are discarded. Discarded

OAM cells do not alter the dropped cell

counter value.

If cleared, the OAMCRC bit (CR16) only

disables CRC10 checking on F5 OAM

cells. The ALC always performs CRC10

checking on F4 OAM cells.

Edition 2.0MB86687A APPENDICES

A. REGISTER TABLE

The ALC register address table is shown

on the following pages. Please note that

the Register Tables TYPE field indicates

the type of host access cycle used to

access each register.

Abbreviations used are as follows:

R/O = Host read access only.

W/R = Host read/write access

W/O = Host write access only.

(T) = After initialisation, these

registers are updated using TCLK

and have a recovery time dependent

on TCLK.

CW/R = Host write access only after

setting the control write enable bit

(CWRE) of the ALC Control Register.

The Registers listed in Fig. 30 to Fig. 32

are further described in Appendix B.

An ‘x’ symbol in a register bit location

indicates that that bit is not used by the

ALC. These unused bits should be

written to ‘0’ when writing to the register

and will return ’1’ when reading the

All the ALC write registers are initialised

to 0 after power–up.

MB86687A APPENDICESEdition 2.0

Fig. 30 – ALC REGISTER MAP (1 of 3)

ADDRESS FUNCTION

TRANSMIT DESCRIPT OR TABLE BASE ADDRESS REGISTER

CIRCUIT REFERENCE TABLE BASE ADDRESS REGISTER

TRANSMIT QUEUE BASE ADDRESS REGISTER

TRANSMIT PENDING QUEUE START ADDRESS REGISTER

TRANSMIT PENDING QUEUE WRITE POINTER

7TRANSMIT BUFFER RELEASE QUEUE START ADDRESS REG.

TRANSMIT BUFFER RELEASE QUEUE WRITE POINTER

8TRANSMIT BUFFER RELEASE QUEUE END ADDRESS REG.

4TRANSMIT PENDING QUEUE END ADDRESS REGISTER

MODE REGISTER

CONTROL REGISTER

DMA MODE REGISTER

RESERVED

DMA BURST REGISTER

GFC/CI STATUS CHANGE REGISTER

TRANSMIT PENDING QUEUE READ POINTER

TRANSMIT BUFFER RELEASE QUEUE READ POINTER

RESERVED

INTERRUPT STATUS REGISTER

INTERRUPT MASK REGISTER

–––

R/O

TYPE

W / O

CW / R

W / O

W/R

R / O

Fig. 34

Fig. 35

Fig. 36

Fig. 33

Fig. 39

Fig. 41

Fig. 43

Fig. 44

Fig. 45

Fig. 46

Fig. 47

W/R

REF

Fig. 33

W/R

Fig. 34

Fig. 35

Fig. 36

Fig. 37

Edition 2.0MB86687A APPENDICES

Fig. 31 – ALC REGISTER MAP (2 of 3)

ADDRESS FUNCTION

ALC A VERAGE CELL TRANSMISSION RA TE REGISTER

ALC LEAKY BUCKET CAPACITY REGISTER

RESERVED

TRANSMIT QUEUE SERVICE ENABLE REGISTER

ALC PEAK CELL TRANSMISSION RATE REGISTER

RESERVED

RESERVED–––

–––

TYPE

W / O

TRANSMIT QUEUE SERVICE RATE REGISTER LOW 1

TRANSMIT QUEUE SERVICE RATE REGISTER LOW 2

TRANSMIT QUEUE SERVICE RATE REGISTER LOW 3

TRANSMIT QUEUE SERVICE RATE REGISTER LOW 4

TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 1

TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 2

TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 3

TRANSMIT QUEUE SERVICE RATE REGISTER MEDIUM 4

TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 1

TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 2

TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 3

TRANSMIT QUEUE SERVICE RATE REGISTER HIGH 4

Fig. 47

Fig. 48

Fig. 49

Fig. 50

REF

Fig. 47

Fig. 49

(T)

MB86687A APPENDICESEdition 2.0

Fig. 32 – ALC REGISTER MAP (3 of 3)

ADDRESS FUNCTION

43 RECEIVE BUFFER FREE QUEUE WRITE POINTER

RECEIVE BUFFER FREE QUEUE START ADDRESS REGISTER

RECEIVE DESCRIPTOR BASE ADDRESS REGISTER

RECEIVE BUFFER READY QUEUE WRITE POINTER

RECEIVE BUFFER READY QUEUE END ADDRESS REGISTER

RECEIVE BUFFER READY QUEUE STAR T ADDRESS REGISTER

RECEIVE BUFFER FREE QUEUE END ADDRESS REGISTER

HOST RECEIVE DESCRIPT OR / STATUS TABLE READ REG.

RECEIVE BUFFER READY QUEUE READ POINTER

RECEIVE BUFFER FREE QUEUE READ POINTER

RECEIVE BUFFER TIME OUT COUNTER PERIOD REGISTER

DROPPED CELL COUNTER

RECEIVE BUFFER TIME OUT INTER VAL REGISTER

DROPPED PACKET COUNTER

W / O

RECEIVE ADDRESS FILTER REGISTER

CW / R

W / O

CW / R

W / O

R / O

W / O

R / O

W / R

W / O

R / O

RECEIVE QUEUE BASE ADDRESS REGISTER

RECEIVED BUFFER READY DATA HOLD REGISTER

MAXIMUM RECEIVED PACKET LENGTH REGISTER

TYPE

R / O

W / O

HOST RECEIVE DESCRIPT OR / STATUS TABLE WRITE REG.

HOST RECEIVE DESCRIPT OR / STATUS TABLE ACCESS REG.

Fig. 51

Fig. 52

Fig. 53

Fig. 54

Fig. 55

Fig. 56

Fig. 57

Fig. 58

Fig. 59

W/R

REF

W/R

Fig. 51

Fig. 52

Fig. 53

Fig. 54

Fig. 55

Fig. 56

Fig. 58

Edition 2.0MB86687A APPENDICES

B. REGISTER MAPS

Fig. 33 – REGISTERS 0, 1 AND 2

This base address (shifted left by 8 bits) is added to the 12 bit Transmit Descriptor

address (shifted left by 5 bits) from the Transmit Pending or Release Queue to obtain

the full 24 bit address of the Transmit Descriptor required to execute a packet

transmission.

This base address (shifted left by 8 bits) is added to the 10 bit circuit reference address

(shifted left by 4 bits) from the Transmit Descriptor to obtain the full 24 bit address of the

Circuit Reference Table entry describing the circuit to be used when executing the

requested transmission.

XXXX00

TQA0TQA1TQA2TQA3TQA4TQA5TQA6

This register contains the upper10 bits of both the Transmit Pending and Buffer Release

Queue addresses. This base address is concatenated with the start or end address

(shifted left by 1 bit) or with the write or read pointers (shifted left by 1 bit) to obtain the

upper 23 bits of the system or dual port SAR memory address of the Pending or

Release Queue entry. Address bit 0 is always set to 0 by the ALC.

TDA15

TDA7

TDA14

TDA6

TDA13

TDA5

TDA12

TDA4

TDA11

TDA3

TDA10

TDA2

TDA9

TDA1

TDA8

TDA0

CRA15

CRA7

CRA14

CRA6

CRA13

CRA5

CRA12

CRA4

CRA11

CRA3

CRA10

CRA2

CRA9

CRA1

CRA8

CRA0

D15

TQA7

TQA9 TQA8

MB86687A APPENDICESEdition 2.0

Fig. 34 – REGISTER 3, 4 AND 5

TPS8TPS9TPS10TPS11TPS12XX

TPS0TPS1TPS2TPS3TPS4TPS5TPS6TPS7

TPE8TPE9TPE10TPE11TPE12XXX

TPE0TPE1TPE2TPE3TPE4TPE5TPE6TPE7

This offset address is shifted left by one bit and concatenated to the Transmit

Queue Base Address Register contents (shifted left by 14 bits) to obtain the

upper 23 bits of the Transmit Pending Queue end address. This end address

indicates the finish of the Transmit Pending Queue space which is used to pass

transmit request buffer descriptor addresses from the Host to the ALC. Address

bit 0 is always set to 0 by the ALC.

This offset address is shifted left by one bit and concatenated to the Transmit

Queue Base Address Register contents (shifted left by 14 bits) to obtain the upper

23 bits of the Transmit Pending Queue start address. This start address indicates

the beginning of the Transmit Pending Queue space which is used to pass

transmit request buffer descriptor addresses from the Host to the ALC. Address

bit 0 is always be set to 0 by the ALC.

TPW8TPW9TPW10TPW11TPW12FULLEMPTYINCWRAP

TPW0TPW1TPW2TPW3TPW4TPW5TPW6TPW7

This offset address is shifted left by 1 bit and concatenated to the Transmit Queue

Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of

the Transmit Pending Queue write pointer. The Host uses this pointer when entering

transmit requests by writing a transmit descriptor reference address to the transmit

pending queue. Address bit 0 is always be set to 0 by the ALC.

D15

INCWRAP – When writing to the host–controlled queue registers, if the most

significant bit of the control data bus is set, the ALC will

automatically increment its internal copy of the pointer being

written to regardless of the pointer value specified on the data bus.

EMPTY – If this bit is set, it indicates that the ALC’s pointer for the queue is

at the same value as the host pointer’s value returned by the read

and that the queue is empty.

FULL – If this bit is set, it indicates that the host pointer and ALC pointer

values are the same and that the queue is full.

Edition 2.0MB86687A APPENDICES

Fig. 35 – REGISTER 6, 7 AND 8

TPR8TPR9TPR10TPR11TPR12ASYNCIXX

TPR0TPR1TPR2TPR3TPR4TPR5TPR6TPR7

This offset address is shifted left by 1 bit and concatenated to the Transmit Queue

Base Address Register contents ( shifted left by 14 bits ) to obtain the upper 23 bits

of the Transmit Pending Queue read pointer. The ALC uses this pointer when

retrieving transmit requests by reading a transmit descriptor reference address

from the Transmit Pending Queue. Address bit 0 is always set to 0 by the ALC.

BRS8X

BRS0BRS7

BRS1BRS2BRS3BRS4BRS5BRS6

BRS9BRS10BRS11BRS12XX

BRE0BRE7 BRE1BRE2BRE3BRE4BRE5BRE6

BRE8X BRE9BRE10BRE11BRE12XX

This offset address shifted left by 1 bit is concatenated to the Transmit Queue Base

Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the

Transmit Release Queue start address. This start address indicates the beginning of

the Transmit Release Queue space used by the ALC to indicate the availability of free

transmit descriptors to the host. Address 0 is always set to 0.

This offset address shifted left by 1 bit is concatenated to the Transmit Queue Base

Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the

Transmit Release Queue end address. This end address indicates the finish of the

Transmit Release Queue space used by the ALC to indicate the availability of free

transmit descriptors to the host. Address 0 is always set to 0.

D15

ASYNCI – When set this indicates value was changing during an

asynchronous microprocessor read. Since this means an incorrect

transitional value may have been recorded the register should be

re–read.

MB86687A APPENDICESEdition 2.0

BRW8X

BRW0BRW7 BRW1BRW2BRW3BRW4BRW5BRW6

BRW9BRW10BRW11BRW12ASYNCIX

BRR8INCWRAP BRR9BRR10BRR11BRR12FULLEMPTY

This offset address is shifted left by one bit and concatenated to the Transmit Queue

Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of

the Transmit Buffer Release Queue write pointer. The ALC uses this pointer when a

packet transmission has been completed to return the transmit descriptor used to the

pool of free transmit descriptors for use by the host in future transmit requests.

Please refer to Register 6 on page 58 for a description of ASYNCI.

This offset address is shifted left by one bit and concatenated to the Transmit Queue

Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of

the Transmit Buffer Release Queue read pointer. The Host uses this read pointer to

obtain an available transmit descriptor when a packet is ready for transmission.

Fig. 36 – REGISTERS 9 and 10

D15

BRR0BRR1BRR2BRR3BRR4BRR5BRR6BRR7

INCWRAP – When writing to the host–controlled queue registers, if the most

significant bit of the control data bus is set, the ALC will

automatically increment its internal copy of the pointer being

written to regardless of the pointer value specified on the data bus.

EMPTY – If this bit is set, it indicates that the ALC’s pointer for the queue is

at the same value as the host pointer’s value returned by the read

and that the queue is empty.

FULL – If this bit is set, it indicates that the host pointer and ALC pointer

values are the same and that the queue is full.

Edition 2.0MB86687A APPENDICES

RCR9–0: Receive Circuit Reference of circuit with changed status.

Fig. 37 – REGISTER 13

D15 X CE GFC3 GFC2 RCR9GFC0GFC1

CE: Status of Congestion Experienced Bit.

GFC3–0: Status of GFC Field (UNI mode only).

RCR8

RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0

This register shows the status of the latest change in congestion experienced and

GFC status with its associated Receive Circuit Reference.

MB86687A APPENDICESEdition 2.0

DBL7–DBL0: This register may be set to limit the maximum number of ALC,

system memory DMA access cycles that may occur in a single

block. This burst length is applicable only when the ALC is

operating in ready dependent, DMA mode.

A burst length limit of 0 indicates unlimited burst length.

A burst length limit in the range 1 – 255 indicates the maximum

number of ALC DMA cycles that can occur before the bus is

released to allow re-arbitration for control of the system bus.

Fig. 38 – REGISTER 14

DBL7 DBL1DBL2DBL6 DBL4DBL5 DBL0DBL3 D0

D15 RIF3 RIF2 RIF1 RIF0 TIF0TIF1TIF2TIF3

RIF3–RIF0: Receive Buffer Ready Interrupt Frequency.

This count specifies the frequency of receive buffer ready

interrupts.

This value specifies the number of received buffers that are

completed before the ALC generates a service request to the

host using the Receive Buffer Ready Queue Write interrupt.

TIF3–TIF0: Transmit Buffer Release Interrupt Frequency.

This count specifies the frequency of transmit buffer release

interrupts.

This value specifies the number of transmitted buffers that are

completed with the IOC bit set before the ALC generates a

service request to the host using the Receive Buffer Ready

Queue Write interrupt.

Edition 2.0MB86687A APPENDICES

Fig. 39 – REGISTER 15

STEALDSTEALODMAOPTBURSTDBRSTOSCEPARSELSBL

WMOD BMODE1ORDERRMOD CMODE BMODE0MMODE

BURSTO: Burst Overhead. If this bit is set then the ALC will finish all control

transfers for transmit before switching over to receive and vice

versa.

SYN

SBL: Single Cycle Burst Length. This selects between 8–transfer (set)

and 4–transfer (cleared) data bursts.

BURSTD: Burst Data. If this bit is set then the ALC will finish all data

transfers for transmit before switching over to receive and vice

versa.

SCE: Single Cycle Enable. This bit is set to enable single clock cycle

burst data transfers

PARSEL: Parity Select. This bit is set for odd parity and cleared for even

parity.

D15

DMAOPT: DMA Optimise. Setting ths bit will cause the ALC to optimise the

dead cycles between overhead operations.

STEALO: Steal Overhead. If this bit is set then the ALC will allow transmit to

steal overhead cycles from receive and vice versa.

STEALD: Steal Data. If this bit is set then the ALC will allow transmit to

steal data cycles from receive and vice versa.

Note: Please refer to section 3.7.3 for an explanation of the setting

of the BURST and STEAL bits.

MB86687A APPENDICESEdition 2.0

Fig. 40 – REGISTER 15 contd.

STEALDSTEALODMAOPTBURSTDBRSTOSCEPARSELSBL

WMOD BMODE1ORDERRMOD CMODE BMODE0MMODE

ORDER: SAR Memory Byte Ordering Convention.

This bit is cleared to select Big Endian (Motorola/SPARC) byte

ordering and set to select Little Endian (Intel/DEC Alpha) byte

ordering. This byte ordering applies to the transmit and receive

buffer data and selected Endian word ordering applies to the queue

structures Descriptor data uses the Little Endian ordering convention.

The queue data format is configurable as Big Endian or Little Endian,

using word swapping.

SYN

SYN: 0 DMA treated as asynchronous.

1 DMA treated as synchronous.

BMODE1–0: SAR Memory Control Signal Mode.

00 Intel / GP Timings

01 Intel 486 Timings

10 Motorola Timings

11 Motorola 68x40 timings

MMODE: SAR Memory Mode.

This memory mode bit is set to select dual port RAM use for

segmentation and reassembly and cleared to select DMA use of

system memory for segmentation and reassembly.

CMODE: SAR Memory Cycle Time.

This bit is cleared to select ready dependent SAR memory cycles

(minimum cycle time = 2 x DCCLK) and set to select fast mode SAR

memory cycles (cycle time = 2 x DCCLK).

D15

WMOD: 0 WR signal as MB86686

1 WR signal extended.

RMOD: 0 Data sampled on falling edge of DCLK, RD signal as

MB86686.

1 Data sampled on rising edge RD signal extended.

Edition 2.0MB86687A APPENDICES

Fig. 41 – REGISTER 16

SRSTINIT CWRE

DCOAMUNSELAF16AF17

RSTRTTSTLP MAAL5L

VPB2–0: Virual Path Detect bits (Valid range 000 – 101). These are used to

control how many bits of the VP are used in the receive address

mapping.

AF17–16: Address Filter Bits 17 –16. These are the 2 msbs of the receive

address filter. For a full description of this function see section

3.5.9.

UNSEL: UNI/NNI Select. If set this bit uses an NNI address for filtering

(uses all 18 bits of Address Filter). If it is cleared it uses a UNI

address for filtering (used only 14 lsbs of the Address Filter)

MBRQE VPB2 VPB1 VPB0

D15

OAMCRC RDAU

DCOAM: Discard OAM. If this bit is set the ALC will discard all cells

received (excepting F4 cells) which are not user data cells.

MBRQE: Enable Buffer Ready Queue Interrupt when M=0. When in

streaming mode setting this bit will cause a buffer ready queue

interrupt to occur every time a packet is terminated (M=0)

irrespective of the setting of the receive buffer Interupt frequency.

MB86687A APPENDICESEdition 2.0

Fig. 42 – REGISTER 16 contd.

SRSTINIT CWRE

DCOAMUNSEL

RSTRTTSTLP MAAL5L

TSTLP: Test Loop Enable.

When this bit is set the ALC’s transmit cell stream interface is

internally looped back into the receive cell stream interface using

TXCLK.

RSTRT: ALC Cell Stream Interface Daisy Chain Restart.

When this bit is set a daisy chain token pulse is generated on

ALC’s TOUT line. This is used to restart the token daisy chain

if the token has been lost.

CWRE: ALC Host Queue Pointer Initialisation Enable.

This bit is set to allow the Host to initialise the Transmit Pending

Queue Read Pointer, the Transmit Buffer Release Queue Write

Pointer, the Receive Buffer Free Queue Read Pointer and the

Receive Buffer Ready Queue Write Pointer.

This bit should be cleared after initialisation for normal operation.

INIT: Host Initialisation Complete.

This bit is set by the Host when it (the host) has completed all

required initialisation of ALC registers and memory structures.

SRST: ALC Software Reset.

This bit is set to reset all internal ALC circuitry.

MBRQE VPB0 VPB1 VPB2

D15

OAMCRC RDAU

RDAU: Receive Descriptor Auto Update of Remaining Capacity. Setting

this bit enables automatic initialisation of the bytes remaining field

in the Receive Descriptor with the Buffer Size field and automatic

clearing of the Bytes Received field.

MAAL5L: Maintain AAL5 Length. Setting this bit will cause the ALC to

automatically compute the AAL5 length field across multiple

chained or streamed transmit buffers.

OAMCRC: OAM CRC checking. This bit should be set to enable CRC–10

checking on all non–user data cells excepting F4 cells.

AF17 AF16

Edition 2.0MB86687A APPENDICES

Fig. 43 – REGISTER 17

RIDDMASKDCHAINSMODEBCHAIN

HEC0HEC1HEC2VPFBASAMTRTL0TRTL1

TRTL1 – TRTL0: Transmit Routing Tag Length.

This field specifies the length (if any) of routing tag to be

appended to all transmitted cells.

00: No Routing Tag

01: One Octet Routing Tag

10: Two Octet Routing Tag

11: Three Octet Routing Tag.

AM: Traffic Rate Averaging Method.

This bit is cleared to select the single leaky bucket (trickle) method

of traffic rate averaging and set to select the double leaky bucket

(burst) method. The method chosen applies to averaging for each

individual virtual circuit and also for the total ALC output traffic.

BAS: Buffer Ageing Support.

This bit is set to support receive buffer ageing. For a full description of

this function, please refer to section 3.1.6.

VPF: Virtual Path Filter Enable.

If this bit is set then only incoming cells whose VPI matches the

value specified in the Receive Address Filter Register are processed.

If this bit is cleared then the incoming VPI value is ignored.

HEC2 – HEC0: Header Error Check Operation.

Cell header error check mask byte value.

HEC2 = 0 Mask = 0x55.

HEC2 = 1 Mask = 0x00.

HEC1 = 0 Transmitted cell header check octet included

( 53 byte cell ).

HEC1 = 1 Transmitted cell header check octet omitted

(52 byte cell ).

HEC0 = 0 Cell header error checking enabled.

HEC0 = 1 Cell header error checking disabled.

D15

0 RTL1 RTL0

MB86687A APPENDICESEdition 2.0

BCHAIN: Receive Buffer Chaining Mode Enable

Set to enable chaining mode whereby a single packet may be

located in different reassembly buffers each described by a different

descriptor but linked using pointers into a single chain.

Cleared to disable buffer chaining.

SMODE: Receive Streaming Mode Enable

Set to enable ALC streaming mode whereby processing of large

received packets can begin before all the packet data is available.

Cleared to disable streaming mode.

DCHAIN: Transmit Cell Stream Daisy Chain Enable

Set to allow multiple ALC devices to share a single network

interface device by using token passing. Cleared if using a single

ALC device per network interface device.

DMASK: Disable Transmit Queue Masking

Set to disable automatic service request masking from medium

and low priority queues when the total ALC data rate limit is

exceeded. Cleared to enable masking.

ie. DMASK = 0 High Queue Enabled Only

DMASK = 1 Low, Medium and High Queues Enabled

RTL1–RTL0: Receive Routing Tag Length

This field specifies the length (if any) of routing tag expected to be

appended to received cells.

00: No Routing Tag

01: One Octet Routing Tag

10: Two Octet Routing Tag

11: Three Octet Routing Tag.

RID: Reassembly ID Select (applies to entire receive side of the ALC)

RID = 0: VCI is used for addressing.

RID = 1: MID field is used for addressing.

Fig. 44 – REGISTER 17 (continued)

RIDDMASKDCHAINSMODEBCHAIN

HEC0HEC1HEC2VPFBASAMTRTL0TRTL1

D15

RTL1 RTL00

Edition 2.0MB86687A APPENDICES

Fig. 45 – REGISTER 18

TAC: Receive Status / Descriptor Table Access Complete.

Set when the host read or write access to the receive status/

descriptor table as requested through register 59 has completed.

RFE: Receive Buffer Free Queue Empty.

Set if no receive buffer descriptors are available for ALC use. Host

must service previously received packets.

TRF: Transmit Buffer Release Queue Full.

Set if the last available location in the transmit buffer release

queue has been used by the ALC. The host must respond to

previously completed transmissions by reading the transmit release

queue entries.

RRFL: Receive Buffer Ready Queue Write Fail.

Set if the ALC attempts to write to an already full receive buffer ready

queue. The host must service previously received packets.

RRW: Receive Buffer Ready Queue Write.

Set when the ALC has completed reception of a packet (or number of

packets – see register 16). Host must acknowledge reception by reading

the associated receive buffer ready queue entry.

RRFU: Receive Buffer Ready Queue Full.

Set when the receive buffer ready queue is full. The host must service

previously received packets.

INIT: Initialisation Complete.

Set when the ALC internal initialisation is complete.

TRW: Transmit Buffer Release Queue Write.

Set when the ALC has completed the requested packet transmission.

Host should acknowledge this by reading the corresponding release

queue entry.

On detection of an interrupt condition the ALC sets an interrupt flag in this register.

If the corresponding interrupt mask bit in Register 19 is set then the ALC activates

the output interrupt pin. The host processor may determine the interrupt cause by

reading this register. An interrupt is cleared and disabled by writing a ”1” to the

associated bit and re–enabled by writing a ”0”.

INITRRFUTRFRFE RRFLTAC TRW RRW

BUSERRSRCOMRRCOMDTCOMGFCCCECPARERRX

D15

MB86687A APPENDICESEdition 2.0

Fig. 46 – REGISTER 18 (continued) and 19

RRCOM: Receive RAM Test Complete.

Set by the ALC to indicate that the ALC’s internal receive scratch pad

memory test has completed.

SRCOM: Send RAM Test Complete.

Set by the ALC to indicate that the ALC’s internal transmit scratch pad

memory test has completed.

1 = Interrupt generation enabled

This interrupt mask register contains one bit for each possible interrupt source as

described for the Interrupt Status Register 18. above. Each interrupt condition can be

enabled to activate the ALC’s output interrupt signal by setting the corresponding interrupt

mask bit in this register. Likewise each interrupt source can be prevented from activating

the external interrupt pin by clearing the corresponding bit in this register.

For each mask location:

0 = Interrupt generation masked.

1 = Interrupt generation enabled.

INITRRFUTRFRFE RRFLTAC TRW RRW

BUSERRSRCOMRRCOMCECPARERRX

D15

DTCOM: Descriptor Table Test Complete.

Set by the ALC to indicate that the ALC’s internal RSD

memory test has completed.

PARERR: .

DTCOMGFCC

CEC: Congestion Experienced Change. Circuit Changed in register 13

GFCC: GFC Field Change (UNI Mode only). Circuit changed in register 13

Parity Error on DMA Interface

In addition this register, when read indictes the revision of the MB86687A. This is set to

0xXX01h.

BUSERR Set by the ALC in Fast Mode when host activates the DTACK/READY

input to indicate a bus error

These three fields are used only during the manufacturing phase.

Edition 2.0MB86687A APPENDICES

Fig. 47 – REGISTERS 20 to 31

Registers 20 to 31 – Transmit Queue Service Rate Registers

SC0SC1XXXXX

SR0SR1SR2SR3SR4SR5SR6SR7

SCP

Note: The maximum value which SR0 – SR7 can take is given by:

Where L is cell width in nano-seconds, SCP the selected counter

period integer multiple of the system clock period.

This maximum value corresponds to a single active Virtual Circuit

using the total link capacity.

D15

The Service Rate counters are used to implement leaky bucket traffic management on

each of the ALC’s 12 peak rate queues. Bits SR7 – SR0 are used to specify the rate at

which tokens are removed from the leaky buckets of each circuit associated with that

queue. In single leaky bucket mode this value determines the rate of cell transmission

during the initial burst. In double leaky bucket mode this value determines the rate of cell

transmission in each burst.

The counter value specified is decremented using a scaled version of the input

transmission clock (TCLK). TCLK is divided by the scaling factor specified in bits SC0

and SC1 of this register as shown below. Each time the counter reaches zero it is

reloaded to its initial value.

SC1 SC0 Scaling Factor

0 0 4

0 1 16

1 0 64

1 1 256

MB86687A APPENDICESEdition 2.0

Fig. 48 – REGISTER 32

ENM2ENM1ENL3

ENAP

XX ENL1 ENL2

ENH4ENH3ENH2ENH1ENM4ENM3

ENL4

Servicing of each of the 12 available transmission descriptor queues can be enabled by

setting and disabled by clearing their respective peak cell transmission rate counter enables

as shown below. Also the total ALC peak and average rate counters can be individually

enabled by setting and disabled by clearing the ENAP and ENAA bits respectively.

Low Priority Transmit Queue Service Enables:

ENL1: Enable counter for low priority service queue 1

ENL2: Enable counter for low priority service queue 2

ENL3: Enable counter for low priority service queue 3

ENL4: Enable counter for low priority service queue 4

Medium Priority Transmit Queue Service Enables:

ENM1: Enable counter for medium priority service queue 1

ENM2: Enable counter for medium priority service queue 2

ENM3: Enable counter for medium priority service queue 3

ENM4: Enable counter for medium priority service queue 4

High Priority Transmit Queue Service Enables:

ENH1: Enable counter for high priority service queue 1

ENH2: Enable counter for high priority service queue 2

ENH3: Enable counter for high priority service queue 3

ENH4: Enable counter for high priority service queue 4

Total ALC Traffic Management Counter Enables:

ENAP: Enable counter for ALC peak transmission rate.

ENAA: Enable counter for ALC average transmission rate.

ENAA

D15

Edition 2.0MB86687A APPENDICES

Fig. 49 – REGISTER 33 AND 34

PS0PS1XXXXX

PR0PR1PR2PR3PR4PR5PR6PR7

AS0AS1XXXXXX

AR0AR1AR2AR3AR4AR5AR6AR7

This total ALC output peak rate counter is used to implement leaky bucket traffic

management on the ALC’s transmitted cell stream. Bits PR7 – PR0 are used to specify

the rate at which tokens are removed from the leaky bucket. In single leaky bucket

mode this value determines the rate of cell transmission during the initial burst. In double

leaky bucket mode this value determines the rate of cell transmission in each burst.

The counter value specified is decremented using a scaled version of the input

transmission clock (TCLK). TCLK is divided by the scaling factor specified in bits PS0

and PS1 of this register as shown below. Each time the counter reaches zero it is

reloaded to its initial value.

PS1 PS0 Scaling Factor

0 0 1

0 1 2

1 0 4

1 1 8

This total ALC output average rate counter is used to implement leaky bucket traffic

management on the ALC’s transmitted cell stream. Bits AR7 – AR0 are used to specify

the rate at which tokens are removed from the leaky bucket. In single leaky bucket

mode this value determines the rate of cell transmission during the initial burst. In double

leaky bucket mode this value determines the length of time that the output cell stream is

idle between bursts.

The counter value specified is decremented using a scaled version of the input

transmission clock (TCLK). TCLK is divided by the scaling factor specified in bits AS0

and AS1 of this register as shown below. Each time the counter reaches zero it is

reloaded to its initial value.

AS1 AS0 Scaling Factor

0 0 1

0 1 2

1 0 4

1 1 8

D15

MB86687A APPENDICESEdition 2.0

Fig. 50 – REGISTER 35

XXXXXX

LBC0LBC1LBC2LBC3LBC4LBC5LBC6LBC7

Note:

If the resulting value of M is not a positive integer then in the single leaky bucket

method it should be rounded DOWN to the nearest positive integer and in the

double leaky bucket method it should be rounded UP to the next positive integer.

In this case a minimum allowed value of B is specified for each selected U.

U = 0.875 minimum B = 9.

U = 0.75 minimum B = 5

U = 0.625 minimum B = 4

All other values of U minimum B = 3.

D15

This register specifies the number of tokens held in the ALC total traffic

management leaky bucket. This parameter together with the ALC peak transmission

rate register setting and the ALC average transmission rate register setting

determines the total cell transmission rate at the ALC’s output.

This capacity value can be used together with the ALC peak cell rate and average

cell rate to calculate the maximum burst length of transmitted cells generated by the

ALC.

For Single Leaky Bucket Mode:

M = (B–1) x (1–U) Note that M  0

For Double Leaky Bucket Mode:

M = B x (1–U)

B = maximum number of cells in the output burst.

M = leaky bucket capacity as specified in LBC7 – LBC0

U = utilisation = average cell output rate / peak cell output rate

= (AR7 – AR0) / (PR7 – PR0)

Edition 2.0MB86687A APPENDICES

RQA0RQA1RQA2RQA3RQA4RQA5RQA6RQA7

Fig. 51 – REGISTERS 40 and 41

NAM SIFC ADCCK ARXCLK DMID X RQA9 RQA8

D15

This register contains the upper10 bits of both the Recieve Buffer Free Queue and

Buffer Ready Queue addresses. This base address is concatenated with the start or

end address (shifted left by 1 bit) or with the write or read pointers (shifted left by 1

bit) to obtain the upper 23 bits of the system or dual port SAR memory address of the

Pending or Release Queue entry. Address bit 0 is always set to 0 by the ALC.

NAM: Non Assured Mode – If set the ALC receive will dma out to

system memory the AAL5 SAR payload within the trailer

cell even if the packet CRC32 check fails.

SIFC: Streaming Interrupt First Cell – If set, after writing out the

payload from the first cell of a packet the ALC will write the

receive descriptor to the RBRQ and generate an RRW interrupt.

ADCCK: Set if microprocessor reads are asynchronous to DCCK.

ARXCLK: Set if microprocessor reads are asynchronous to RXCLK.

DMID: For AAL3/4 receive traffic. If set, the ALC will not discard

cells with non–zero MID fields.

RBFS8RBFS9RBFS10RBFS11RBFS12XXX

RBFS0RBFS1RBFS2RBFS3RBFS4RBFS5RBFS6RBFS7 D0

D15

This offset address is shifted left by one bit and concatenated to the Recieve Queue

Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of

the Recieve Pending Queue start address. This start address indicates the beginning

of the Recieve Pending Queue space which is used to pass recieve request buffer

descriptor addresses from the Host to the ALC. Address bit 0 is always be set to 0 by

the ALC.

MB86687A APPENDICESEdition 2.0

Fig. 52 – REGISTER 42, 43 AND 44

RBFE0RBFE1RBFE2RBFE3RBFE4RBFE5RBFE6RBFE7

RBFE8RBFE9RBFE10RBFE11RBFE12XXX

RBFW8RBFW9RBFW10RBFW11RBFW12FULLEMPTYINCWRAP

RBFW0RBFW1RBFW2RBFW3RBFW4RBFW5RBFW6RBFW7

D15

This offset address is shifted left by one bit and concatenated to the Recieve Queue

Base Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of

the Recieve Pending Queue end address. This end address indicates the finish of

the Receive Pending Queue space which is used to pass Receive request buffer

descriptor addresses from the Host to the ALC. Address bit 0 is always set to 0 by

the ALC.

This offset address is shifted left by 1 bit and concatenated to the Receive Queue Base

Address Register contents (shifted left by 14 bits) to obtain the upper 23 bits of the

Receive Pending Queue write pointer. The Host uses this pointer when entering Receive

requests by writing a receive descriptor reference address to the Receive pending queue.

Address bit 0 is always be set to 0 by the ALC.

INCWRAP – When writing to the host–controlled queue registers, if the most

significant bit of the control data bus is set, the ALC will

automatically increment its internal copy of the pointer being

written to regardless of the pointer value specified on the data bus.

EMPTY – If this bit is set, it indicates that the ALC’s pointer for the queue is

at the same value as the host pointer’s value returned by the read

and that the queue is empty.

FULL – If this bit is set, it indicates that the host pointer and ALC pointer

values are the same and that the queue is full.

RBFR0RBFR1RBFR2RBFR3RBFR4RBFR5RBFR6RBFR7

RBFR8RBFR9RBFR10RBFR11RBFR12ASYNCIXX

D15

This offset address is shifted left by 1 bit and concatenated to the Receive Queue

Base Address Register contents ( shifted left by 14 bits ) to obtain the upper 23 bits

of the Receive Pending Queue read pointer. The ALC uses this pointer when

retrieving transmit requests by reading a receive descriptor reference address from

the Receive Pending Queue. Address bit 0 is always set to 0 by the ALC.

Please refer to Register 6 on page 58 for a description of ASYNCI.

Edition 2.0MB86687A APPENDICES

Fig. 53 – REGISTER 45, 46 AND 47

RBRE0RBRE1RBRE2RBRE3RBRE4RBRE5RBRE6RBRE7

RBRE8RBRE9RBRE10RBRE11RBRE12XXX

D15

This offset address shifted left by 1 bit is concatenated to the Receive Queue Base

Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the

Receive Release Queue end address. This end address indicates the finish of the

Receive Release Queue space used by the ALC to indicate the availability of free

Receive descriptors to the host. Address 0 is always set to 0.

RBRS8RBRS9RBRS10RBRS11RBRS12XXX

RBRS0RBRS1RBRS2RBRS3RBRS4RBRS5RBRS6RBRS7 D0

D15

This offset address shifted left by 1 bit is concatenated to the Receive Queue Base

Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the

Receive Release Queue start address. This start address indicates the beginning of

the Receive Release Queue space used by the ALC to indicate the availability of free

Receive descriptors to the host. Address 0 is always set to 0.

This base address (shifted left by 8 bits) is added to the 12 bit receive descriptor address

(shifted left by 5 bits) from the Receive Buffer Ready Queue or Receive Buffer Free queue

entry to obtain the full 24 bit address of the receive descriptors.

D15

RDA0

RDA8

RDA1

RDA9

RDA2

RDA10

RDA3

RDA11

RDA4

RDA12

RDA5

RDA13

RDA6

RDA14

RDA7

RDA15

MB86687A APPENDICESEdition 2.0

Fig. 54 – REGISTER 48, 49 AND 50

RBRW8

RBRR0

RBRW9RBRW10RBRW11RBRW12ASYNCIXX

RBRW0RBRW1RBRW2RBRW3RBRW4RBRW5RBRW6RBRW7

RBRR1RBRR2RBRR3RBRR4RBRR5RBRR6RBRR7

RBRR8RBRR9RBRR10RBRR11RBRR12FULLEMPTYINCWRAP

This offset address is shifted left by 1 bit and concatenated to the Receive Queue Base

Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of the

Receive Buffer Ready Queue write pointer. The ALC uses this pointer to write the

address of the Receive Descriptor for a received packet which has been reassembled

and placed in the receive buffer. Address bit 0 is always set to 0.

Please refer to Register 6 on page 58 for a description of ASYNCI.

This offset address is shifted left by 1 bit and concatenated to the Receive Queue

Base Address Register contents (shifted left by 14 bits ) to obtain the upper 23 bits of

the Receive Buffer Ready Queue read pointer. The Host uses this pointer to read the

address of the Receive Descriptor for a received packet which has been reassembled

and placed in the receive buffer. Address bit 0 is always set to 0.

DPC0DPC1DPC2DPC3DPC4DPC5DPC6DPC7

DPC8DPC9DPC10DPC11DPC12DPC13DPC14ASYNCI

This counter is incremented each time a received packet is lost due to no receive

buffers being available to start reassembly of the incoming data.

N.B. This register is not cleared when read unlike previous revisions of the ALC.

Please refer to Register 6 on page 58 for a description of ASYNCI.

D15

Edition 2.0MB86687A APPENDICES

Fig. 55 – REGISTERS 51 AND 52

BTC0

BTC1BTC2BTC3BTC4BTC5BTC6BTC7

BTC8BTC9BTC10BTC11BTC12BTC13BTC14BTC15

BTI8BTI9BTI10BTI11BTI12BTI13BTI14BTI15

The value in this register represents the number of DCCK clock periods required to

increment the receive buffer ageing time base counter. this value is used to pre scale

the ALC input DCCK clock before clocking the ALC’s time base counter. The time base

counter is used to check for receive buffer time out conditions.

The value written to this register defines the maximum time period allowed between the

arrival of a incoming packet and the host servicing the receive buffer.

If the time required by the host to service received packets exceeds this value then the

Received Buffer Ready Queue Status code of 1100b indicating receive buffer timeout

condition is written to the Receive Buffer Ready Queue entry corresponding to that

channel. The ALC’s time base counter is incremented using the DCCK clock pre-scaled

by the value in the Receive Buffer Time Out Counter Period register as described

above.

BTI0BTI1BTI2BTI3BTI4BTI5BTI6BTI7

D15

MB86687A APPENDICESEdition 2.0

DHR0DHR1DHR2DHR3DHR4DHR5DHR6DHR7

DHR8DHR9DHR10DHR11DHR12DHR13DHR14DHR15

This register contains the maximum number of bytes of incoming packet data that can

be received by the ALC. If the length of the received packet exceeds this number then

the ALC will deliver the packet but drop the cells beyond the level programmed.

When the ALC receives an incoming packet while only a single location is available in

the Receive Buffer Ready Queue, writing the Receive Buffer entry corresponding to this

packet will cause the generation of the Receive Buffer Ready Queue Full Interrupt . If a

further packet is received after this interrupt but before the host has serviced the

Receive Buffer Ready Queue then no Receive Buffer Ready queue space is available to

hold the packet received indication. In this case the ALC instead writes the Receive

Buffer Ready Queue entry to this Receive Buffer Ready Data Hold Register and

generates the Receive Buffer Ready Queue Write Fail interrupt. Note that if additional

packets are received the value in this register will be overwritten with the most recently

received packet’s Receive Buffer Ready Queue entry data.

D15

MPL0

MPL8

MPL1

MPL9

MPL2

MPL10

MPL3

MPL11

MPL4

MPL12

MPL5

MPL13

MPL6

MPL14

MPL7

MPL15

Fig. 56 – REGISTER 53 AND 54

Edition 2.0MB86687A APPENDICES

Fig. 57 – REGISTER 55 AND 56

AF9AF15

Address Filter These bits, together with AF17 and AF16 in Register 16, are used

as a filter for those address bits not covered in the 10 bits of the

ALC mapped address.

D15 AF14 AF13 AF12 AF11 AF10 AF8

AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0

This counter value is incremented each time a received cell is dropped by the ALC

due to:

1) Cell received for a packet which the receive has previously aborted due to:

Buffer overflow

No buffers available

No chaining buffers available

Buffer time out

Maximum packet length exceeded

2) EOM/COM received with no BOM (for AAL3/4)

3) CRC10 error (with RID=0 CR17, VCI used for addressing) (for AAL3/4)

4) Non–zero MID (with RID=0 CR17, VCI used for addressing and DMID=0)

(for AAL3/4)

N.B. This register is not cleared when read unlike previous revisions of the ALC.

Please refer to Register 6 on page 58 for a description of ASYNCI.

D15

DCC0

DCC8

DCC1

DCC9

DCC2

DCC10

DCC3

DCC11

DCC4

DCC12

DCC5

DCC13

DCC6

DCC14

DCC7

ASYNCI

MB86687A APPENDICESEdition 2.0

Fig. 58 – REGISTER 57 AND 58

DSC8DSC9DSC10DSC11

DCRD

RIP

ACT

DSC0DSC1DSC2DSC3DSC4DSC5

DSC6DSC7

This register is used in conjunction with the Host Receive Descriptor / Status Table

Access Register by the host to write Receive Descriptor / Status Table entries.

The host normally accesses this table only during initialisation.

DSC0 – DSC11: Receive descriptor pointer for this Receive Circuit Reference.

DP: Receive descriptor pointer in DSC0 – DSC11 above is valid.

RIP: Set Receive in progress on the Receive Circuit Reference

corresponding to this entry.

ACT: Activate monitoring of the Receive Circuit Reference corresponding

to this entry

DCRD: Discard received packets on the channel referenced by this entry.

DSC8DSC9DSC10DSC11

DCRD

RIP

ACT

DSC0DSC1DSC2DSC3DSC4DSC5

DSC6DSC7

D15

This register is used by the host to read the Receive Descriptor / Status Table.

This table specifies the location and status of specific receive channel descriptors.

DSC0 – DSC11: Receive descriptor pointer for this Receive Circuit Reference.

DP: Receive descriptor pointer in DSC0 – DSC11 above is valid.

RIP: Reception in progress on the Receive Circuit Reference

corresponding to this entry.

ACT: Active monitoring of the Receive Circuit Reference corresponding

to this entry.

DCRD: Discard in progress on the channel referenced by this entry.

Edition 2.0MB86687A APPENDICES

Fig. 59 – REGISTER 59

RESRESAAL TYP1AAL TYP0HOSTR RD/WR

This register is used, together with registers 57 and 58 to gain read and write access to

the ALC’s internal Receive Descriptor / Status Table. The tables need to be accessed

by the host for initialization, scatter/gather mode and emergency buffer recovery.

When the Host Access Request (HOSTR) bit is set and the read/write control (RD/WR)

bit is SET, the contents of register 58 and the AAL Type bits are written to the table

entry at the address indicated by RCR 0:9. The ALC will generate a TAC interrupt to

indicate that the write operation is complete.

When the Host Access Request (HOSTR) bit is set and the read/write control bit

(RD/WR) is CLEARED, the ALC is configured to read the internal Receive

Descriptor / Status Table entry at the address indicated by RCR 0:9. The ALC will

generate a TAC interrupt to indicate that the read operation is complete. At this time

D15

RCR0 –RCR9: This is the Table address Receive Circuit Reference.

AAL TYP: 00 AAL3/4

01 Transparent Mode

10 Transparent Cell Mode

11 AAL5.

HOSTR: Set to 1: Host Access Requested

Cleared to 0: Host Access Completed.

RD/WR: Set to 1: Write Request

Cleared to 0: Read Request.

RCR9 RCR8

RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0

MB86687A APPENDICESEdition 2.0

C. AC TIMINGS

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Setup time of TDI TDI 1 ns

Hold time of TDI TDI 2 ns

TDO delay TDO 5 13 ns

TMS setup TMS 4 ns

TMS hold TMS 2 ns

Table 3 – JTAG Interface Timing

Fig. 60 – System Clock Timing

tDCKH tDCKL

tDCLK

DCCK

RESET

tRST

Fig. 61 – Reset Timing

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Clock High Time DCCK tDCKH 13 ns

Clock Low Time DCCK tDCKL 15 ns

Clock Period DCCK tDCLK 30* ns

Reset Pulse Width RESET tRST 10 tDCLK ns

Table 4 – Miscellaneous – AC Timing Parameters

* Note: When the device is configured for Single cycle operation with 0 wait states

the clock period is restricted to 40ns

Note: On the following pages the following notation is used:

RMOD=0/1 means normal/extended read mode – CR15 RMOD bit

WMOD=0/1 means normal/extended write mode – CR15 WMOD bit

ASYNC/SYNC means asynchronous/synchronous DMA interface – CR15 SYN bit

Edition 2.0MB86687A APPENDICES

tTCKH

tTCKL

tTCLK

TXCLK

RXCLK

tRCKH

tRCKL

tRCLK

Fig. 62 – Cell Stream Clock Timing

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Transmit Clock High Time TXCLK tTCKH 18 ns

Transmit Clock Low Time TXCLK tTCKL 18 ns

Transmit Clock Period TXCLK tTCLK 40* ns

Receive Clock High Time RXCLK tRCKH 16 ns

Receive Clock Low Time RXCLK tRCKL 17 ns

Receive Clock Period RXCLK tRCLK 40* ns

Table 5 – Cell Stream Interface clocks – AC Timing Parameters

* Note: In Fujitsu Cell Stream Mode the clock period is restricted to 50ns.

* Note: The period of TXCLK and RXCLK must be greater or equal to the period of

DCCK.

MB86687A APPENDICESEdition 2.0

TXCLK

TXD0–7 Output Data Byte 1 Output Data Byte 2

tOC

TXSOC

Output Data Byte 3

Fig. 63 – Cell Stream Interface Transmit Port (Fujitsu Mode) Timing

tOCI

Fig. 64 – Cell Stream Interface Receive Port (Fujitsu Mode) Timing

RXCLK

RXD0–7 Input Data Input Data

tDS tDH

RXSOC

RXEN

tOC tOC

Input Data Input Data

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

TXSOC, TXD Active Delay TXCLK tOC 10 20 ns

TXD Inactive Delay TXCLK tOCI 5ns

RXSOC, RXD Setup Time RXCLK tDS 0ns

RXSOC, RXD Hold Time RXCLK tDH 6ns

RXEN Delay RXCLK tOC 14 23 ns

Table 6 – Cell Stream Interface Fujitsu Mode – AC Timing Parameters

Edition 2.0MB86687A APPENDICES

Fig. 65 – Cell Stream Interface Transmit Port (Utopia mode) Timing

TXFULL

tDH

tOC

TXCLK

TXD0–7

TXSOC

TXEN

tDS

tOC tOCI

tOC

Fig. 66 – Cell Stream Interface Receive Port (Utopia mode) Timing

RXEMPTY

tDH

tOC

RXCLK

RXD0–7

tDS tDH

RXSOC

RXEN

tDS

tOC

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

TXSOC, TXD, TXEN Delay TXCLK tOC 822 ns

TXD Inactive Delay TXCLK tOC 5ns

TXFULL Setup Time TXCLK tDS 2ns

TXFULL Hold Time TXCLK tDH 2ns

RXSOC, RXD, RXEMPTY Setup RXCLK tDS 0ns

RXSOC, RXD, RXEMPTY Hold RXCLK tDH 6ns

RXEN Delay RXCLK tOC 15 28 ns

Table 7 – Cell Stream Interface UTOPIA Mode – AC Timing Parameters

MB86687A APPENDICESEdition 2.0

Fig. 67 – CSI Token Transmit and Receive Timing

tOC

ÌÌ

TOUT

Token Transmit

tDS tDH

TIN

TXCLK

Token Receive

tOC

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

TIN Setup Time TXCLK tDS 0ns

TIN Hold Time TXCLK tDH 5ns

TOUT Delay TXCLK tOC 11 20 ns

Table 8 – Cell Stream Interface Token Passing – AC Timing Parameters

Edition 2.0MB86687A APPENDICES

Valid Address

ÌÌ

Fig. 68 – Microprocessor Interface – Read Timing

A1–A6

Valid Data

D0–D15

tAHR

tARD

tRDD tDRD

ÑÑÑ

tRDCS

ÑÑÑ

tCSRD

ÌÌ

Valid Address

A1–A6

Valid Data

D0–D15

tDH

tDS

tAWR

tWRW

tAHW

ÑÑÑ

tWRCS

Fig. 69 – Microprocessor Interface – Write Timing

ÑÑÑ

tCSWR

MB86687A APPENDICESEdition 2.0

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Address Valid to Read

Active RD tARD 0ns

CS Valid to Read Active RD tCSRD 0ns

Read Active to Valid Data RD tRDD 19 36 ns

Read Inactive to Invalid Data RD tDRD 5ns

Read Active to Invalid

Address RD tAHR 6ns

Read Inactive to CS

Inactive RD tRDCS 0ns

Address Active to Write

Active WR tAWR 0ns

CS Valid to Write Active WR tCSWR 0 ns

Write Pulse Width WR tWRW 5 ns

Data Setup Time WR tDS 5ns

Data Hold Time WR tDH 1ns

Write Active to Invalid

Address WR tAHW 6ns

Write Inactive to CS

Inactive WR tWRCS 0ns

Table 9 – Microprocessor Interface – AC Timing

Edition 2.0MB86687A APPENDICES

tWWD

ÌÌ

Fig. 70 – Microprocessor Interface – Write to Write Timing

Fig. 71 – Microprocessor Interface – Interrupt Timing

DCCK

IRQ

tIRQA tIRQI

tWRIRQI

tIRQDEL

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Write to Write Delay – DCCK WR tWWD 4DCCK ns

Write to Write Delay – TXCLK WR tWWT 4TXCLK* ns

IRQ Active Delay IRQ tIRQA 916 ns

WR Inactive to IRQ Inactive WR IRQ tWRIRQI 3DCCK 4DCCK ns

IRQ Inactive Delay IRQ tIRQI 40 ns

IRQ Inactive to Active IRQ tIRQDEL 2DCCK ns

Table 10 – Microprocessor Interface – AC Timing

*Note: See Fig. 30 – ALC Register Map, registers marked (T) denotes TXCLK write

recovery.

MB86687A APPENDICESEdition 2.0

Fig. 72 – Microprocessor Interface – Intel DMA Access Timing (SYNC)

HOLD

HLDA

A2–A23

BE0–3

RD & WR u processor u processor

DCLK

tHOLDA

tHLDAS

tADDRAZ tADDRIZ

tHOLDI

tHLDAH

BGACK

ALC bus valid

Fig. 73 – Microprocessor Interface – Intel DMA Access Timing (ASYNC)

HOLD

HLDA

A2–A23

BE0–3

RD & WR u processor u processor

DCLK

tHOLDA

tHLDAS

tADDRAZ tADDRIZ

tHOLDI

tHLDAH

BGACK

ALC bus valid

Edition 2.0MB86687A APPENDICES

Fig. 74 – Microprocessor Interface – Intel DMA Access Control Override Timing

ALC bus valid

tHLDAH

tHLDAS tHOLDI

tHOLDA

HOLD

HLDA

A2–A23

BE0–3

RD & WR u processor

DCLK

tHOLDA

tHLDAS

tADDRAZ

BGACK tADDRIZ

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

HOLD Active Delay HOLD tHOLDA 814 ns

HOLD Inactive Delay – ASYNC HOLD tHOLDI 75 ns

HOLD Inactive Delay –SYNC HOLD tHOLDI 10 22 ns

Setup Time of HLDA Active –

ASYNC HLDA tHLDAS 1 ns

Setup Time of HLDA Active –

SYNC HLDA tHLDAS 7 ns

Hold Time of HLDA Invalid –

ASYNC HLDA tHLDAH 1 ns

Hold Time of HLDA Invalid –

SYNC HLDA tHLDAH 2 ns

ALC Bus Active Delay A2–A23,

BE3–0,

MRD,

MWR,

tADDRAZ 516 ns

ALC Bus Inactive Delay A2–A23,

BE3–0,

MRD,

MWR

tADDRIZ 75 ns

Table 11 – Microprocessor Interface – Intel DMA Access AC Timing

MB86687A APPENDICESEdition 2.0

Fig. 75 – Microprocessor Interface – Motorola DMA Access Timing (SYNC)

DCLK

u processor

ALC bus valid

tBRA

tBGS

tADDRA

tBRI

A2–A23,

SIZ0–1,

DS, AS

& R/W

BGACK

tADDRIZ

tBGH

u processor

Fig. 76 – Microprocessor Interface – Motorola DMA Access Timing (ASYNC)

DCLK

u processor

ALC bus valid

tBRA

tBGS

tADDRA

tBRI

A2–A23,

SIZ0–1,

DS, AS

& R/W

BGACK

tADDRIZ

tBGH

u processor

Edition 2.0MB86687A APPENDICES

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

BR Active Delay BR tBRA 814 ns

BR Inactive Delay – ASYNC BR tBRI 75 ns

BR Inactive Delay – SYNC BR tBRI 10 22 ns

Setup Time of BG, AS & BGACK

Active – ASYNC BG tBGS 1ns

Setup Time of BG, AS & BGACK

Active – SYNC BG tBGS 8ns

Hold Time of BG, AS & BGACK

Invalid – ASYNC BG tBGH 1ns

Hold Time of BG, AS & BGACK

Invalid – SYNC BG tBGH 0ns

ALC Bus Active Delay A2–A23,

SIZ0–1,

DS, AS,

R/W

tADDRAZ 516 ns

ALC Bus Inactive Delay A2–A23,

SIZ0–1,

DS, AS,

R/W

tADDRIZ 75 ns

Table 12 – Microprocessor Interface – Motorola DMA Access AC Timing

MB86687A APPENDICESEdition 2.0

DCCK

DATA

Fig. 77 – DPR / DMA Interface – Intel Read Cycle (SYNC)

A2–A23

BE0 BE1

BE2 BE3

READY

tADDRA tRDA

tRDYH

tRDYS

tDATS

tDATH

tRDI

tADDRI

tRDW

D0–D31

**CS

(TOCS etc)

tCSA tCSI

DCCK

DATA

Fig. 78 – DPR / DMA Interface – Intel Read Cycle (ASYNC)

A2–A23

BE0 BE1

BE2 BE3

READY

tADDRA tRDA

tRDYS tRDYH

tDATS tDATH

tRDI

tADDRI

tRDW

D0–D31

**CS

(TOCS etc)

tCSA tCSI

Edition 2.0MB86687A APPENDICES

Fig. 79 – DPR / DMA Interface – Intel Write Cycle (SYNC)

DCCK

DATA

A2–A23

BE0 BE1

BE2 BE3

READY

tADDRA

tWRA

tDATA

tWRW

tADDRI

tWRI

tDATI

tRDYH

tRDYS

D0–D31

Fig. 80 – DPR / DMA Interface – Intel Write Cycle (ASYNC)

DCCK

DATA

A2–A23

BE0 BE1

BE2 BE3

READY

tADDRA

tWRA

tDATA

tWRW

tADDRI

tWRI

tDATI

tRDYH

tRDYS

D0–D31

MB86687A APPENDICESEdition 2.0

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Address Active Delay A2–A23 tADDRA 15 28 ns

BE Active Delay – non burst BE0–BE3 tADDRA 13 22 ns

BE Active Delay – burst BE0–BE3 tADDRA 15 24 ns

Address BE Inactive Delay A2–A23 tADDRI 5ns

Read Active Delay RD tRDA 10 17 ns

Read Inactive Delay – RMOD=0 RD tRDI 916 ns

Read Inactive Delay – RMOD=1 RD tRDI 916 ns

Setup Time of Ready – ASYNC READY tRDYS 1ns

Setup Time of Ready – SYNC READY tRDYS 2ns

Hold Time of Ready – ASYNC READY tRDYH 2ns

Hold Time of Ready – SYNC READY tRDYH 1ns

Read Active Width (RMOD=0) RD tRDW tDCCK – 1ns ns

Setup Time of Data – RMOD=0 D0–D31 tDATS 0 ns

Setup Time of Data – RMOD=1 D0–D31 tDATS 6 ns

Hold Time of Data – RMOD=0 D0–D31 tDATH 10 ns

Hold Time of Data – RMOD=1 D0–D31 tDATH 7 ns

Write Active Delay WR tWRA 10 17 ns

Write Inactive Delay –

WMOD=0 WR tWRI 916 ns

Write Inactive Delay –

WMOD=1 WR tWRI 916 ns

Write Active Width (WMOD=0) WR tWRW tDCCK – 1ns ns

Write Data Active Delay D0–D31 tDATA 13 22 ns

Write Data Inactive delay D0–D31 tDATI 5 ns

Parity Active delay PRTY 0–3 15 24 ns

Cycle Start Active delay **CS tCSA 11 20 ns

Cycle State Inactive delay **CS tCSI 917 ns

Table 13 – DPR / DMA Interface – Intel Cycle AC Timing

Edition 2.0MB86687A APPENDICES

DCCK

DATA

Fig. 81 – DPR / DMA Interface – Motorola Read Cycle (SYNC)

A0–A23

DTACK

D0–D31

SIZ0, SIZ1

tADDRA tASDSA

tDTKS

tASDSI

tADDRI

tDATS tDATH

tDTKH

tASDSW

DCCK

DATA

Fig. 82 – DPR / DMA Interface – Motorola Read Cycle (ASYNC)

A0–A23

DTACK

D0–D31

SIZ0, SIZ1

tADDRA tASDSA

tDTKS

tASDSI

tADDRI

tDATS tDATH

tDTKH

tASDSW

MB86687A APPENDICESEdition 2.0

DCCK

R / W

DATA

A0–A23

SIZ0, SIZ1

DTACK

D0–D31

tADDRA

tASA

tDATA

tDSA

tDSW

tASW

tDTKS

tDTKH

tASDSI

tDATI

tADDRI

Fig. 83 – DPR / DMA Interface – Motorola Write Cycle (SYNC)

Fig. 84 – DPR / DMA Interface – Motorola Write Cycle (ASYNC)

DCCK

R / W

DATA

A0–A23

SIZ0, SIZ1

DTACK

D0–D31

tADDRA

tASA

tDATA

tDSA

tDSW

tASW

tDTKS tDTKH

tASDSI

tDATI

tADDRI

Edition 2.0MB86687A APPENDICES

100

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Address Active delay A2–A23 tADDRA 15 28 ns

SIZ0/1 Active Delay – non burst SIZ0/1 tADDRA 13 22 ns

SIZ0/1 Active Delay – burst SIZ0/1 tADDRA 15 24 ns

Address SIZ0/1 Inactive Delay A2–A23 tADDRI 5ns

R/W Delay R/W 15 24 ns

Read AS Active Delay AS tASDSA 11 17 ns

Read DS Active Delay DS tASDSA 9 16 ns

Read AS Inactive Delay –

RMOD=0 AS tASDSI 10 17 ns

Read DS Inactive Delay –

RMOD=0 DS tASDSI 9 16 ns

Read AS Inactive Delay –

RMOD=1 AS 8 14 ns

Setup Time of DTACK –

ASYNC DTACK tDTKS 1 ns

Setup Time of DTACK – SYNC DTACK tDTKS 2 ns

Hold Time of DTACK – ASYNC DTACK tDTKH 2 ns

Hold Time of DTACK – SYNC DTACK tDTKH 1 ns

Read DS Active Width DS tDSW tDCCK – 1ns ns

Setup Time of Data – RMOD=0 D0–D31 tDATS 0 ns

Setup Time of Data – RMOD=1 D0–D31 6 ns

Hold Time of Data – RMOD=0 D0–D31 tDATH 10 ns

Hold Time of Data – RMOD=1 D0–D31 7 ns

Write AS Active Delay AS tASA 11 17 ns

Write DS Active Delay DS tDSA 916 ns

Write AS Inactive Delay AS tASDSI 10 17 ns

Write DS Inactive Delay DS tASDSI 9 16 ns

Write AS Active Width AS tASW tDCCK – 1ns ns

Write DS Active Width DS tDSW 1/2 tDCCK –

1ns ns

Write Data Active Delay D0–D31 tDATA 13 22 ns

Write Data Inactive Delay D0–D31 tDATI 5 ns

Table 14 – DPR / DMA Interface – Motorola Cycle AC Timing

MB86687A APPENDICESEdition 2.0

101















 

Fig. 85 – Single Cycle Burst – Intel Extended Cycle (SBL=0, SYNC)

 

 



 

  

 

 



 

Fig. 86 – Single Cycle Burst – Intel Extended Cycle (SBL=0, ASYNC)















 

 

 







  

 

 



 

Edition 2.0MB86687A APPENDICES

102

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Address Active Delay A23–2 tADDRA 15 28 ns

Write/Read Active Delay W/R tADDRA 16 26 ns

BE Active Delay BE3–0 tADDRA 15 24 ns

Address BE Write/Read Inactive

Delay A23–2,

BE3–0 W/R tADDRI 5ns

ADS Active Delay ADS tADSA 13 22 ns

ADS Inactive Delay ADS tADSI 11 19 ns

BLAST Active Delay BLAST tBLSTA 17 29 ns

BLAST Inactive Delay BLAST tBLSTI 7 14 ns

Setup Time of Data (Data Burst no

parity) SRD31–0 tDATS 0 ns

Hold Time of Data SRD31–0 tDATH 7 ns

Write Active Delay1 SRD31–0 tDATA1 13 22 ns

Write Active Delay2 SRD31–0 tDATA2 17 28 ns

Write Inactive Delay SRD31–0 tDATI 5 ns

Setup Time of SYNC READY READY tSRDYS 2ns

Hold T ime of SYNC READY READY tSRDYH 1ns

Setup T ime of ASYNC READY READY tARDYS 1ns

Hold T ime of ASYNC READY READY tARDYH 2ns

Table 15 – Single Cycle Burst – Intel Extended Cycle Timing

MB86687A APPENDICESEdition 2.0

103

Fig. 87 – Single Cycle Burst – Motorola Extended Cycle (SBL=0, SYNC)















 

 







  

 

 





Fig. 88 – Single Cycle Burst – Motorola Extended Cycle (SBL=0, ASYNC)















 

 



 

  

 

 





Edition 2.0MB86687A APPENDICES

104

Parameter Signal Abbrev Values Units

(ns)

Min Typical Max (ns)

Address Active Delay A23–2 tADDRA 15 28 ns

R/W Active Delay R/W tADDRA 15 24 ns

SIZ0, SIZ1 Active Delay SIZ0, SIZ1 tADDRA 15 24 ns

Address BE Write/Read Inactive

Delay A23–2,

SIZ0, SIZ1,

W/R

tADDRI 5ns

TS Active Delay TS tTSA 13 22 ns

TS Inactive Delay TS tTSI 11 19 ns

TIP Active Delay TIP tTIPA 12 20 ns

TIP Inactive Delay TIP tTIPI 10 18 ns

Setup Time of Data (Data Burst no

parity) SRD31–0 tDATS 0 ns

Hold Time of Data SRD31–0 tDATH 7 ns

Write Active Delay1 SRD31–0 tDATA1 13 22 ns

Write Active Delay2 SRD31–0 tDATA2 17 28 ns

Write Inactive Delay SRD31–0 tDATI 5 ns

Setup Time of SYNC DTACK DTACK tSDTKS 2 ns

Hold Time of SYNC DTACK DTACK tSDTKH 1 ns

Setup Time of ASYNC DTACK DTACK tADTKS 1 ns

Hold Time of ASYNC DTACK DTACK tADTKH 2 ns

Table 16 – Single Cycle Burst – Motorola Extended Cycle Timing

MB86687A APPENDICESEdition 2.0

105

D. RATINGS

D.1 Absolute Maximum

Ratings

Rating Symbol Values Units

Min Max

Positive Supply Voltage +VDD –0.5 6.0 V

Input Voltage VDIN –0.5 +VDD + 0.5 V

Output Voltage VO1 –0.5 +VDD + 0.5 V

Input Current IMAX –10.0 125 

Storage Temperature TSTG –40 125 oC

NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as detailed in the operational sections of this datasheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

D.2 DC Characteristics

Parameter Symbol Pin Test Condition Value Unit

Min. Typ. Max.

Positive Supply Voltage VDD +4.75 +4.75 +5.0 +5.25 V

Positive Supply Current +IVS Static no load – – 100 mA

Input High Voltage (TTL) VIH 2.2 – +VDD V

Input Low Voltage (TTL) VIL 0 – 0.8 V

Input Leakage Current IL0<=VI<=+VDD –10 – 10 A

Pull–up Input Leakage Current ILUL2 0<=VI<=+VDD –190 – –38 A

Input Leakage Current ILZH1 0<=VI<=+VDD –10 – 10 A

Output Low Voltage VOL IOL=3.2mA VSS – 0.4 V

Output High Voltage VOH IOH=–2mA 4.2 – VDD V

Output Off Leakage Current ILO –10 – 10 mA

Input Pin Capacitance Cin – – 8 pF

Output Pin Capacitance Cout – – 16 pF

I/O Pin Capacitance Ci/o – – 21 pF

Loading capacitance Cl60 pF

Operating Temperature TA0 – +70 oC

Power Dissipation (operating) PO1000 mW

Edition 2.0MB86687A APPENDICES

106

E. JTAG

E.1 JTAG Cells

The Boundary Scan Register (BSR) consists of 123 registers, which form a serial shift

chip to finish at pin 24.

It should be noted that none of the internal D–types which form the BSR are reset, and

hence are initially undefined. A valid pattern needs to be shifted into the register prior

to any testing. However, while the JTAG TAP controller is reset, the I/O pins are

connected through to the system logic.

I / O Pin Type: I = Input

C = Clock input

O = Output

B = Bidirectional

T = Tristate

Iu = Input with pull-up resistor.

BSR Cell Type: BSI 1 allows capture of device input pin and control of logic

input pin.

BSI 3 allows capture of device input pin only.

BSO allows capture of logic output pin and control of device

output pin ( = BSI1 ).

BSOE allows control of tristate-able output pin

(preset–able).

BSDI allows control of bidirectional pin (= BSOE).

BSBI allows capture and control of bidirectional input and

output pin ( = BSI 1 + BSO ).

Control Group No.: Denotes a JTAG BSR cell which controls a (group of)

tristate-able output(s) or bidirectional pin(s).

Controlled Group No.: Denotes a JTAG BSR cell which connects to a tristate-able

output or bidirectional pin which is controlled by the JTAG

BSR cell numbered in the previous column.

MB86687A APPENDICESEdition 2.0

107

1 BSI1 Iu 83 TXDRV

2 BSOE 1

3 BSO 1 T 88 DS/BLAST/TIP

4 BSDI 2

5 & 6 BSBI 2 B 93 MRD / AS/ ASD

7 BSO 1 T 94 MWR / R/W R/W

8 BSOE 3

9 BSO 3 T 95 HOLD / BR

10 BSI1 I 98 HLDA / BG

11 BSDI 4

12 & 13 BSBI 4 B 99 BGACK

14 BSI1 I 100 DTACK / READY

15 BSI1 I 101 RESET

16 BSI1 I 102 CS

17 BSOE 5

18 BSO 5 T 103 IRQ

19 BSI1 I 104 RD

20 BSI1 I 105 WR

21 BSI1 I 106 A1

22 BSI1 I 108 A2

23 BSI1 I 109 A3

24 BSI1 I 110 A4

25 BSI1 I 111 A5

26 BSI1 I 112 A6

27 BSI1 I 113 TEST

28 BSDI 6

29 & 30 BSBI 6 B 115 DATA0

31 & 32 BSBI 6 B 116 DATA1

33 & 34 BSBI 6 B 117 DATA2

35 & 36 BSBI 6 B 118 DATA3

37 & 38 BSBI 6 B 121 DATA4

39 & 40 BSBI 6 B 122 DATA5

41 & 42 BSBI 6 B 123 DATA6

43 & 44 BSBI 6 B 125 DATA7

45 & 46 BSBI 6 B 126 DATA8

47 & 48 BSBI 6 B 127 DATA9

49 & 50 BSBI 6 B 128 DATA10

51 & 52 BSBI 6 B 133 DATA11

53 & 54 BSBI 6 B 134 DATA12

55 & 56 BSBI 6 B 135 DATA13

57 & 58 BSBI 6 B 136 DATA14

59 & 60 BSBI 6 B 138 DATA15

Edition 2.0MB86687A APPENDICES

108

61 BSI3 C 139 DCCK

62 BSO O 140 TOUT

63 BSI1 I 155 TIN

64 BSOE 7

65 BSDI 8

66 BSO 7 T 143 TXSOC

67 BSI3 C 144 TXCLK

68 BSO 7 T 145 TXD0

69 BSO 7 T 146 TXD1

70 BSO 7 T 148 TXD2

71 BSO 7 T 149 TXD3

72 BSO 7 T 150 TXD4

73 BSO 7 T 151 TXD5

74 BSO 7 T 152 TXD6

75 BSO 7 T 153 TXD7

76 BSO O 156 RXEN

77 BSI1 I 157 RXSOC

78 BSI3 C 158 RXCLK

79 BSI1 I 159 RXD0

80 BSI1 I 160 RXD1

81 BSI1 I 161 RXD2

82 BSI1 I 162 RXD3

83 BSI1 I 163 RXD4

84 BSI1 I 166 RXD5

85 BSI1 I 168 RXD6

86 BSI1 I 169 RXD7

87 BSI1 Iu 167 TXFULL

88 BSO 7 T 55 TXEN

89 BSI1 Iu 56 RXEMPTY

90 BSI1 Iu 57 CS / UT

91 BSO 1 T 89 BE0 / SRA0

92 BSO 1 T 90 BE1 / SRA1

93 BSO 1 T 91 BE2 / SIZ0

94 BSO 1 T 92 BE3 / SIZ1

95 BSO 1 T 87 SRA2

96 BSO 1 T 197 SRA3

97 BSO 1 T 199 SRA4

98 BSO 1 T 202 SRA5

99 BSO 1 T 203 SRA6

100 BSO 1 T 204 SRA7

MB86687A APPENDICESEdition 2.0

109

101 BSO 1 T 8 SRA8

102 BSO 1 T 9 SRA9

103 BSO 1 T 11 SRA10

104 BSO 1 T 12 SRA11

105 BSO 1 T 13 SRA12

106 BSO 1 T 37 SRA13

107 BSO 1 T 39 SRA14

108 BSO 1 T 40 SRA15

109 BSO 1 T 41 SRA16

110 BSO 1 T 59 SRA17

111 BSO 1 T 62 SRA18

112 BSO 1 T 63 SRA19

113 BSO 1 T 64 SRA20

114 BSO 1 T 66 SRA21

115 BSO 1 T 67 SRA22

116 BSO 1 T 68 SRA23

117 BSO O 44 TOCS

118 BSO O 45 TDCS

119 BSO O 46 ROCS

120 BSO O 47 RDCS

121 & 122 BSBI 8 B 29 PRTY0

123 & 124 BSBI 8 B 31 PRTY1

125 & 126 BSBI 8 B 32 PRTY2

127 & 128 BSBI 8 B 33 PRTY3

129 BSI1 Iu 35 SADRV

130 & 131 BSBI 8 B 170 SRD0

132 & 133 BSBI 8 B 172 SRD1

134 & 135 BSBI 8 B 173 SRD2

136 &137 BSBI 8 B 175 SRD3

138 & 139 BSBI 8 B 178 SRD4

140 & 141 BSBI 8 B 179 SRD5

142 & 143 BSBI 8 B 181 SRD6

144 & 145 BSBI 8 B 185 SRD7

146 & 147 BSBI 8 B 187 SRD8

148 & 149 BSBI 8 B 190 SRD9

150 & 151 BSBI 8 B 192 SRD10

Edition 2.0MB86687A APPENDICES

110

152 & 153 BSBI 8 B 193 SRD11

154 & 155 BSBI 8 B 195 SRD12

156 & 157 BSBI 8 B 196 SRD13

158 & 159 BSBI 8 B 205 SRD14

160 & 161 BSBI 8 B 206 SRD15

162 & 163 BSBI 8 B 207 SRD16

164 & 165 BSBI 8 B 208 SRD17

166 & 167 BSBI 8 B 1 SRD18

168 & 169 BSBI 8 B 2 SRD19

170 & 171 BSBI 8 B 4 SRD20

172 & 173 BSBI 8 B 5 SRD21

174 & 175 BSBI 8 B 6 SRD22

176 & 177 BSBI 8 B 7 SRD23

178 & 179 BSBI 8 B 14 SRD24

180 & 181 BSBI 8 B 16 SRD25

182 & 183 BSBI 8 B 17 SRD26

184 & 185 BSBI 8 B 18 SRD27

186 & 187 BSBI 8 B 20 SRD28

188 & 189 BSBI 8 B 21 SRD29

190 & 191 BSBI 8 B 22 SRD30

192 & 193 BSBI 8 B 24 SRD31

C 73 TCK

I 75 TMS

I 77 TDI

T 81 TDO

RXSOC

RXCLK

RXD0

RXD1

RXD2

VSS

RXD3

RXD4

RXD5

RXD6

RXD7

VDD

N/C

VSS

SRD0

SRD1

SRD2

SRD3

SRD4

SRD5

SRD6

SRD7

SRD8

SRD9

VSS

SRD10

SRD11

SRD12

SRD13

VDD

SRA3

SRA4

SRA5

SRA6

SRA7

VSS

SRD14

SRD15

SRD16

SRD17

IRQ

RESET

VSS

DTACK/READY/BERR

BGACK

HLDA/BG

HOLD/BR

MWR / R/W / R/W

VDD

MRD/AS/ADS/TS

BE3/SIZ1

BE2/SIZ0

BE1/SRA1

VSS

BE0/SRA0

DS/ TIP/ BLAST

SRA2

N/C

TXDRV

TDO

TDI

N/C

TMS

N/C

VSS

N/C

RESERVED

SRA23

SRA22

VDD

SRA21

SRA20

SRA19

SRA18

SRA17

VSS

SRD19

SRD20

SRD21

SRD22

SRD23

SRA8

SRA9

SRA10

SRA11

SRA12

SRD24

SRD25

SRD26

SRD27

VSS

SRD28

SRD29

SRD30

SRD31

PRTY0

PRTY1

TOCS

TDCS

ROCS

RDCS

N/C

SRA16

PRTY2

SADRV

N/C

VSS

SRA13

SRA14

SRA15

VDD

RXEN

TIN

TXD7

TXD6

TXD5

VSS

TXD4

TXD3

TXD2

TXD1

TXD0

VDD

TXCLK

TXSOC

TOUT

DCCK

VSS

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

VSS

DATA5

DATA4

DATA3

DATA2

VDD

DATA1

DATA0

TEST

ALC

PRTY3

126 52

105130156

157

182

208

Fig. 89 – ALC Pin Assignment

104

VDD

N/C

VSS

N/C

VDD

N/C

VDD

TXFULL

N/C

VSS

VDD

VSS

N/C

TCK

N/C

SRD18

N/C

VSS

CS/UT

N/C

TXEN

N/C

RXEMPTY

N/C

(T OP VIEW)

MB86687A

MB86687A APPENDICESEdition 2.0

111

F. PIN DESCRIPTION

F.1 Physical Pin Diagram

Edition 2.0MB86687A APPENDICES

112

F.2 Pin Description Table

Pin No. Pin Name Type Function

1 SRD18 I/O SAR Memory data bus bit 18

2 SRD19 I/O SAR Memory data bus bit 19

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

4 SRD20 I/O SAR Memory data bus bit 20

5 SRD21 I/O SAR Memory data bus bit 21

6 SRD22 I/O SAR Memory data bus bit 22

7 SRD23 I/O SAR Memory data bus bit 23

8 SRA8 O (3-state) SAR Memory address bit 8

9 SRA9 O (3-state) SAR Memory address bit 9

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

11 SRA10 O (3-state) SAR Memory address bit 10

12 SRA11 O (3-state) SAR Memory address bit 11

13 SRA12 O (3-state) SAR Memory address bit 12

14 SRD24 I/O SAR Memory data bus bit 24

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

16 SRD25 I/O SAR Memory data bus bit 25

17 SRD26 I/O SAR Memory data bus bit 26

18 SRD27 I/O SAR Memory data bus bit 27

19 N/C – Not Connected

20 SRD28 I/O SAR Memory data bus bit 28

21 SRD29 I/O SAR Memory data bus bit 29

22 SRD30 I/O SAR Memory data bus bit 30

23 N/C – Not Connected

24 SRD31 I/O SAR Memory data bus bit 31

25 N/C – Not Connected

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

28 N/C – Not Connected

29 PRTY0 I/O Parity for SRD7 – SRD0

30 N/C – Not Connected

31 PRTY1 I/O Parity for SRD15 – SRD8

32 PRTY2 I/O Parity for SRD23 – SRD16

33 PRTY3 I/O Parity for SRD31 – SRD24

34 N/C – Not Connected

35 SADRV I SAR Memory constant drive

36 N/C – Not Connected

37 SRA13 O (3-state) SAR Memory address bit 13

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

39 SRA14 O (3-state) SAR Memory address bit 14

40 SRA15 O (3-state) SAR Memory address bit 15

MB86687A APPENDICESEdition 2.0

113

Pin No. Pin Name Type Function

41 SRA16 O (3-state) SAR Memory address bit 16

42 N/C – Not Connected

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

44 TOCS O Transmit Overhead Start of Cycle

45 TDCS O Transmit Data Start of Cycle

46 ROCS O Receive Overhead Start of Cycle

47 RDCS O Receive Data Start of Cycle

48 N/C – Not Connected

49 N/C – Not Connected

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

51 N/C – Not Connected

52 N/C – Not Connected

53 N/C – Not Connected

54 N/C – Not Connected

55 TXEN O (high–Z) UTOPIA Transmit Enable

56 RXEMPTY I UTOPIA Receive Empty

57 CS/UT I Fujitsu Cell Stream / UTOPIA Select

58 N/C – Not Connected

59 SRA17 O (3-state) SAR Memory address bit 53

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

62 SRA18 O (3-state) SAR Memory address bit 18

63 SRA19 O (3-state) SAR Memory address bit 19

64 SRA20 O (3-state) SAR Memory address bit 20

65 N/C – Not Connected

66 SRA21 O (3-state) SAR Memory address bit 21

67 SRA22 O (3-state) SAR Memory address bit 22

68 SRA23 O (3-state) SAR Memory address bit 23

69 N/C – Not Connected

70 N/C – Reserved

71 N/C – Not Connected

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

73 TCK I JTAG Port Clock

74 N/C – Not Connected

75 TMS I JTAG Test Mode Select

76 N/C – Not Connected

77 TDI I JTAG Data Input

78 N/C – Not Connected

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

80 N/C – Not Connected

Edition 2.0MB86687A APPENDICES

114

Pin No. Pin Name Type Function

81 TDO O JTAG Data Output

82 N/C – Not Connected

83 TXDRV I Cell Stream Constant Drive

84 N/C – Not Connected

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

86 N/C – Not Connected

87 SRA2 O (high–Z) SAR Memory data bus bit 62

88 DS / BLAST / TIP O (3–state) Data Strobe / Burst Last / Transfer in Progress

89 BE0 O (3-state) SAR Memory BE0/SRA0

90 BE1 O (3-state) SAR Memory BE1/SRA1

91 BE2 O (3-state) SAR Memory BE2/SIZ0

92 BE3 O (3-state) SAR Memory BE3/SIZ1

93 MRD/AS/ ADS / TS I/O SAR Memory MRD/AS/ADS / TS

94 MWR/ R/W/ R/W O (3-state) SAR Memory MWR/R/W / R/W

95 HOLD/BR O (high-Z) SAR Memory HOLD/BR

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍ

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

98 HLDA/BG I SAR Memory HLDA/BG

99 BGACK O (high-Z) SAR Memory BGACK

100 DTACK/READY/BERR I SAR Memory DTACK/READY or Bus Error

101 RESET I ALC Master Reset input

102 CS I p Chip Select

103 IRQ O (high-Z) Interrupt Request

104 RD I p Read

105 WR I p Write

106 A1 I Microprocessor Address bit 1

107 VSS –

108 A2 I Microprocessor Address bit 2

109 A3 I Microprocessor Address bit 3

110 A4 I Microprocessor Address bit 4

111 A5 I Microprocessor Address bit 5

112 A6 I Microprocessor Address bit 6

113 TEST I Test Input – connect to Vss

114 VDD –

115 DATA0 I/O Microprocessor Data Bus bit 0

116 DATA1 I/O Microprocessor Data Bus bit 1

117 DATA2 I/O Microprocessor Data Bus bit 2

118 DATA3 I/O Microprocessor Data Bus bit 3

ÍÍÍÍÍ

119

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

120 N/C – Not Connected

MB86687A APPENDICESEdition 2.0

115

Pin No. Pin Name Type Function

121 DATA4 I/O Microprocessor Data Bus bit 4

122 DATA5 I/O Microprocessor Data Bus bit 5

123 DATA6 I/O Microprocessor Data Bus bit 6

124 N/C – Not Connected

125 DATA7 I/O Microprocessor Data Bus bit 7

126 DATA8 I/O Microprocessor Data Bus bit 8

127 DATA9 I/O Microprocessor Data Bus bit 9

128 DATA10 I/O Microprocessor Data Bus bit 10

129 N/C – Not Connected

ÍÍÍÍÍ

130

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍ

131

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

132 N/C – Not Connected

133 DATA11 I/O Microprocessor Data Bus bit 11

134 DATA12 I/O Microprocessor Data Bus bit 12

135 DATA13 I/O Microprocessor Data Bus bit 13

136 DATA14 I/O Microprocessor Data Bus bit 14

137 N/C – Not Connected

138 DATA15 I/O Microprocessor Data Bus bit 15

139 DCCK I DMA Cycle Clock input

140 TOUT O Token Out output

141 N/C – Not Connected

ÍÍÍÍÍ

142

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

143 TXSOC O (3-state) Cell Stream Interface Transmit Sync

144 TXCLK I Cell Stream Interface Transmit

145 TXD0 O (3-state) Cell Stream Interface Transmit data bit 0

146 TXD1 O (3-state) Cell Stream Interface Transmit data bit 1

147 VDD –

148 TXD2 O (3-state) Cell Stream Interface Transmit data bit 2

149 TXD3 O (3-state) Cell Stream Interface Transmit data bit 3

150 TXD4 O (3-state) Cell Stream Interface Transmit data bit 4

151 TXD5 O (3-state) Cell Stream Interface Transmit data bit 5

152 TXD6 O (3-state) Cell Stream Interface Transmit data bit 6

153 TXD7 O (3-state) Cell Stream Interface Transmit data bit 7

ÍÍÍÍÍ

154

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

155 TIN – Token In input

156 RXEN O Indicates ALC receive buffers full

157 RXSOC I Cell Stream Interface Receive Sync

158 RXCLK I Cell Stream Interface Receive

159 RXD0 I Cell Stream Interface Receive data bit 0

160 RXD1 I Cell Stream Interface Receive data bit 1

Edition 2.0MB86687A APPENDICES

116

Pin No. Pin Name Type Function

161 RXD2 I Cell Stream Interface Receive data bit 2

162 RXD3 I Cell Stream Interface Receive data bit 3

163 RXD4 I Cell Stream Interface Receive data bit 4

ÍÍÍÍÍ

164

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍ

165

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

166 RXD5 I Cell Stream Interface Receive data bit 5

167 TXFULL I UTOPIA Transmit Full

168 RXD6 I Cell Stream Interface Receive data bit 6

169 RXD7 I Cell Stream Interface Receive data bit 7

170 SRD0 I/O SAR Memory data bus bit 0

171 N/C – Not Connected

172 SRD1 I/O SAR Memory data bus bit 1

173 SRD2 I/O SAR Memory data bus bit 2

174 N/C – Not Connected

175 SRD3 I/O SAR Memory data bus bit 3

ÍÍÍÍÍ

176

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

177 N/C – Not Connected

178 SRD4 I/O SAR Memory data bus bit 4

179 SRD5 I/O SAR Memory data bus bit 5

180 N/C – Not Connected

181 SRD6 I/O SAR Memory data bus bit 6

182 N/C – Not Connected

ÍÍÍÍÍ

183

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

184 N/C – Not Connected

185 SRD7 I/O SAR Memory data bus bit 7

186 N/C – Not Connected

187 SRD8 I/O SAR Memory data bus bit 8

188 N/C – Not Connected

ÍÍÍÍÍ

189

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

190 SRD9 I/O SAR Memory data bus bit 9

191 N/C – Not Connected

192 SRD10 I/O SAR Memory data bus bit 10

193 SRD11 I/O SAR Memory data bus bit 11

194 N/C – Not Connected

195 SRD12 I/O SAR Memory data bus bit 12

196 SRD13 I/O SAR Memory data bus bit 13

197 SRA3 O (3-state) SAR Memory address bit 3

198 N/C – Not Connected

199 SRA4 O (3-state) SAR Memory address bit 4

ÍÍÍÍÍ

200

ÍÍÍÍÍÍÍÍ

VSS

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

ÍÍÍÍÍ

201

ÍÍÍÍÍÍÍÍ

VDD

ÍÍÍÍ

–

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ

202 SRA5 O (3-state) SAR Memory address bit 5

203 SRA6 O (3-state) SAR Memory address bit 6

204 SRA7 O (3-state) SAR Memory address bit 7

205 SRD14 I/O SAR Memory data bus bit 14

206 SRD15 I/O SAR Memory data bus bit 15

207 SRD16 I/O SAR Memory data bus bit 16

208 SRD17 I/O SAR Memory data bus bit 17

MB86687A APPENDICESEdition 2.0

117

G. PACKAGE DIMENSIONS

.006 ± .002

.016 (0.40)

MAX

FPT-208P-M01

Dimensions in

inches (millimeters)

208-LEAD PLASTIC FLAT PACKAGE

(CASE No.: FPT-208P-M01)

1992 FUJITSU LIMITED F208001S–3C

156

157

208

104

105 0 (0) MIN

(STAND OFF HEIGHT)

Details of “A” part

.006 (0.15)

MAX

1.102 ±.004

(28.00 ±0.10)

LEAD No.

(MOUNTING HEIGHT)

.152 (3.85) MAX

(0.15 ± 0.05)

.020 ± .008

(0.50 ± 0.20)

1.205 ±.008

(30.60 ±0.20)

.0197 (0.50)

TYP

INDEX “A”

.008 (0.20)

.010 (0.25)

1.004

(25.50)

REF

Details of “B” part

.004 (0.10)

.003 (0.08)

“B”

1.165 (29.60)

NOM

.008 ± .004

(0.20 ± 0.10) M

0° to 10°

Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical applications.

Complete information sufficient for construction purposes is not necessarily given.

This information contained in this document does not convey any license under copyrights, patent

rights, software rights or trademarks claimed by Fujitsu.

The information contained in this document has been carefully checked and believed to be reliable.

However Fujitsu assumes no responsibility for inaccuracies.

Fujitsu reserves the right to change the product specifications without notice.

No part of this publication may be copied or reproduced in any form without the prior written consent

of Fujitsu.

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