Digitally Programmable series: PDU-13256 (8 Bit) TTL Interfaced Delay Units Features: @ Input & output TTL buffered w@ 8-BIT TTL programmable delay line @ Two (2) separate outputs; inverting & non-inverting. & Completely interfaced m@ Compact & low profile 0 = Logic 0 1 = Logic 1 0 = Dont care. T, = Reference or inherent delay of unit. T, ~ T.,,; multiplier of incremental delay Delay variation: Monotonic in one direction m Programmed delay tolerance:+5% or 2 g@ Inherent delay: 44 NS onpin6 Specifications: Test Conditions @ Input signal requirement: TTL logic @ Input pulse-width: Output fan-out: TTL schottky load = 150% of Max. delay. @ Input pulse spacing: = 3 times of Max. delay. : : @ Input pulse voltage: NS whichever is greater TTL logic. ! ; mw Measurements taken @ 45NS onpin5. [yPical T, = 25C, Veo = BV. m@ Power dissipation: 1.1W Max. @ Supply voltage: 4.75 to 5.25. Vdc @ Operating temperature: 0-70C m= Temperature Coefficient: 100 PPM/C Part No. PDU-13256-1 PDU-13256-2 PDU-13256-3 PDU-13256-4 PDU-13256-5 PDU-13256-6 PDU-13256-7 PDU-13256-8 PDU-13256-9 PDU-13256-10 NOTE: 1. Forthe sake of simplicity all 256 programmable steps are not shown in this truth table. 2. After Bit 6, the incremental delay tolerance is 5% of programmed delay. DATA DELAY DEVICES Inc. @ 385 Lakeview Avenue, Clifton, New Jersey 07011 @ (201) 772-1106 = TWX 710-989-7008