This document is not intended for viewing onscreen. It is best viewed when printed and read from paper. Depending on your printer, you may need to select "Shrink to Fit" in the print dialog to ensure that the document prints correctly. ASAHI KASEI [AK23911 AK2 Biml 3 9 1 MMBMD IVINR FOR r/i SHIFT QPSK !ODUHTIO General Description The AK2391 is a band limitingfilterfor ir/4shift QPSK modulationof PersonalHandy phone System (PHS) in Japan.The AK2391 is compliantwith PersonalHandy phone System standardof RCR in Japan.The AK2391consistsof a Sum logic, Root Nyquist-Roll-offfilters and DA convertersetc. *l *l *! *l I Features [ Compliant with PersonalHandy phone System (PHS) in Japan TransmissionRate 384kbps Roll-offFilter (DigitalFiltert AnalogFilter) * Root tiyquist FrequencyResponse * Roll-offRate CX=O.5 * Pass Band (3dB) 96kHz * Stop Band Attenuation Min 60dB(at600kHz) Min 65dB(at900kHz) ModulationError 1.7%rmsTyp. Ramp responsecircuit D/A converter AdjustableOutputLevel and DC Offset voltage Differentiallogicalcircuitconformingto the i7/4 shift QPSK modulationsystem NormalMode SUPPIYCurrent 7.OmA Typ. PowerSaving Mode 20,uA Typ. 2.'7V-5.5V SUPPIY Voltage Package 24 Pin VSOP Block Diagram I I BSTI ( 384Kbps(~ SDATA SCLK () 384 kHz PLLC (~ Delay BSTO I Serial to Parallel---='-Su.w Converter ----- Logic -'--+-Digital ~ Fi Iter DAC > Ana Iog --+-( 1A LPF IAB ---+- Digital Fi Iter ~ DAC > Ana Iog LPF QAB h v PLL 1 Control Register // Offset Adjust @!ww!L VREF GEN ~ ) VBIAS / / ~ u CKMOD UCLK AVDD AVSS OVSS DVDDTSTB RCLK RDATA STB 19.2UHZ OO56-E-1O QA j! PDIB PD2B AGND 1995/07 ASAHI KASE1 [AK23911 Package/Pin Assignments BSTO~ 10 24 ~RDATA BSTI~ 2 23 ~RcLK 3 22 ~STB SCLK~ 4 21 ~TSTB DVDD~ 5 20 ~DVSS MCLK~ 6 19 ~PD2B PLLC~ 7 18 ~PDIB CKh40D~ 8 17 ~MRsT 9 16 ~QA 10 15 ~QAB 11 14 ~AVSS 12 13 ~AGND SDATA~ IA= IAB~ AVDD~ VBIAS~ OO56-E-1O 1995/07 -2" [AK23911 ASAHI KASEI Pin/Function I 1/0 Descriptions I Function Serialdata input pin. Serial data is sampledon the I risingedge of SCLK. Partitioningof the parallel data is decidedon the risingedge of BSTI . Serial clock input pin. SCLK I 4 Clock frequencyis 384kHz. I Masterclock input pin. Clock frequencyis 19.2!I(Hz. MCLK 6 In the masterclock mode, MCLK is distributedto all circuits. Clock mode select pin.SettingCKYOD to "L" puts the I CKMOD 8 AK2391 in the master clock mode.SettingCKl(ODto "H" puts the AK2391 in the PLL clock mode. PLL bufferpin. Must be connectedto the ground o 7 PLLC througha 4700PF+20% capacitor. I Burst signal input pin.BSTI is synchronouslysampled 2 BSTJ on the risingedge of SCLK. o Burst signaloutput pin. 1 BSTO Positiveoutput pin for in phase. IA o 9 Ro210kQ Note 1), COS20PF Note 2) o Negativeoutput pin for in phase. IAB 10 Ro210kQ Note 1), COS20PF Note 2) o Positiveoutput pin for quadraturephase. C)A 16 Ro~lOkQ Note 1), COS20PF Note 2) Negativeoutput pin for quadraturephase. QAB o 15 RoalOkQ Note 1), CO=20PF Note 2) Op-ampbias voltageoutput pin. Must be connected VBIAS o 12 to the analog ground throughresister. Ro=47Kf2t5% Power down controlpins. A power down mode can be PDIB I 18 PD2B selectedby using both PDIB and PD2B. 19 Clock pin for controlregisterdata. RCLK I 23 RDATA is sampledon the risingedge of RCLK. B Controldata input pin on the on-chipregisters. RDATA 24 Strobe pin for control registerdata. STB I 22 RDATA is stored to the registeron the risingedge of STB. Test mode controlpin. SettingTSTB to "H" puts the TSTB I 21 AK2391 in the normal mode. SettingTSTB to "L" puts the AK2391 in the test mode. (see "setting of control register") Masterreset pin. H level inputcausesall registers MRST I 17 reset to L. . AVDD Analogpower supply pin. 11 -- AVSS Analoggroundpin. 14 -- Digitalpower supply pin. DVDD 5 -- Digitalgroundpin. DVSS 20 ..,-..,1 ,,..,,. 13 IA LJINIJ l- I,lb~ulnDutDin. Note I)Registermust be connectedbetweenXA and XAB. Note 2)At power down mode.thesepins are high impedance. (The voltageis VDD/2.) Pin 3 Name SDATA OO56-E-1O 1995/07 -3- ASAHI KASEI [AK23911 ABSOLUTE Parameter DC Supply (Referencedto GND) I MAXIMUM RATING Symbol Min I DVDD I Max -0.3 I Units Ivl 7.0 Note 1) AVDD2DVDD WARNING: Operationsat or beyond these limitsmay result in permanentdanage to the device. Normal operationis not guaranteedat these extremes. RECOMMENDED Parameter DC Supply (Referencedto GND) OperatingTemperature Note: AVSS,DVSS=OV ELECTRICAL OPERATING CONDITIONS Symbol Min DVDD AVDD T, 2.7 2.7 "30 TYP Max Units 5.5 5.5 85 v v "c CHARACTERISTICS I DC Characteristics Parameter Supply Current Mode 1 All circuitsare turnedoff. Mode 2 VREF and PLL circuitsare turnedon. Mode 3 VREF circuit is only turned on. Mode 4 (MasterClock) NormalOperatingmode Mode 4 (PLL) NormalOperatingmode InputLeakageCurrent DigitalHigh-LevelOutput Voltage Io.=-hl) (Notel) DigitalLow-LevelOutput Voltage 10,=2mA (Notel) DigitalHigh-LevelInputVoltage DigitalLow-LevelInputVoltage te 1) Symbol IDD I, VOH Min VIL Max Units 20 30 I.LA I 2.0 I 3.0 500 700 7.0 9.0 8.5 13.0 ~lo Vr)-1. o 0.5 VOL VIH TYP mA PA mA A ,(.LA v v v 0.7VD O.3VD v BSTO Pin only 1995/07 -4" ASAH1 KASE1 H Analog Characteristics (AVDD=2. 7-'5.5V9DVDD=2. 7'-5.5V) Symbol Parameter min typ max %B MCLK Frequency f, 19.2 MHZ SCLK Frequency f, 384 KHz AnalogGround Reference Voltage AnalogOutput Level (Note 1) Itt+IAB QA+QAB 2'2 V.NIT AdjustableRange of AnalogOutputLevel O.460 0.500 +20.o %0 -17.5 -20.0 -22.5 -60 -65 -60 dB dB dB 3 %rms 1.7 ~,-loo PP1/Oc TemperatureDrift of AnalogOutputLevel IQA-QABI AdjustableRange of DC OffsetVoltage VPP +17.5 ModulationError I IA-IABI , 0.575 +15.o Stop Band Attenuation at 600kHzt96kHz at 900kHz*96kHz (Note2) SpuriousLevel (Note2) DC OffsetVoltage v 0.5AVDDk0.2 VREF 35 40 30 mV 50 mV Note I:Outputload impedanceis more than 10KC2, and data streamsfrom DATA pin are all zero. Note 2:Referencedto twiceof the power betweenOHZ to 96kHz. OO56-E-1O -5- [AK23911 ASAHI KASEI SwitchingCharacteristics Parameter Master BSTI Clock I Symbol I fclk Frequency Min I TVD 19:2 I Max I Units MHz Input Timing BSTI DELAY TItiE FROM SCLK RISINGEDGE 0.65 -0.65 td,,tdf ,lLS SDATA Input Timing SDATA SET UP TIME SDATA HOLD TIME t, ps ,uS O.65 O.65 th RDATA Input Timing REGISTERCLK FREQUENCY REGISTERDATA SET UP TIME REGISTERDATA HOLD TIME STROBE SET UP TI)!E STROBE PULSE WIDTH STROBE HOLD TIME 5 frclk t,, 50 50 50 50 50 t,h tSu t Pw tht DigitalSignal TimingCharacteristics :<----------------- -----+ 7/ 50% For all digitalTiming. SDATA InputTiming Diagram t df ;+: PUi 1 1 ,, , 1 SDATA 1 SCLK dThJddn-r -6- MHz ns ns ns ns ns ASAHI KASEI [AK23911 BSTI Input TimingDiagram )f~ JUUUUUU ~JHz pmrttlaldata SDATA > xl Y1 x2 Y2 x3 Y3 " ! 2.25symtx21: BSTO i Xlca Y103 X109 103 110 Yllo Ollm )) 6. Z5symboI i 9! ~((ramp up Zsymbol ramp down 2symbol A -1 /-- /-~lMlwOUtDUt I.Q : -2.5symbol =j--+-# i 24.3* 0.6As I ; RI I R2 RI a ~ R2 11 01 12 I106 I109 1110 RD1 RD2 Q106I Q107 [ Q106 Q109 Q110 RIM R02 I106 )) I /) I Q2 I107 1 ORamp up 2symbol ORamp down 2symbol ODelay timdFrm BSTI to BSTO) :2.25symbol OParallel data(Xk, Yk) is modulatedto (Ik,Qk). :24.3*0.6LLs ODelay time of modulation OData for ramp_upand ramp_downare generatedautomatically. ramp_updata 0000(4bits) ramp_downdata 0000(4bits) RDATA Input TimingDiagram ,, t rh RDATA ,!, RCLK -- ! , ! , I I :* 1 /'frclk STB , , , , o 1 I , 4 , , ! ! -.-,/ , ,,/ l-- , t sll X ,-- , , , t pw tht 1995/07 -7" ASAHI KASE1 [AK23911 Specificationsin regardto the BSTI input @ The "firstBSTI " is definedas firstburst signal inputafter recoverof power down mode (full power down condit on[mode1] or partialenergizationcondition[node 2]). (Ref. Fig.3) All timinginsidethe AK2391use the risingedge of "firstBSTI" as the start point. So,384kHzinternalclock,output signal,and anothertimingare decided by this rising edge. @ Both "H" length and "L" lengthof theBSTI shouldbe even symbol lengths.AK2391expect these lengths for modulation.(Ref.Fig.d) @l Accordingto 0 and @, In some casesyou would not be sure whetherBSTI lengthsare even or not. We recommendyou to use the power down mode (mode 1 or mode 2) duringBSTI "L". It is a good method to preventtimingerrors. power mode 1 or mode 2 mode saving mode 4 BSTI "first BSTI" rising edge Fig.3 BSTI I ! "H" length 1 "L" length 1 "L" ( "H" length 2 "H" length 1,2,3"-. and "L" length equal to even symbol lengths. length 2 "L" length 3 "H" length 3 1 ,2,3.-. must be Fig.4 OO56-E-1O 1995/07 -8- ASAHI KASEI Useful examplesare shown below. (Example1) In case of burst operationafter power-downcancellation point A mode 1 or mode 2 -- retie4 power MV ing mode Mst i~put = L burst operat ion : Min. lAS :, ....-. burst input = L burst operat ion (( )) BST I k 1' This rising edge sets al internal timing of maculation. "H" length and "L" lengths Intermadiately you are even symbo I lengths. use mode 1 or 2 \ "H" I'engthand "L" lengths are e en symbo I Iengths. i during this interval, If you use mode 1 or 2at you set this Iength point A, this rising edge equa I to even symbo I resets all internal timing. Iength. (Example 2) In case of continuousoperationafter power-downcancellation point B !zade1 or saving mode mode 2 I ,! :: mode 4 burst ~input= L `.----, cent inuous(( )) burst input = L burst operat ion (( )) BST I += This rising edge sets ail internal timing of modulation. IntermediateIy you use made 1 or 2 during this interval, or you set this length equal to even symba I length. "H" ten th and "L" lengths are eve1 symbo I lengths. v If You usemcde 1 or2at point B, this rising edge re-setsal I internal timing. 1995/07 OO56-E-1O -9- ASAHI KASEI [AK23911 Power saving mode l)Currentconsumption Switchstatus PDIB PD2B CKMOD Power saving mode Mode 1 Mode 2 Mode 3 Mode 4 (STAND BY) o (NON TRANSMITTING) (NON TRANSMITTING) (TRANSMITTING) 1 1 1 Currentconsumption(max) ex ernal clock PLL mode mo$e x 0 0 x 1 0 700,UA 1 x 9mA 30LLA 301LA 3mA 13mA This LSI selects the above four nodesaccordingto the statusof the power down control pins (PDIB,PD2B) and the clock mode selectpin. PLL mode is selectedat the time of CK!JOD of =1, and externalclock mode is selectedat the time of CKMOD=O.The "transmitting" mode 4 indicatesthe normaloperationcondition. 2) Rising-uptime The time requiredfor stabilization of the blocksbecomingactiveat the time of shifting from one mode to another(shiftingtime)is shown in the followingtable. Status shifting Clock mode Shiftingtime Externalclock Power off + mode 1 lms Power off mode mode 3 lms mode 1 ~ mode 3 Ioo/.Ls mode 1 ~ mode 4 100WS mode 3 mode 4 25ps Other shifting 0s Power off * PLL ode mode 1 1Oms Power off * mode 2 10ms mode 1 + ode 2 I 10ms ode 1 mode 4 1I 10ms mode 2 mode 4 ,I 25us Other shifting `0s w... off w.1 4 4% a ~a The shiftingtimesbetweenmodes (max.value)and use examplesare shown in the following figure. (At the time of externalclock mode: CKMOD=O) ,! mode 1 PDIB mode 3: ,. !! I mode 4 mode 1 I loo#s 1995/07 -1o- ASAHI KASEI (At the time of PLL mode;CKMOD=l) power off mode 1 m I PDIB 1Oms ,h& PD2B 100!.s #y~ 25us mode 2 &de Ions mode 4 -11- ~ 2{ mode 4 mode 2 ASAH1 KASEI E [AK23911 Settingof controlregister RDATA RCLK STB A3 A2 Al AO D5 D4 D3 D2 D1 DO o 1 0 000 0 0 0101000000 Ich Offset Qch Offset 0 1 1 0 xx I-Juno Ich o 1 1 1 xx Qch Gain O () () 1 XX XXIQ Ooloxxxxxly ana Gain FTEST CONSTANTINPUT DATATEST Outputgain can be controlledby settingof controlregister.( -20.0%to +17.5% :step 2.5%). Outputoff-setvoltage( IA-IAB, QA-QAB)canbe controlled. ( -41.9mVto +40.6mV:step 1.3mV). Note that one step of off-setvoltageis changed if output gain level is pre-set. (Resetof controlregisters) After power is supplied,contentsof controlregistersare unknown.So, please set controlregistersafter power is supplied.If you want to initilizeall controlregisters to zero, please use MRST pin. OO56-E-1O 1995/07 -12- ASAHI KASEI (Table of gain control) Registerdata D4 D3 D5 x x o x x o x x o x x o x x o x x o x x o x x o x x 1 x x 1 x x 1 x x 1 x x 1 Registerdata D5 D4 D3 x x 1 x x 1 x x 1 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 D2 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 D1 1 0 0 DO 1 0 1 0 1 0 1 0 1 0 1 0 1 Outputgain (Percentage of standardoutput level) 117.5 115.0 112.5 110.0 107.5 105.0 102.5 100.0 97.5 95.0 92.5 90.0 87.5 DO 0 1 0 outputgain (Percentage of standardoutput level) 85.0 82.5 80.0 (Tableof off-setvoltage) 0 0 0 0 1 1 1 1 L-L- ster lata D4 D3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 D2 1 0 0 0 0 D1 1 1 1 DO 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 3.9 2.6 1.3 0 -1.3 -2.6 -3.9 -5.2 -41.6 1 -13- I [AK23911 ASAH1 KASEI (Testmode) With test mode, the followingoutputscan be selectedin regard to the data written into the registerswith the addresses0001 and 0010. For test mode, writingto the registeris executedwith the TSTB terminalin "H" condition,and test mode then is reachedwhen the TSTB terminalis switchedto "L". Test mode sequenceexample 1. Write data to address0001 or 0010. 2. Set TSTB to "L". (Shiftingto testmode) 3. Set BSTI to "H". (Outputstart) 4. Write data to address0110 or 0111. (Gainadjustment) 5. Write data to address0100 or 0101. (Offsetadjustment) 6. Set BSTI to "L". (Outputcompletion) 7. Set TSTB to "H". (Shiftto normalmode) @) FTEST (in regardto the data writtento the registerof the address0001) Test mode Registerdata DO output D3 D2 D1 D4 x x o 0 x I=O,Q=O x x x o 1 1=0, Q=VUNIT x x x 1 0 I=VurQ,~, Q=O x x x 1 1 I= VUNIT, Q=VUNIT Note: Vunit is the voltagecorrespondingto the output when the input data all are zero, correspondingto the value when gain and offsethave been adjusted. D5 x x x x @ Constantinput DATA TEST(inregardto the data written to the registerof the address 0010) Test mode Registerdata DO output D3 D2 D1 D5 D4 x x n=l,2,3".. x x o 0 Output for (Xn,Yn)=(O,O) x n=l,2,3.. " x x x o 1 Output for (Xn,Yn)=(O,l) x x n=l,2,3. "" x x 1 0 Output for (Xn,Yn)=(l,O) x x n=l,2,3". " x x 1 1 Output for (Xn,Yn)=(l,l) Note 1) FTEST and ConstantinputDATA TEST are active if TSTB is set to `L' and BSTI is se tto'H'. Note 2) Rampingresponseis not executedin the TEST mode. 1995/07 OO56-E-1O -14- ASAHI KASEI [AK23911 Application Circuit I ~Connection for PLLmode Operationis made using the 384 kHz clock enteredfrom the serialdata Input clock terminal(SCLK).At this time, fix the CKMOD terminalto "H" and the MCLK terminalto DVDD or DVSS. Dat 38 13u r s t S i gna co 1 I ster Input BurstSi Ou t pu t Outp saving select R1 C1=4700PF*20% C2=1OOOPF R1=47KQ?5% * Load... 2lOKf2. - ~20pF OO56-E-1O 1995/07 -15- ASAHI KASEI [AK23911 OConnection for externalclock mode Operationis made using the 19.2 kHz clock entered from the MCLKterminal.At this time, set the CKMOD terminalto "L", synchronizethe SCLK terminalto the rise of the 19.2MHz, and provide384 kHz as input. Data 384Kbps DVSS () ( ) SCLK DVDD ( ( ) MCLK .4VSS( () 384KHz+ 19. 2MHz+ I Z% Burst S i gna 1 con t ro Input~ 1 = SDATA CKMOD AVDD PLLC IMRST BSTI STB ) v () Register Data Input * Burst output S i gna Ou t Pu I BSTO IA RCLK lAB TSTB QA PD2B( ) ~--power QAB PDIB( ) t [ d-$ RD ATA AGND = :g _mode saving select VBIAS( I R]= C2=1OOOPF Rl=47KQt5% * Load... 2lOKf2. S20PF OO56-E-1O 1995/07 -16- ASAHI KASEI H [AK23911 Packagesize 24 Pin VSOP TJnit:nlm *7.8 0"1 7 r 13 24 RMUIM~ A n 0 q In * Y tltltltltmf 1 - +0.1 0.22-0.05 Note: 12 ~65 0.12 G Dimensions with include a range L a * do not remnant. *O-10" Deta [Material] i I o f A Resin :LowStress Type Epoxy Resin Lead Frame:42Alloy OO56-E-1O 1995/07 -17- [AK23911 ASAHI KASEI Package larking [XXXYS Content] xxx: Manufacturing Data Last d,igit of AD year, 2 digitsof week number. Y: Manufacturing Lot Number (UsingA-Z Alphabet,without I.O,U,Z) s: AssemblyPlantCode OO56-E-1O -18- 1 Productsand productspecificationsmentionedin this data sheet are subject to change withoutnotice due to product improvements. Please understandthat ASAHI KASEI MICROSYSTEMSCo., Ltd. (AKM) shall not be held liable for the results of using this product under conditions other than those specified in this data sheet. AIso, PleaSE! note that this company shall not be held liable frjr infringement of patent rights, industrial ownership Or Other rights Of any third party regarding the use of information or drawings included in this data sheet. Furthermore,in the case that the product described in this data sheet is specified as a strategic product under the provisions Of the foreign exchange and foreign trade control laws of Japan (including services), it is necessary to obtain an export permit in accordance with the specified laws in the event of import.