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ASAHI KASEI [AK23911
Biml AK2 391
MMBMDIVINRFORr/iSHIFTQPSK
!ODUHTIO
General Description
The AK2391is a band limitingfilterfor ir/4shift QPSK modulationof PersonalHandy
phoneSystem(PHS) in Japan.The AK2391is compliantwith PersonalHandy phoneSystem
standardof RCR in Japan.The AK2391consistsof a Sum logic,Root Nyquist-Roll-offfilters
and DA convertersetc.
[Features I
❑Compliant with PersonalHandyphone System (PHS) in Japan
❑TransmissionRate 384kbps
❑Roll-offFilter(DigitalFiltert AnalogFilter)
* Root tiyquistFrequencyResponse
* Roll-offRate CX=O.5
* Pass Band (3dB) 96kHz
* Stop Band Attenuation Min 60dB(at600kHz)
Min 65dB(at900kHz)
•l ModulationError 1.7%rmsTyp.
•l Ramp responsecircuit
❑D/A converter
•! AdjustableOutputLeveland DC Offsetvoltage
❑Differentiallogicalcircuitconformingto the i7/4shift QPSK modulationsystem
❑SUPPIYCurrent NormalMode 7.OmA Typ.
PowerSavingMode 20,uA Typ.
❑SUPPIY Voltage 2.’7V-5.5V
•l Package 24 Pin VSOP
■Block Diagram
II
BSTI ( Delay I--+-(
-’--+-
Digital > AnaIog
~
Serial to Parallel---=’-
Su.w DAC
384Kbps(
~FiIter LPF
SDATA Converter ----- Logic ---+- Digital ~DAC > AnaIog
FiIter LPF
SCLK () h
384 kHz v
PLLC (~ PLL Control Offset VREF
-Register Adjust GEN ~ )
~1
j!
/
// /
u
CKMOD UCLK AVDD AVSS OVSS DVDDTSTB RCLK RDATA STB PDIB PD2B AGND
19.2UHZ
BSTO
1A
IAB
QA
QAB
VBIAS
OO56-E-1O @!ww!L 1995/07
ASAHI KASE1 [AK23911
■Package/Pin Assignments
BSTO~ 10 24 ~RDATA
BSTI~ 223 ~RcLK
SDATA~ 322 ~STB
SCLK~ 421 ~TSTB
DVDD~ 520 ~DVSS
MCLK~ 619 ~PD2B
PLLC~ 718 ~PDIB
CKh40D~ 817 ~MRsT
IA= 916 ~QA
IAB~ 10 15 ~QAB
AVDD~ 11 14 ~AVSS
VBIAS~ 12 13 ~AGND
OO56-E-1O
-2” 1995/07
ASAHI KASEI [AK23911
Pin/Function Descriptions
Pin Name I1/0 IFunction
3SDATA I Serialdata input pin. Serialdata is sampledon the
risingedge of SCLK. Partitioningof the parallel
data is decidedon the risingedge of BSTI .
4SCLK I Serialclock inputpin.
Clock frequencyis 384kHz.
6MCLK IMasterclock inputpin. Clock frequencyis 19.2!I(Hz.
In the masterclock mode, MCLK is distributedto all
circuits.
8CKMOD IClockmode selectpin.SettingCKYOD to “L” puts the
AK2391in the masterclock mode.SettingCKl(ODto “H”
puts the AK2391 in the PLL clockmode.
7 PLLC oPLL bufferpin. Must be connectedto the ground
througha 4700PF+20% capacitor.
2 BSTJ I Burst signalinputpin.BSTI is synchronouslysampled
on the risingedge of SCLK.
1 BSTO o Burst signaloutputpin.
9IA o Positiveoutputpin for in phase.
Ro210kQ Note 1), COS20PF Note 2)
10 IAB o Negativeoutputpin for in phase.
Ro210kQ Note 1), COS20PF Note 2)
16 C)A o Positiveoutputpin for quadraturephase.
Ro~lOkQ Note 1), COS20PF Note 2)
15 QAB o Negativeoutputpin for quadraturephase.
RoalOkQ Note 1), CO=20PF Note 2)
12 VBIAS o Op-ampbias voltageoutputpin. Must be connected
to the analogground throughresister.Ro=47Kf2t5%
18 PDIB I Powerdown controlpins. A powerdown mode can be
19 PD2B selectedby using both PDIB and PD2B.
23 RCLK I Clockpin for controlregisterdata.
RDATA is sampledon the risingedge of RCLK.
24 RDATA B Controldata inputpin on the on-chipregisters.
22 STB I Strobepin for controlregisterdata.
RDATA is storedto the registeron the risingedge
of STB.
21 TSTB I Test mode controlpin. SettingTSTB to “H” puts the
AK2391in the normalmode. SettingTSTB to “L” puts
the AK2391in the test mode.
(see “setting of control register”)
17 MRST I Masterresetpin. H level inputcausesall registers
resetto L.
11 AVDD .Analogpower supplypin.
14 AVSS —Analoggroundpin.
5DVDD —Digitalpower supplypin.
20 DVSS —Digitalgroundpin.
.- .,-..,- 1,,..,,.
13 IA LJINIJ l– I,lb~ulnDutDin.
Note I)Registermustbe connectedbetweenXA and XAB.
Note 2)At powerdown mode.thesepins are high impedance.(The voltageis VDD/2.)
OO56-E-1O -3- 1995/07
ASAHI KASEI [AK23911
ABSOLUTE MAXIMUM RATING
Parameter Symbol Min Max Units
DC Supply (Referencedto GND)
II DVDD I -0.3 I 7.0 Ivl
Note 1) AVDD2DVDD
WARNING:Operationsat or beyondthese limitsmay result in permanentdanageto the device.
Normaloperationis not guaranteedat theseextremes.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min TYP Max Units
DC Supply (Referencedto GND) DVDD 2.7 5.5 v
AVDD 2.7 5.5 v
OperatingTemperature T, “30 85 “c
Note: AVSS,DVSS=OV
ELECTRICAL CHARACTERISTICS I
■DC Characteristics
Parameter Symbol
SupplyCurrent Mode 1 IDD
All circuitsare turnedoff.
Mode 2
VREF and PLL circuitsare
turnedon.
Mode 3
VREF circuitis only turned
on.
Mode 4 (MasterClock)
NormalOperatingmode
Mode 4 (PLL)
NormalOperatingmode
InputLeakageCurrent I,
DigitalHigh-LevelOutputVoltage VOH
Io.=-hl) (Notel)
DigitalLow-LevelOutputVoltage VOL
10,=2mA (Notel)
DigitalHigh-LevelInputVoltage VIH
DigitalLow-LevelInputVoltage VIL
te 1) BSTO Pin only
Min TYP Max
20 30
I 2.0 I 3.0
500 700
7.0 9.0
8.5 13.0
~lo
Vr)-1.o
0.5
0.7VD
O.3VD
Units
I.LA
mA
PA
mA
❑A
,(.LA
v
v
v
v
1995/07
-4”
ASAH1 KASE1
H AnalogCharacteristics
(AVDD=2.7-’5.5V9DVDD=2.7’-5.5V)
Parameter Symbol min typ max %B
MCLK Frequency f, 19.2 MHZ
SCLK Frequency f, 384 KHz
AnalogGroundReference Itt+IAB QA+QAB
Voltage 2’2 VREF 0.5AVDDk0.2 v
AnalogOutputLevel V.NIT O.460 0.500 0.575 VPP
(Note 1)
AdjustableRangeof AnalogOutputLevel +15.o +17.5 +20.o %0
-17.5 -20.0 -22.5
Stop Band Attenuation at 600kHzt96kHz -60 dB
(Note2) at 900kHz*96kHz -65 dB
SpuriousLevel -60 dB
(Note2)
ModulationError 1.7 3 %rms
TemperatureDriftof AnalogOutputLevel ~,-loo PP1/Oc
DC OffsetVoltage IIA-IABI , IQA-QABI 30 mV
AdjustableRangeof DC OffsetVoltage 35 40 50 mV
Note I:Outputload impedanceis more than 10KC2,and data streamsfrom DATA pin are all
zero.
Note 2:Referencedto twiceof the power betweenOHZ to 96kHz.
OO56-E-1O -5-
ASAHI KASEI [AK23911
■SwitchingCharacteristics
Parameter I Symbol I Min I TVD I Max I Units
Master Clock Frequency fclk 19:2 MHz
BSTI Input Timing
BSTI DELAYTItiE td,,tdf -0.65 0.65 ,lLS
FROM SCLK RISINGEDGE
SDATA Input Timing
SDATA SET UP TIME t, O.65 ps
SDATA HOLD TIME th O.65 ,uS
RDATA Input Timing
REGISTERCLK FREQUENCY frclk 5MHz
REGISTERDATASET UP TIME t,, 50 ns
REGISTERDATA HOLD TIME t,h 50 ns
STROBESET UP TI)!E tSu 50 ns
STROBE PULSEWIDTH tPw 50 ns
STROBEHOLD TIME tht 50 ns
DigitalSignal TimingCharacteristics
:<----------------- -----+
7/50%
For all digitalTiming.
SDATA InputTimingDiagram
PUi ,
tdf
;+:
,,
1
11
SDATA 1
SCLKdThJddn-r
-6-
ASAHI KASEI [AK23911
BSTI InputTimingDiagram
~JHz JUUUUUU
pmrttlaldata >)f~
SDATA xl Y1 x2 Y2 x3 Y3Ollm Xlca Y103X109 103 110 Yllo
!2.25symtx21:“)) i 6. Z5symboI 9!
BSTO i ramp up Zsymbol
~(( ramp down 2symbol
/-- A
/-- -1
~lMlwOUtDUt :
I.Q =j--+-# ~
-2.5symbol i
24.3* 0.6As ; I
I RI R2 11 12 )) I I106 I107 I106 I109 1110 RD1 RD2
aRI R2 01 Q2 /) I Q106I Q107 [ Q106 Q109 Q110 RIM R02 1
ORamp up 2symbol
ORamp down 2symbol
ODelay timdFrm BSTI to BSTO) :2.25symbol
OParallel data(Xk,Yk) is modulatedto (Ik,Qk).
ODelay timeof modulation
OData for ramp_upand ramp_down:24.3*0.6LLs
are generatedautomatically.
ramp_updata 0000(4bits)
ramp_downdata 0000(4bits)
RDATA InputTimingDiagram
,, trh
RDATA ,!,
RCLK —
:* !
, ,
1/’frclk !,
, ,
I,
Io
STB 1
, I
4
,!,
,-.-,/ ,,/
!l-- ,-- X
,, , ,
tsll tpw tht
1995/07
-7”
ASAHI KASE1
Specificationsin regardto the
@ The “firstBSTI “ is defined
mode (full power downcondit
[AK23911
BSTI input
as firstburst signalinputafter recoverof power down
on[mode1] or partialenergizationcondition[node2]).
(Ref.Fig.3) All timinginsidethe AK2391use the risingedge of “firstBSTI” as the
startpoint.So,384kHzinternalclock,outputsignal,and anothertimingare decided
by this risingedge.
@ Both “H” length and “L” lengthof theBSTI shouldbe even symbollengths.AK2391expect
theselengthsfor modulation.(Ref.Fig.d)
@l Accordingto 0 and @, In some casesyou would not be sure whetherBSTI lengthsare
even or not. We recommendyou to use the power down mode (mode 1 or mode 2) duringBSTI
“L”. It is a good methodto preventtimingerrors.
mode 1 or
power saving mode mode 2 mode 4
BSTI
“first BSTI” rising edge
Fig.3
BSTI I ! “L” length 1 (“L” length2 “L” length3
“H” length1 “H” length2 “H” length 3
“H” length 1,2,3”-. and “L” length 1,2,3.-. must be
equal to even symbol lengths.
Fig.4
OO56-E-1O 1995/07
-8-
ASAHI KASEI
Usefulexamplesare shownbelow.
(Example1) In case of burstoperationafterpower-downcancellation
point A
mode 1 or
mode 2 —: Min. lAS
power MV ing mode retie4 :,
....-.
al
BSTI
Mst i~put = L burst operation burst input = L burst operation
((
))
k\
1’
This rising edge sets “H” length and “L” lengths Intermadiately you
internal timing of maculation. are even symboI lengths. use mode 1 or 2
during this interval,
you set this Iength
equa I to even symboI
Iength.
“H” I’engthand “L” lengths
i
are e en symboI Iengths.
If you use mode 1 or 2at
point A, this rising edge
resets all internal timing.
(Example 2) In case of continuousoperationafterpower-downcancellation
point B
!zade1 or I ,!
mode 2
saving mode mode 4 ::
‘.----,
burst ~input= L centinuous(( burst input = L burst operation
))
BSTI ((
))
+=
This rising edge sets IntermediateIy you use “H” ten th and “L” lengths
ail internal timing of modulation. made 1 or 2 during this 1
are eve symboI lengths.
interval, or you set this v
length equal to even symbaI If You usemcde 1 or2at
length. point B, this rising edge
re-setsal I internal timing.
OO56-E-1O 1995/07
-9-
ASAHI KASEI [AK23911
■Power savingmode
l)Currentconsumption
Powersavingmode Switchstatus Currentconsumption(max)
PDIB PD2B CKMOD $
ex ernalclock PLL mode
mo e
Mode 1 (STAND BY) o x x 30LLA 301LA
Mode 2 (NON TRANSMITTING) 1 013mA
Mode 3 (NON TRANSMITTING) 100700,UA
Mode 4 (TRANSMITTING) 1 1 x9mA 13mA
This LSI selectsthe abovefournodesaccordingto the statusof the power down control
pins (PDIB,PD2B) and the clockmode selectpin. PLL mode is selectedat the time of CK!JOD
=1, and externalclockmode is selectedat the time of CKMOD=O.The “transmitting”of
mode 4 indicatesthe normaloperationcondition.
2) Rising-uptime
The time requiredfor stabilizationof the blocksbecomingactiveat the time of shifting
fromone mode to another(shiftingtime)is shown in the followingtable.
Clock mode Statusshifting Shiftingtime w...
off
Externalclock Poweroff + mode 1 lms
mode Poweroff - mode 3 lms
mode 1 ~
4%
w.1
mode 3 Ioo/.Ls
mode 1 ~ mode 4 100WS
mode 3 4mode 4 25ps
Othershifting 0s
PLL ❑ode Poweroff * mode 1 1Oms
Poweroff * a ~a
mode 2 10ms
mode 1 + ❑ode 2 10ms
I
❑ode 1 - mode 4 I10ms
1
mode 2 - mode 4 I 25us
,
Othershifting ‘0s
The shiftingtimesbetweenmodes (max.value)and use examplesare shown in the following
figure.
(At the time of externalclockmode:CKMOD=O)
loo#s
,!
mode 1 mode 3: mode 4 mode 1
,.
PDIB !!
I I
1995/07
-1o-
ASAHI KASEI
(At the time of PLL mode;CKMOD=l)
m
power off
Ions
1Oms ,h&
#y~
100!.s
25us
mode 2 mode 4
mode 1 &de 2{ mode 4 mode 2
I
PDIB
PD2B ~
-11-
ASAH1 KASEI
E Settingof controlregister
[AK23911
RDATA
RCLK
STB
A3 A2 Al AO D5 D4 D3 D2 D1 DO
o 1 0 0 ❑000 ❑0
0101000000
0 1 1 0 xx I-Juno
o 1 1 1 xx ❑ana
O () () 1 XX XXIQ
Ooloxxxxxly
Ich Offset
Qch Offset
Ich Gain
Qch Gain
FTEST
CONSTANTINPUTDATATEST
Outputgain can be controlledby settingof controlregister.( -20.0%to +17.5%:step
2.5%).Outputoff-setvoltage(IA-IAB,QA-QAB)canbe controlled.( -41.9mVto +40.6mV:step
1.3mV).Note that one step of off-setvoltageis changedif outputgain level
is pre-set.
(Resetof controlregisters)
Afterpower is supplied,contentsof controlregistersare unknown.So, pleaseset
controlregistersafterpower is supplied.If you want to initilizeall controlregisters
to zero,please use MRST pin.
OO56-E-1O 1995/07
-12-
ASAHI KASEI
(Table of gain control)
Registerdata Outputgain (Percentage
D5 D4 D3 D2 D1 DO of standardoutputlevel)
xxo 1 1 1 117.5
xxo 1 1 0 115.0
x x o 1 0 1 112.5
xxo 1 0 0 110.0
xxo 0 1 1 107.5
x x o 0 1 0 105.0
xxo 0 0 1 102.5
xxo 0 0 0 100.0
x x 1 1 1 1 97.5
x x 1 1 1 0 95.0
x x 1 1 0 1 92.5
xx1 1 0 0 90.0
x x 1 0 1 1 87.5
Registerdata outputgain (Percentage
D5 D4 D3 D2 D1 DO of standardoutputlevel)
x x 1 0 1 0 85.0
x x 1 0 0 1 82.5
xx1 0 0 0 80.0
(Tableof off-setvoltage)
0
0
0
0
1
1
1
1
L-L-
ster
D4
1
0
0
0
0
1
1
1
1
0
lata
D3
1
0
0
0
0
1
1
1
1
0
D2
1
0
0
0
0
1
1
1
1
0
D1
1
1
1
0
0
1
1
0
0
0
DO
1
1
0
1
0
1
0
1
0
0
3.9
2.6
1.3
0
-1.3
-2.6
-3.9
-5.2
-41.6 I
-13-
ASAH1 KASEI [AK23911
(Testmode)
With test mode, the followingoutputscan be selectedin regardto the data writteninto
the registerswith the addresses0001and 0010.For test mode, writingto the registeris
executedwith the TSTB terminalin “H” condition,and test mode then is reachedwhen the
TSTB terminalis switchedto “L”.
Test mode sequenceexample
1. Write data to address0001 or 0010.
2. Set TSTB to “L”. (Shiftingto testmode)
3. Set BSTI to “H”. (Outputstart)
4. Write data to address0110 or 0111.(Gainadjustment)
5. Write data to address0100 or 0101.(Offsetadjustment)
6. Set BSTI to “L”. (Outputcompletion)
7. Set TSTB to “H”. (Shiftto normalmode)
@) FTEST (in regardto the data writtento the registerof the address0001)
Registerdata Test mode
D5 D4 D3 D2 D1 DO output
xxxxo 0 I=O,Q=O
xxx x o 1 1=0, Q=VUNIT
xxx x 10I=VurQ,~, Q=O
x x x x 1 1 I= VUNIT, Q=VUNIT
Note: Vunit is the voltagecorrespondingto the outputwhen the inputdata all are zero,
correspondingto the valuewhen gain and offsethave been adjusted.
@ ConstantinputDATA TEST(inregardto the data writtento the registerof the address
0010)
Registerdata Test mode
D5 D4 D3 D2 D1 DO output
x x xxo 0 Outputfor (Xn,Yn)=(O,O) n=l,2,3”..
x x xxo 1 Outputfor (Xn,Yn)=(O,l) n=l,2,3..”
x x xx1 0 Outputfor (Xn,Yn)=(l,O) n=l,2,3.””
x x xx1 1 Outputfor (Xn,Yn)=(l,l) n=l,2,3”.”
Note 1) FTEST and ConstantinputDATA TEST are active if TSTB is set to ‘L’ and BSTI is se
tto’H’.
Note 2) Rampingresponseis not executedin the TEST mode.
OO56-E-1O -14- 1995/07
ASAHI KASEI [AK23911
Application Circuit I
~Connection for PLLmode
Operationis made using the 384 kHz clockenteredfrom the serialdata Inputclock
terminal(SCLK).At this time,fix the CKMOD terminalto “H” and the MCLK terminalto DVDD
or DVSS.
Dat
38
13u r s t co
Si gna 1 I ster
BurstSi Input
Ou t pu t
Outp saving
select
R1 -
C1=4700PF*20%
C2=1OOOPF
R1=47KQ?5%
* Load...2lOKf2. ~20pF
OO56-E-1O 1995/07
-15-
ASAHI KASEI [AK23911
OConnection for externalclockmode
Operationis made using the 19.2 kHz clock entered from the MCLKterminal.At this time,
set the CKMOD terminalto “L”, synchronizetheSCLK terminalto the rise of the 19.2MHz,
and provide384 kHz as input.
Data 384Kbps
( ) SDATA DVSS ( )
384KHz+ ( ) SCLK DVDD (
19. 2MHz+ ( ) MCLK .4VSS( )v
ICKMOD AVDD
*
Z%
Burst con tro 1=
Signa 1Input~
Burst Si gna I
output
Ou tPu t
[
C2=1OOOPF
Rl=47KQt5%
* Load...2lOKf2. S20PF
PLLC
BSTI
BSTO
IA
lAB
QA
QAB
d-$ AGND
=
IMRST ( )
STB
:g
Register
RD ATA Data Input
RCLK
TSTB
PD2B( )~—power saving
PDIB( )_mode select
VBIAS( IR]=
OO56-E-1O 1995/07
-16-
ASAHI KASEI
H Packagesize
[AK23911
24 Pin VSOP
TJnit:nlm
*7.8 0“1
r7
24
RMUIM~
13
A
n
0q
In
*
Y
1-tltltltltmf 12
+0.1
0.22-0.05 L~65 0.12
G
Note: Dimensions with a * do not
include arange remnant. *O-10”
Deta i I o f A
[Material] Resin :LowStressType EpoxyResin
Lead Frame:42Alloy
OO56-E-1O -17- 1995/07
ASAHI KASEI [AK23911
Package 1
■larking
[XXXYS Content]
xxx: Manufacturing Data
Last d,igit of ADyear, 2digitsof week number.
Y: ManufacturingLot Number
(UsingA-Z Alphabet,withoutI.O,U,Z)
s: AssemblyPlantCode
OO56-E-1O -18-
Productsand productspecificationsmentionedin this data sheet are subject
to changewithoutnoticedue to productimprovements. Please understandthat
ASAHI KASEI MICROSYSTEMSCo., Ltd. (AKM)shall not be held liablefor the results
of using this product under conditions other than those specified in this data
sheet.
AIso, PleaSE! note that this company shall not be held liable frjr infringement
of patent rights, industrial ownership Or Other rights Of any third party
regarding the use of information or drawings included in this data sheet.
Furthermore,in the case that the product described in this data sheet is
specified as astrategic product under the provisions Of the foreign exchange
and foreign trade control laws of Japan (including services), it is necessary
to obtain an export permit in accordance with the specified laws in the event
of import.
