ees A128 C256 Features Fast Read Access Time - 150ns e Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer e Fast Write Cycle Times Page Write Cycle Time: 3.0ms or 10ms maximum 1 to 64 Byte Page Write Operation Low Power Dissipation 80mA Active Current 200;:A CMOS Standby Current * Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 104 or 10 Cycles Data Retention: 10 years Single 5V + 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Full Military, Commercial, and Industrial Temperature Ranges e#eee Description The AT28C256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256k of memory is organized as 32,768 words by 8 bits. Manufactured with Atmels advanced non-volatile CMOS technology, the device offers access times to 150ns with power dissipation of just 440mW. When the device is deselected, the CMOS standby current is less than 200A. The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are inter- nally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of 1/07. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmels 28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EPROM for device iden- tification or tracking. Pin Configurations AT ALA4VCG_A13 Al2 NC WE. 1 2 3 Pin Name Function AB se te Ag 4 AS Ag 5 AQ -A14 Addresses Aa All 8 = Ag NC 7 CE Chip Enable A2 OE 8 = Al A1O 9 OE Output Enable AO cE NC vo7 WE Write Enable voo vos 1415161718 1920 OO - /O7 Data Inputs/Outputs vor} x NO 3 4 NC No Connect GND Note: PLCC package pins | and 17 are DON'T CONNECT. AlMEt 256K (32K x 8) Paged CMOS E7PROM 2-117AIMEL Block Diagram DATA INPUTS/OUTPUTS vi _ OND VOO - 07 __ titttttt GE _.| OFCE || DATALATCH WE AND WE = * LOGIC , | INPUT/OUTPUT cE _- BUFFERS DECODER |-|__Y-GATING ADDRESS | Mar nix INPUTS DECODER | Device Operation READ: _The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance siate whenever CE or OE is high. This dual line control gives desig- ners flexibility in preventing bus contention. WRITE: A low pulse_on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The ad- dress is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. PAGE WRITE MODE: The page write operation of the AT28C256 allows one to 64 bytes of data to be loaded into the device and then simultaneously written during the internal programming period. After the first data byte has been loaded into the device successive bytes may be loaded in the same man- ner. Each new byte to be written must have its high to low tran- sition on WE (or CE) within 150ps of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 1501s of the last low to high transition, the load period will end and the internal programming period will start. A6 to Al4 specify the page address. The page address must be valid during each high to low transition of WE (or CE). AO to AS are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be changed within the same load period. Only bytes which are specified for writing will be written, unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data on 1/07. Once the write cycle has been completed, tue data is valid on all outputs, and the next cycle may begin. DATA Polling may begin at any time during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C256 provides another method for determining the end of a write 2-118 IDENTIFICATION cycle, During a write operation, successive attempts to read data from the device will result in /O6 toggling between one and zero. Once the write has completed, 1/06 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during the write cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent writes to the AT28C256 in the fol- lowing ways: (a) Vcc sense if Vcc is below 3.8V (typical) the write function is inhibited. (b) Vcc power on delay once Vcc has reached 3.8V the device will automatically time out Sms (typical) before allowing a write, (c) Write inhibit holding any one of OE low, CE high or WE high inhibits write cycles. (d) Noise filter pulses of less than 15ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature is available on the AT28C256. Once the software protection is enabled a software algorithm must be is- sued to the device before a write may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three write commands to specific addresses with specific data must be performed. After the software data protec- tion is enabled the same three write commands must begin each write cycle in order for the writes to occur. All software write commands must obey the page write timing specifications. Once set, the software data protection feature remains active un- less its disable command is issued. Power transitions will not reset the software data protection feature, but the software fea- ture will guard against inadvertent writes during power transi- tions. DEVICE IDENTIFICATION: An extra 64 bytes of EPROM memory are available to the user for device identification. By raising A9 to 12 + 0.5V and using address locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. AT28C256 mummeeees A 1280256 Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature... -65C to +150C All Input Voltages (including N.C. Pins) with Respect to Ground ................ -0.6V to +6.25V All Output Voltages with Respect to Ground .............. -0.6V to Vcc +0.6V Voltage on OE and A9 with Respect to Ground ............. -0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress-rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended D.C. and A.C. Operating Range periods may affect device reliability. AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35 ; Com. 0 - 70C 0c - 70C 0 - 70C Fomorure (Case) Ind. -40C - 85C ~40C - 85C -40C - 85C Mil. -55C - 125C -55C - 125C -55C - 125C -55C - 125C Voc Power Supply 5V410% 5V+10% 5V10% 5V+10% Operating Modes Mode CE OE WE te) Read VIL Vit Vi Dout Write) ViL ViH Vit DIN Standby/Write Inhibit Vin x x High Z Write Inhibit x Xx VIH Write Inhibit x Vit x Output Disable xX ViH xX High 2 Chip Erase Vit Vu VIL High Z Notes: 1. X can be Vir or Vin. 3. Va = 12.0V 0.5V. 2. Refer to A.C. Programming Waveforms. D.C. Characteristics Symbol Parameter Condition Min Max Units lu Input Load Current Vin=0V to Vcc + 1V 10 pA ILo Output Leakage Current Vuio=0V to Vcc 10 pA Isp1 Vec Standby Current CMOS CE=Vcc-.3V to Vcc + 1V Com., Ind. 200 yA Mil. 300 pA Isp2 Vec Standby Current TTL CE=2.0V to Voc + 1V 3 mA loc Vecc Active Current f=5MHz; louT=0mA 80 mA VIL Input Low Voltage 0.8 Vv Vin Input High Voltage 2.0 Vv VoL Output Low Voltage lot=2.1mMA 45 Vv VOH Output High Voltage loH=-400pLA 2.4 Vv 2-119 AIMELAIMET A.C. Read Characteristics AT28C256-15 | AT28C256-20 | AT28C256-25 | AT28C256-35 Symbol | Parameter Min Max Min Max Min Max Min Max Units tacc Address to Output Delay 150 200 250 350 ns tee | CE to Output Delay 150 200 250 350 ns toe | OE to Output Delay 0 70 80 0 100 0 100 ns tor | CE or OE to Output Float 0 50 55 0 60 0 70 ns Output Hold from OE, CE ton or Address, whichever 0 0 0 0 ns occurred first A.C. Read Waveforms ADDRESS ><] ADDRESS VALID CE tCce ~ __ ___| 1OE - OE tACC OH OUTPUT HIGH Z f OUTPUT ~ VALID Notes: 1, CE may be delayed up to tacc - tc after the address transition without impact on tacc. 2. OE may be delayed up to tce - tox after the falling edge of CE without impact on tce or by tacc - tog after an address change without impact on tacc. Input Test Waveforms and Measurement Level 3.0V AC AC DRIVING 1.5V MEASUREMENT LEVELS o.0v LEVEL tr, te < 5ns Pin Capacitance (f=1MHz T=25C) 3. tor is specified from OE or CE whichever occurs first (Cu = SpP). 4. This parameter is characterized and is not 100% tested. Output Test Load 5.0V OUTPUT PIN 1.3K L 100pF Typ Max Units Conditions CIN 6 pF Vin = OV CouT 8 12 pF Vout = 0V 2-120 AT28C256 aqueA.C. Write Characteristics Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns taH Address Hold Time 50 ns tcs Chip Select Set-up Time 0 ns {cH Chip Select Hold Time 0 ns twe Write Pulse Width (WE or GE) 100 ns tbs Data Set-up Time 50 ns toH,toEH Data, OE Hold Time 0 ns tov Time to Data Valid na twe Write Cycle Time AT28C256 10 ms AT28C256F 3.0 ms Note: 1. NR =No Restiction A.C. Write Waveforms- WE Controlled OE aa tOES tOEH ADDRESS x __ tAS) |tAH _ > WE NN. | JOON. tWPH WP. L tDV tDS-| | -tbH DATA IN A.C. Write Waveforms- CE Controlled tOES | tOEH ADDRESS xX tAS cH |} ics CE N L_ tWPH /_-___ iWP- le tDV. tDS| }-tDH fa | = al DATA IN ANRET | zaEL _ Page Mode Characteristics Symbol Parameter Min Max Units two Write Cycle Time AT28C256 10 ms AT28C256F 3.0 ms tas Address Set-up Time 0 ns TAH Address Hold Time 50 ns tos Data Set-up Time 50 ns tbH Data Hold Time 0 ns twe Write Pulse Width 100 ns tBLc Byte Load Cycle Time 150 BS tweH Write Pulse Width High 50 ns Page Mode Write Waveforms M m T {WP} tWPH 1BLC WE 4As _] Ly a Ly tAH X DATA Xvaio pata ~ x XX / BYTE 0 BYTE 1 BYTE 2 BYTE 37 BYTE 62 BYTE 63 L.twe x L. x : YT ~ Pie x : ; 1 Notes: A6 through A14 must specify the page address during each high to low transition of WE (or CE). GE must be high only when WE and CE are both low. Chip Erase Waveforms Vi CE ViL ts = ur = Spsec (min.) VIL tw = 10msec (min.) t Vu = 12.0V + 0.5V 2-122 AT28C256 mummmueeeeseen J 1280256 Software Data 1. 2. 3. other data is loaded. ve Software Data Protection Enable Algorithm Protection Disable Algorithm LOAD DATA AA LOAD DATA AA To TO ADDRESS 5555 ADDRESS 5555 1 1 LOAD DATA 55 LOAD DATA 55 To To ADDRESS 2AAA ADDRESS 2AAA 1 } LOAD DATA AO LOAD DATA 80 ADDRESS 5555 WRITES ENABLED 2 ADDRESS 5555 t } LOAD DATA XX LOAD DATA AA TO (4) TO ANY ADDRESS ADDRESS 5555 { 1 LOAD LAST BYTE LOAD DATA 55 TO TO LAST ADDRESS ENTER DATA ADDRESS 2AAA PROTECT STATE } LOAD DATA 20 TO ADDRESS 5555 EXIT DATA Notes for software program code: T PROTECT STATE Data Format: 1/07 - /O0 (Hex); LOAD DATA XX Address Format: Al4 - AO (Hex). 4 Write Protect state will be activated at end of write even if no ANY ADDRESS } Write Protect state will be deactivated at end of write period LOAD Last BYTE even if no other data is loaded. . 1 to 64 bytes of data are loaded. LAST ADDRESS Software Protected Write Cycle Waveforms i. A OE \N [\_ [OO ce VS \VSNIVINS NS __ tWR tWPH , = hy WE tAS tAH , AO-AS on ADDRESS , , Z 5555 2AAA 5555 Z fn A6-A14 6 xX PAGE ADDRESS, Z 1DS ZL L af DATA X as s Km X X__X s BYTE 0 BYTE 62 BYTE 63 wo- Notes: AG through Al4 must specify the page address during each high to low transition of WE (or CE) after the software code has been entered. OE must be high only when WE and CE are both low. AIMET @) 2-123AIMEL Data Polling Characteristics Symbol Parameter Min Typ Max Units tbH Data Hold Time 0 ns toEH OE Hold Time 0 ns toE OE to Output Delay 100 ns twa Write Recovery Time 0 ns Note: 1. These parameters are characterized and not 100% tested. Data Polling Waveforms ga WE | / mu Toggle Bit Characteristics Symbol Parameter Min Typ Max Units toy Data Hold Time 10 ns tOEH OE Hold Time 10 ns toe OE to Output Delay 100 ns toeHP OE High Pulse 150 ns twR Write Recovery Time 0 ns Note: 1. These parameters are characterized and not 100% tested. Toggle Bit Waveforms WE Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of 1/06 will vary. 3. Any address location may be used but the address should not vary. 2-124 AT28C256 suumQOn--937+702 a0o- oOo QOon--MBs0 2 NORMALIZED SUPPLY CURRENT vs. AT28C256 NORMALIZED SUPPLY CURRENT vs. TEMPERATURE be SUPPLY VOLTAGE nt N m 12 N 1 ~ 2 1.0 PS * o8 _ | = I a ee -55 28 36 65 $5 125 450 475 5.00 5.25 Temperature (C) NORMALIZED SUPPLY CURRENT vs. 10 08 07 06 ADDRESS FREQUENCY Vec = 5V T= 25C 1 2 3 4 Frequency (MHz) AIMEL Supply Voltage (V) 2-125AIMEL Ordering Information tacc loc (MA) . . (ns) Active | Standby Ordering Code Package Operation Range 150 80 0.2 AT28C256(E,F)-15DC 28D6 Commercial AT28C256(E,F)-15FC 28F (0C to 70C) AT28C256(E,F}-15C 32J AT28C256(E,F)-15LC 32L AT28C256(E,F)-15PC 28P6 AT28C256(E,F)-15UC 28U AT28C256(E,F)-15D! 28D6 Industrial AT28C256(E,F)-15Fl 28F (-40C to 85C) AT28C256(E,F)-15Jl 32J AT28C256(E,F)-15L1 32L AT28C256(E,F)-15PI 28P6 AT28C256(E,F)-15ul 28U 150 80 0.3 AT28C256(E,F)-15DM 28D6 Military AT28C256(E,F)-15FM 28F (-55C to 125C) AT28C256(E,F)-15LM 32L AT28C256(E,F)-15UM 28U AT28C256(E,F)-15DM/883 28D6 Military/883C AT28C256(E,F)-15FM/883 28F Class B, Fully Compliant AT28C256(E,F)-15LM/883 32L (-55C to 125C) AT28C256(E,F)-15UM/883 28U 200 80 0.2 AT28C256(E,F)-20DC 28D6 Commercial AT28C256(E,F)-20FC 28F (0C to 70C) AT28C256(E,F)-20JC 32J AT28C256(E,F)-20LC 32L AT28C256(E,F)-20PC 28P6 AT28C256(E,F)-20UC 28U AT28C256(E,F)-20D! 28D6 Industrial AT28C256(E,F)-20FI 28F {-40C to 85C) AT28C256(E,F)-20JI 32J AT28C256(E,F)-20LI 32b AT28C256(E,F)-20PI 28P6 AT28C256(E,F)-20UI 28U 200 80 0.3 AT28C256(E,F)-20DM 28D6 Military AT28C256(E,F)-20FM 28F (-55C to 125C) AT28C256(E,F)-20LM 32L AT28C256(E,F)-20UM 28U AT28C256(E,F)-20DM/883 28D6 Military/883C AT28C256(E,F)-20FM/883 28F Class B, Fully Compliant AT28C256(E,F)-20LM/883 32L (-55C to 125C) AT28C256(E,F)-20UM/883 28U 250 80 0.2 AT28C256(E,F)-25DC 2806 Commercial AT28C256(E,F)-25FC 28F (0C to 70C) AT28C256(E,F}-255C 32J AT28C256(E,F)-25LC 32L AT28C256(E,F)-25PC 28P6 AT28C256(E,F)-25UC 28U AT28C256-W DIE 2-126 AT28C256 Iees AT 8 C256 Ordering Information tacc Iec (mA) Ordering Code Package Operation Range {ns) Active Standby "9 9 pera 9 250 80 0.2 AT28C256(E,F)-25DI 28D6 Industrial AT28C256(E,F)-25F} 28F (-40C to 85C) AT28C256(E,F)-25J1 32J AT28C256(E,F)-25LI 32L AT28C256(E,F)-25Pl 28P6 AT28C256(E,F)-25UI 28U 250 80 0.3 AT28C256(E,F)-25DM 28D6 Military AT28C256(E,F)-25FM 28F (-55C to 125C) AT28C256(E,F)-25LM 32L AT28C256(E,F)-25UM 28U AT28C256(E,F)-25DM/883 28D6 Military/883C AT28C256(E,F)-25FM/883 28F Class B, Fully Compliant AT28C256(E,F)-25LM/883 32L (-58C to 125C) AT28C256(E,F)-25UM/883 28U 300 80 0.3 AT28C256(E,F)-30DM/883 28D6 Military/883C AT28C256(E,F)-30FM/883 28F Class B, Fully Compliant AT28C256(E,F)-30LM/883 32L (-55C to 125C) AT28C256(E,F)-30UM/883 28U 350 80 0.3 AT28C256(E,F)-35DM/883 28D6 Military/883C AT28C256(E,F)-35FM/883 28F Class B, Fully Compliant AT28C256(E,F)-35LM/883 32L (-55C to 125C) AT28C256(E,F)-35UM/883 28U 150 80 0.35 5962-88525 07 UX 28U Military/883C 5962-88525 07 XX 28D6 Class B, Fully Compliant 5962-88525 07 YX 32L (-55C to 125C) 5962-88525 07 ZX 28F 5962-88525 06 UX 28U Military/883C 5962-88525 06 XX 28D6 Class B, Fully Compliant 962-88525 06 YX 32L (-55C to 125C) 5962-88525 06 ZX 28F 200 80 0.35 5962-88525 04 UX 28U Military/883C 5962-88525 04 XX 28D6 Class B, Fully Compliant 5962-88525 04 YX 32L (-55C to 125C) 5962-88525 04 ZX 28F 250 80 0.35 5962-88525 03 UX 28U Military/883C 5962-88525 03 XX 28D6 Class B, Fully Compliant 5962-88525 03 YX 32L (-55C to 125C) 5962-88525 03 ZX 28F 5962-88525 05 UX 28U Military/883C 5962-88525 05 XX 28D6 Class B, Fully Compliant 5962-88525 05 YX 32L (-55C to 125C) 5962-88525 05 ZX 28F 300 80 0.35 5962-88525 02 UX 28U Mititary/883C 5962-88525 02 XX 28D6 Class B, Fully Compliant 5962-88525 02 YX 32L (-55C to 125C) 5962-88525 02 ZX 28F ANMEL oanAImEt Ordering Information tace lec (mA) Ordering Code Package Operation R (ns) | Active | Standby 9 P ange 350 80 0.35 5962-88525 01 UX 28U Military/883C 5962-88525 01 XX 28D6 Class B, Fully Compliant 962-88525 01 YX 32L (-55C to 125C) 5962-88525 01 2X 28F Package Type 28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack} 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28U 28 Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Biank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 2-128 AT28C256 ennunun