CY7C1338B-90AI - Cypress Semiconductor Corp.

PRELIMINARY

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

CY7C1338B

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

March 22, 2000

Features

• Supports 117-MHz microprocessor cache systems with

zero wait states

• 128K by 32 com m on I/ O

• Fast clock-to-output times

—7.5 ns (117-MHz version)

• Two- bit wraparound counter supporting eit her inter-

leaved or linear bu rst sequence

• Separate processor and controller address strobes pro-

vide direct interf ace w it h the processor and external

cache controller

• Synchronous self-timed write

• Asy nchronous output enable

•3.3V I/Os

• JEDEC-standard pinout

• 100-pi n TQFP packaging

• ZZ “sleep” mode

• Available in Commercial and Industr ial Temperatures

Functional Descri pti on

The CY7C1338B is a 3.3V, 128K by 32 synchronous cache

RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MH z version). A 2-bit on- chip counter cap-

tures the fir st address in a burst and i ncrements the addr ess

automatic ally for the rest of the burst access.

The CY7C1338B allows both interleaved and linear burst se-

quences, selected b y the MODE input pin. A HIGH selects an

interlea ved bu rst sequence , while a LO W sele cts a linear burst

sequence. Burst accesses can be initiated with the processor

Address Strobe (ADSP) or the cache controller Address

Strobe (ADSC) inputs. Address advancement is controlled by

the Address Advancement (ADV) input.

A synchr onous self -timed write mechanism is provi ded to si m-

plify the wri te inter face. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three- state contr ol.

Selec tion Guide

-117 -100 -90 -50

Maximum Access Time (ns) 7.5 8.0 8.5 11.0

Maximum Operatin g Current (mA) 350 325 300 250

Maxim um Standby Current (mA) 2.0 2.0 2.0 2.0

Pentium is a registered trademark of Intel Corporation.

CLK

ADV

ADSC

A[16:0]

BWE

BW0

CE1

CE3

CE2

BURST

COUNTER

DQ[31:24]

BYTEWRITE

REGISTERS

ADDRESS

INPUT

REGISTERS

128K X 32

MEMORY

ARRAY

CLK

CLR

SLEEP

CONTROL

DQ[23:16]

BYTEWRITE

REGISTERS

D Q

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

D Q

ENABLE

CLK

32 32

(A0,A1)2

MODE

ADSP

Logic Block Diagram

DQ[31:0]

BW1

BW2

BW3

CY7C1338B

PRELIMINARY

Pin Configuration

100-Lead TQFP

DNU

VSS

VDD

DNU

A10

A11

A12

A13

A14

A16

DQ14

VDDQ

VSSQ

DQ13

DQ12

DQ11

DQ10

VSSQ

VDDQ

DQ9

DQ8

VSS

VDD

DQ7

DQ6

VDDQ

VSSQ

DQ5

DQ4

DQ3

DQ2

VSSQ

VDDQ

DQ1

DQ0

DQ16

DQ17

VDDQ

VSSQ

DQ18

DQ19

DQ20

DQ21

VSSQ

VDDQ

DQ22

DQ23

VSSQ

VDD

VSS

DQ24

DQ25

VDDQ

VSSQ

DQ26

DQ27

DQ28

DQ29

VSSQ

VDDQ

DQ30

DQ31

CE1

CE2

BW3

BW2

BW1

BW0

CE3

VDD

VSS

CLK

BWE

ADSP

100

BYTE0

BYTE2

A15

ADV

ADSC

MODE

DNU

CY7C1338B

BYTE1

DQ15

BYTE3

CY7C1338B

PRELIMINARY

Pin Descriptions

TQFP Pin

Number Name I/O Description

85 ADSC Input-

Synchronous Address Strobe from Controll er, sam pled on the rising edge of CLK. When asserted

LO W, A[16:0] is ca ptured in the address registers. A[1:0] are also load ed into the burst

counter. When ADSP and ADSC are both asser ted, only ADSP is recognize d.

84 ADSP Input-

Synchronous Address Strobe from Processor, sampl ed on the ris ing edge of CLK. When asserted

LO W, A[16:0] is ca ptured in the address registers. A[1:0] are also load ed into the burst

counter. When ADSP and ADSC are bot h ass erted, o nly ADSP i s recogn ized . ASDP

is ignored when CE1 is deasserted HIGH.

36, 37 A[1:0] Input-

Synchronous A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as

well as being used to acc ess a particular memory locati on in the memory array.

49−44,

81–82,

99–100,

32–35

A[16:2] Input-

Synchronous Address Inputs used in conj unction with A[1:0] to select one of the 64K address loca-

tions. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled a ctive ,

and ADSP or ADSC is active LOW.

96–93 BW[3:0] Input-

Synchronous Byte Write Select Inputs, activ e LOW. Qual ified with BWE to conduct byte writes.

Sampled on the rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8] and

DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ[31:24] and DP3. See Write

Cycle Descri ptions table for further details .

83 ADV Input-

Synchronous Advance Inpu t used to advance the on- chip address cou nter . When LOW the internal

burs t c ounter is adv an ced in a b urst se quenc e. The b urst s equence i s se lected using

the MODE input.

87 BWE Input-

Synchronous Byte W rite Ena ble Input, acti ve LO W. Sampled on t he rising edge of CL K. This signal

must be asserted LOW to conduct a b yte write.

88 GW Input-

Synchronous Global Writ e Input, active LOW. Sa mp led on the rising edge of CLK. This si gnal is

used to conduct a global writ e, independent of the st ate of BWE and BW[3:0]. Globa l

writes override byte writes.

89 CLK Input-Clock Clock Input. Used to capt ure all synchronous inputs to the device.

98 CE1Input-

Synchronous Chip Enable 1 Input, active LOW. Sam pled on the rising edge of CLK. Used in con-

junction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP.

97 CE2Input-

Synchronous Chip Enable 2 Input, active HIGH . Sampled on the rising edge of CLK. Used in con-

junction with CE1 and CE3 to select/deselect the device.

92 CE3Input-

Synchronous Chip Enable 3 Input, active LOW. Sam pled on the rising edge of CLK. Used in con-

junction with CE1 and CE2 to select/deselect the device.

86 OE Input-

Asynchronous Output Enable, asynchronous input, active LOW . Controls the direction of the I/O pins.

When LOW, the I/O pins behave as out puts. When deasserted HIGH, I/O pi ns are

three- stated, and act as input data pins.

64 ZZ Input-

Asynchronous Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power

standb y mode in which all other inputs are ignored, b ut the data in the memory arra y

is main tained. Leaving ZZ floating or NC will default t he device into an active state.

31 MODE -Mode Input. Sel ects the burst order of the device. Tied HIGH selects the int erl eaved

burst order. Pull ed LOW select s the linear burst order. When left floating or NC, de-

faults to interl eaved b urst order.

29–28,

25–22,

19–18,

13–12,

9–6, 3-2,

79–78,

75–72,

69–68,

63–62,

59–56,

53–52

DQ[31:0] I/O-

Synchronous Bidir ectional Data I/O Lin es. As inputs, they feed into an on-chip data re gister that is

triggered b y the ri sing edge of CLK. As o utputs , t he y deliv e r the dat a contai ned i n t he

memory location spe cified by A[16:0] during the pr evious clock rise of the read cycle.

The direction of the pins is controlled by OE i n conjuncti on with the internal contr ol

logic . When O E is asse rted LOW, the pins behave as outputs . When HIGH, DQ[31:0]

and DP[3:0] are placed in a thre e-state condit ion. The outputs are automaticall y

three-stated when a WRITE cycle i s detected.

15, 4 1, 65,

91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

CY7C1338B

PRELIMINARY

Functional Description (continued)

Single Write Accesses Init iated by ADSP

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted

active, and (2) ADSP is asserted LOW. The addresses pre-

sented are loaded into the address register and the burst

count er/con trol logic and deli ver ed t o the RAM cor e. The wri te

inputs (GW, BWE, and BW[3:0]) are ignored during this first

clock cycle. If the write inputs are asserted active ( see W rite

Cycle Descr iptions table for appropr iate states that indicate a

write) on the next clock rise, the appropriate data will be

latched and written into the device. Byte writes are allowed.

During byte writes, BW0 controls DQ[7:0], BW1 controls

DQ[15:8], BW2 controls DQ[23:16], and BW3 control s DQ[31:24].

All I/Os are three-stated during a byte write. Since this is a

common I/O device, the asynchronous OE input signal must

be deasser ted and the I/Os must be three-stated pri or to the

presentation of data to DQ[31:0]. As a safety precaution, the

data lines ar e three-stated once a write cycle i s detected, re-

gardless of the state of OE .

Single Wri te Accesses Initiated by ADSC

This writ e acc ess is i nitiat ed when the f oll owing c ondit ions ar e

satisfied at clock rise: (1) CE1, CE 2, and CE3 are all asserted

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the write input signals (GW, BW E, and BW[3:0])

indi cate a write access. ADSC is ignored if ADS P is active LOW.

The addr ess es presen ted are loa ded int o th e address regist er

and the burst counter/cont rol logic and delivered to the RAM

core. The informatio n presented to DQ[31:0] will be written into

the spe cified add ress lo cation. Byte writes are allow ed. During

byte writes, BW0 contr ols DQ[7:0], BW1 control s DQ[15:8], BW2

controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os a re

thr ee-stat ed when a write i s detec ted, ev en a by te write. Si nce

thi s is a comm on I/O de vice, t he asynchronous OE input signal

mu st be deass erte d and the I /Os mus t be thr ee-st ated prio r to

the p resentation of data to DQ[31:0]. As a safety precaution, the

data lines ar e three-stated once a write cycle i s detected, re-

gardless of the state of OE .

Single Read Accesses

A single read access is initiated whe n the follo wing conditi ons

are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-

serted active, and (2) ADSP or ADSC is asserted LOW (if the

access is initiated by ADSC, the wri te input s must be deassert-

ed during this first cycle). The address presented to the ad-

dress inputs is latched into the address register and the burst

counter/control lo gic and presented to the m em ory core. If the

OE input is asserted LO W , the request ed data will be av ailabl e

at the data outputs a maximum to tCDV after clock rise. ADSP

is i gnored if CE1 is HIGH .

Burst Se quences

The CY7C1338B provides an on-chip 2-bit wraparound burst

counter inside the SRAM. The burst counter is fed by A[1:0],

and can follow either a linear or interleaved burst order. The

burst order is determined by the state of the MODE input. A

LO W on MODE wi ll se lect a line ar bu rst se quenc e. A HI GH on

MODE will select an interleaved burst order. Leaving M ODE

unconnected will cause the device to default to a interleaved

burst sequence .

17, 4 0, 67,

90 VSS Ground G round f or the I/O circu it ry of the de vice. Should be connected to gr ound of the sy s-

tem.

5, 10, 14,

21, 2 6, 55,

60, 71, 76

VSSQ Ground G round f or the de vice. Should be connected to gr ound of the sy stem.

4, 11, 20,

27, 5 4, 61,

70, 77

VDDQ I/O Po wer

Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

1,16, 30,

50–51, 66,

NC -No connects.

38, 3 9, 42,

43 DNU -Do not use pins. Should be left unconnected or tied LOW.

Pin Descriptions (continued)

TQFP Pin

Number Name I/O Description

Table 1. Counter Implementation for the Intel

Pentium®/80486 Processor’s Sequence

First

Address Second

Address Third

Address Fourth

Address

AX + 1 , AxAX + 1, AxAX + 1, AxAX + 1 , Ax

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Table 2. Counter Implementation for a Linear Seque nce

First

Address Second

Address Third

Address Fourth

Address

AX + 1, AxAX + 1, AxAX + 1, AxAX + 1, A x

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

CY7C1338B

PRELIMINARY

Sleep Mode

The ZZ in put pin is an asynchronous inp ut. Asse rting ZZ HIGH

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to ent er into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed. Ac-

cesses pending when entering the “sleep” mode are not con-

sidered valid nor is the completion of the operation guaran-

teed. The device must be deselected prior to entering the

“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain

inactive for the duration of tZZREC after the ZZ input returns

LO W. Leaving ZZ unconnected defaults the device int o an ac-

tive st ate.

Cycle Description Table[1, 2, 3]

Cycle Description ADD

Used CE1CE3CE2ZZ ADSP ADSC ADV WE OE CLK DQ

Deselected Cyc le, Power- down None H X X L X L X X X L-H High-Z

Deselected Cyc le, Power- down None L X L L L X X X X L-H High-Z

Deselected Cyc le, Power- down None L H X L L X X X X L-H High-Z

Deselected Cyc le, Power- down None L X L L H L X X X L-H High-Z

Deselected Cyc le, Power- down None X X X L H L X X X L-H High-Z

Snooze M ode, P ower-down None X X X H X X X X X X High-Z

Read Cycle, Begin Burst External L L H L L X X X L L -H Q

Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z

Write Cycl e, Begin Burst External L L H L H L X L X L-H D

Read Cycle, Begin Burst External L L H L H L X H L L -H Q

Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z

Write Cycl e, Continue Bur st Next X X X L H H L L X L-H D

Write Cycl e, Continue Bur st Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z

Write Cycl e, Suspend Burst Current X X X L H H H L X L-H D

Write Cycl e, Suspend Burst Current H X X L X H H L X L-H D

Notes:

1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.

2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE

is a “Don't Care” for the remainder of the write cycle.

3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.

CY7C1338B

PRELIMINARY

Maximum Ratings

(Above which the usefu l l ife ma y be impaired. For use r gui de-

li nes, not tested .)

Storage Temperature ... ..... .............. .. ........ .. .–65°C to +150°C

Ambient Temperature with

Power Applied...............................................–55°C to +125°C

Supply Voltage on VDD Rel ativ e to GND..... ...........–0.5V to +4.6V

DC Voltage Applied t o Output s

in High Z State[5]...............................................–0. 5V to V DD + 0.5V

DC Input Voltage[5]...........................................–0.5V to V DD + 0.5V

Cu r re n t in to Outp ut s (L OW ) ..... ..... ....... ..... ..... ..... ....... .. 20 mA

Static Discharge Voltage.......... ..... .. ..... ..... ..... .. ..... ... >2001V

(per MIL- STD-883, Method 3015)

Latch-Up Current... ......... ..... ..... ..... ............ ..... .. ...... >200 mA

Notes:

4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.

5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.

6. TA is the ca se temper atu re.

Wr i te C ycl e D escri p t i o n s[1, 2, 3, 4]

Function GW BWE BW3BW2BW1BW0

Read 11XXXX

Write Byte 0 - DQ[7:0] 101110

Write Byte 1 - DQ[15:8] 101101

Write Bytes 1, 0 101100

Write Byte 2 - DQ[23:16] 101011

Write Bytes 2, 0 101010

Write Bytes 2, 1 101001

Write Bytes 2, 1, 0 101000

Write Byte 3 - DQ[31:24] 100111

Write Bytes 3, 0 100110

Write Bytes 3, 1 100101

Write Bytes 3, 1, 0 100100

Write Bytes 3, 2 100011

Write Bytes 3, 2, 0 100010

Write Bytes 3, 2, 1 100001

Write All Bytes 100000

Write All Bytes 0 XXXXX

Operating Range

Range Ambient

Temperature[6] VDD VDDQ

Com’l 0°C to +70°C3.135V t o 3.6V 2.375V to VDD

Ind’l-40°C to +85°C3.135V to 3.6V 2.375V to VDD

CY7C1338B

PRELIMINARY

Electrical Characteristics Over the Operating Range

P arameter Des cri ption Test Conditi ons Min. Max. Unit

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA 1.7 V

VOL Output LOW Vo ltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA 0.7 V

VIH Input HIGH Voltage 1.7 VDD +

0.3V V

VIL Input LOW Voltage[5] –0.3 0.8 V

IXInput Load Current

(except ZZ and MODE) GND ≤ VI ≤ VDDQ −11µA

Input Current of MODE Input = VSS –30 µA

Input = VDDQ 5µA

Input Current of ZZ Input = VSS –5µA

Input = VDDQ 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ V DD, Output Disabled –55µA

IOS Output Short Circuit Current[7] VDD = Max ., V OUT = GND –300 mA

IDD VDD Operating Supply Current VDD = Max ., IOU T = 0 mA,

f = fMAX =1/tCYC 8.5-ns cycle, 117 MHz 350 mA

10-ns cycl e, 100 MHz 32 5 mA

11-ns cycle, 90 MHz 300 mA

20-ns cycle, 50 MHz 250 mA

ISB1 Automatic CE Power-Down

Current—TTL In puts Max. VDD, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL,

f = fMAX = 1/tCYC, inputs switch-

ing

8.5-ns cycle, 117 MHz 110 mA

10-ns cycl e, 100 MHz 10 0 mA

11-ns cycle, 90 MHz 90 mA

20-ns cycle, 50 MHz 80 mA

ISB2 Automatic CE Power-Down

Current —CMOS Input s Max. VDD, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0, inputs static

All speeds 10 mA

ISB3 Automatic CE Power-Down

Current—CMOS Inputs Ma x. VDD, De vice Deselected,

VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,

f = fMAX, in puts s w itch ing

8.5-ns cycle, 117 MHz 85 mA

10-ns cycl e, 100 MHz 75 m A

11-ns cycle, 90 MHz 65 mA

20-ns cycle, 50 MHz 55 mA

ISB4 Automatic CE Power-Down Current

—CMOS Inpu ts Max. VDD, Device Deselected,

VIN ≥ V DD – 0.3V or VIN ≤ 0.3V, f =

0, inputs static

All speeds 18 mA

Note:

7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

CY7C1338B

PRELIMINARY

ZZ Mode Elec trical Characteristics

Parameter Description Test Conditions Min Max Unit

ICCZZ Snooze mode

standby current ZZ > VDD − 0.2V 3 mA

tZZS Device operation to

ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ re c ove ry time ZZ < 0.2 V 2t CYC ns

Capacitance[8]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 5.0V 5.0 pF

CI/O I/O Capacitance 8.0 pF

Note:

8. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

3.0V

GND

90%

10% 90%

10%

≤3.0 ns ≤3.0 ns

OUTPUT

R1=317Ω

R2=351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

ALL INPUT PULSES

OUTPUT

RL=50Ω

Z0=50Ω

VL=1.5V

3.3V

CY7C1338B

PRELIMINARY

Switching Characteristics Over the Operating Range[9]

Parameter Description

-117 -100 -90 -50

Min. Max. Min. Max. Min. Max. Min. Max. Unit

tCYC Clo ck Cy cle Tim e 8. 5 10 1 1 2 0 ns

tCH Clock HIGH 3.0 4.0 4.5 4.5 ns

tCL Clock LOW 3.0 4.0 4.5 4.5 ns

tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns

tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCDV Data Output Valid After CLK Rise 7.5 8.0 8.5 11.0 ns

tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2 .0 ns

tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 n s

tADH ADSP, ADSC Hold After CLK Rise 0 .5 0.5 0.5 0.5 n s

tWES BWS[1:0], GW,BWE Set-Up Befor e CLK Ri se 2.0 2.0 2.0 2.0 ns

tWEH BWS[1:0], GW,BWE Hold A fter CLK Ri s e 0.5 0.5 0.5 0.5 n s

tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns

tADVH ADV Hold Af ter CLK Rise 0 .5 0.5 0.5 0.5 ns

tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns

tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns

tCEH Ch ip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCHZ Clock to H i g h-Z [10, 11] 3.5 3.5 3.5 3.5 ns

tCLZ Clock to Low-Z[10, 11] 0000ns

tEOHZ OE HIGH to Output High- Z[10, 12] 3.5 3.5 3.5 3.5 ns

tEOLZ OE LOW to Outp ut Low-Z[10, 12] 0000ns

tEOV OE LOW to Outp ut Valid 3.5 3. 5 3.5 3.5 ns

Notes:

9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and

output loading of the specified IOL/IOH and loa d capaci tance. Show n in ( a) and ( b) of AC test l oads .

10. tCHZ, tCLZ, tEOHZ, a nd tEOLZ are specified wi th a l oad capacit ance of 5 pF as in part (b) of A C Te st Loads. Transition is measur ed ± 200 mV f rom st eady-stat e v oltage .

11. At any given voltage and temperature, tCHZ (max) is les s than tCLZ (min).

12. This parameter is sampled and not 100% tested.

CY7C1338B

PRELIMINARY

Timing Diagram s

Write Cycle Timing[13, 14]

Notes:

13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).

14. WDx stands for Write Data to Address X.

ADSP

CLK

ADSC

ADV

ADD

Data-

tCYC

tCH

tCL

tADS

tADH

tADS tADH

tADVS tADVH

WD1 WD2 WD3

tAH

tAS

tWS tWH tWH

tWS

tCES tCEH

2b 3a

Sin g le Write Burst W rite

Unselected

ADSP ignored with CE1 inactive

CE1 masks AD SP

= D ON ’T CARE

= UNDEFINED

Pipelined Write

2a 2c 2d

tDH

tDS

High-Z

Unselected with CE2

ADV Must Be Inactive for ADSP Write

ADSC initiated write

CY7C1338B

PRELIMINARY

Read Cycle Timin g[13, 15 ]

Note:

15. RDx stands for Read Data from Address X.

Timing Diagram s (continued)

ADSP

CLK

ADSC

ADV

ADD

CE1

CE2

CE3

2a 2c

Data Out

tCYC tCH

tCL

tADS tADH

tADS

tADH

tADVS

tADVH

RD1 RD2 RD3

tAH

tAS

tWS tWH

tWH

tWS

tCES tCEH

tCDV

tEOV

2b 2c 2d 3a

tOEHZ tDOH

tCLZ tCHZ

Singl e Read Burst Read Unselected

ADSP ignored with CE1 i nactive

Suspend Burst

CE1 masks ADSP

= DON’T CARE = UNDEFINED

Pipel ined Read

ADSC initiated read

Unselected with C E2

CY7C1338B

PRELIMINARY

Read/W rite Cyc le Timin g

Timing Diagram s (continued)

tAH

tAS

WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).

tCLZ

tCHZ

CE is the combi nation of CE2 and CE3. All chip selects need to be active in order to select

the devic e. RAx stands for Read Address X, WAx stands for Writ e Address X, Dx stands for Data-i n X,

tDOH

CLK

ADD

CE1

Data

BCD

ADSP

ADSC

ADV

Q(A) Q(B) Q

(B+1) Q

(B+2) Q

(B+3) Q(B) D(C) D

(C+1) D

(C+2) D

(C+3) Q(D)

tCYC

tCH tCL

tADS tADH

tADVH

tADVS

tCEH

tCES

tWEH

tWES

tCDV

Dev ic e or igin ally

deselected

ADSP ignored

with CE1 HI GH

tEOHZ

Qx stands for Data-out X.

In/Out

CY7C1338B

PRELIMINARY

Timing Diagram s (continued)

In/Out

tAS

= DON’T CARE = UNDEFINED

WE is th e combination of BWE, B W[1:0], and GW to define a wri te cycle (see Write Cycle Descripti ons tabl e).

tCLZ

tCHZ

CE is the co mb ination of CE2 and CE3. All chi p selects need to be acti ve in orde r to select

the device. RAx stands for Read Address X, W Ax stands for Write Address X, Dx stands for Data-in X,

tDOH

CLK

ADD

CE1

Data

ADSP

ADSC

ADV

Q(A) Q(B) Q(D) D(C)

D (E) D (F) D (G)

tCYC

tCH tCL

tADS tADH

tCEH

tCES

tWEH

tWES

tCDV

Pipeline Timing

Device originally

deselected

ADSP ignored

with CE1 HIGH

Qx stands for Data-out X.

Q(C)

EFGH

D (H)

CY7C1338B

PRELIMINARY

Timing Diagram s (continued)

three-state

I/Os

tEOHZ tEOV

tEOLZ

OE Switching Waveforms

CY7C1338B

PRELIMINARY

Note:

16. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.

17. I/Os are in three-state when exiting ZZ “sleep” mode.

Timing Diagram s (continued)

ADSP

CLK

ADSC

CE1

CE3

LOW

HIGH

ZZ tZZS

tZZREC

ICC ICC(active)

Three-state

I/Os

ZZ Mode Timing [16, 17]

CE2

ICCZZ

HIGH

CY7C1338B

PRELIMINARY

of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document #: 38-00939–**

Orde ring Information

Speed

(MHz) Ordering Code Package

Name Package Typ e Operating

Range

117 CY7C1338B-117AC A1 01 100-Lead Thin Quad Fl at Pac k Commer cial

100 CY7C1338B-100AC A1 01 100-Lead Thin Quad Fl at Pac k

90 CY7C1338B-90AC A1 01 100-Lead Thin Quad Fl at Pac k

50 CY7C1338B-50AC A1 01 100-Lead Thin Quad Fl at Pac k

100 CY7C1338B-100AI A101 100-Lead Thin Quad Fl at Pac k Industrial

90 CY7C1338B-90AI A1 01 100-Lead Thin Quad Fl at Pac k

50 CY7C1338B-50AI A1 01 100-Lead Thin Quad Fl at Pac k

Package D i ag ra m

100-Pin Thin Plasti c Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A