_______________General Description
The MAX530 is a low-power, 12-bit, voltage-output digi-
tal-to-analog converter (DAC) that uses single +5V or
dual ±5V supplies. This device has an on-chip voltage
reference plus an output buffer amplifier. Operating cur-
rent is only 250µA from a single +5V supply, making it
ideal for portable and battery-powered applications. In
addition, the SSOP (Shrink-Small-Outline-Package) mea-
sures only 0.1 square inches, using less board area than
an 8-pin DIP. 12-bit resolution is achieved through laser
trimming of the DAC, op amp, and reference. No further
adjustments are necessary.
Internal gain-setting resistors can be used to define a
DAC output voltage range of 0V to +2.048V, 0V to
+4.096V, or ±2.048V. Four-quadrant multiplication is pos-
sible without the use of external resistors or op amps. The
parallel logic inputs are double buffered and are compati-
ble with 4-bit, 8-bit, and 16-bit microprocessors. For DACs
with similar features but with a serial data interface, refer
to the MAX531/MAX538/MAX539 data sheet.
________________________Applications
Battery-Powered Data-Conversion Products
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
Microprocessor-Controlled Calibration
____________________________Features
♦Buffered Voltage Output
♦Internal 2.048V Voltage Reference
♦Operates from Single +5V or Dual ±5V Supplies
♦Low Power Consumption:
250µA Operating Current
40µA Shutdown-Mode Current
♦SSOP Package Saves Space
♦Relative Accuracy: ±1/2LSB Max Over
Temperature
♦Guaranteed Monotonic Over Temperature
♦4-Quadrant Multiplication with No External
Components
♦Power-On Reset
♦Double-Buffered Parallel Logic Inputs
______________Ordering Information
Ordering Information continued on last page.
* Dice are tested at T
A
= +25°C, DC parameters only.
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
________________________________________________________________
Maxim Integrated Products
1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
D0/D8
VDD
ROFS
RFB
D4
D3/D11
D2/D10
D1/D9
TOP VIEW
VOUT
VSS
REFOUT
REFGND
A0
D7
D6
D5
16
15
14
13
9
10
11
12
LDAC
CLR
AGND
REFIN
DGND
CS
WR
A1
DIP/SO/SSOP
MAX530
__________________Pin Configuration
MAX530
REFOUT REFIN ROFS
2.048V
REFERENCE
POWER-ON
RESET
DAC LATCH
CONTROL
LOGIC
REFGND
AGND
CLR
A0
A1
CS
WR
LDAC
VDD
DGND
VSS
VOUT
RFB
17
14
NBL
INPUT
LATCH
D0/D8
D1/D9
D2/D10 D4
D3/D11 D6
D5 D7
NBM
INPUT
LATCH
NBH
INPUT
LATCH
24 1 234567
21
20
23
12
19
18 13 22
15
8
9
11
10
16
12-BIT DAC LATCH
________________Functional Diagram
Call toll free 1-800-998-8800 for free samples or literature.
PART TEMP. RANGE PIN-PACKAGE
MAX530ACNG 0°C to +70°C 24 Narrow Plastic DIP
MAX530BCNG 0°C to +70°C 24 Narrow Plastic DIP
MAX530ACWG 0°C to +70°C 24 Wide SO
MAX530BCWG 0°C to +70°C 24 Wide SO
MAX530ACAG 0°C to +70°C 24 SSOP
MAX530BCAG 0°C to +70°C 24 SSOP
MAX530BC/D 0°C to +70°C Dice* ±1
±1
±
1/2
±1
±
1/2
±1
±
1/2
ERROR
(LSB)
19-0168; Rev 3; 7/95
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
VDD to DGND and VDD to AGND................................-0.3V, +6V
VSS to DGND and VSS to AGND .................................-6V, +0.3V
VDD to VSS ............................................................... -0.3V, +12V
AGND to DGND........................................................-0.3V, +0.3V
REFGND to AGND........................................-0.3V, (VDD + 0.3V)
Digital Input Voltage to DGND ................... -0.3V, (VDD + 0.3V)
REFIN.................................................(VSS - 0.3V), (VDD + 0.3V)
REFOUT.............................................(VSS - 0.3V), (VDD + 0.3V)
REFOUT to REFGND................................... -0.3V, (VDD + 0.3V)
RFB ...................................................(VSS - 0.3V), (VDD + 0.3V)
ROFS .................................................(VSS - 0.3V), (VDD + 0.3V)
VOUT to AGND (Note 1) .............................................. VSS, VDD
Continuous Current, Any Input ........................................±20mA
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)......1067mW
Wide SO (derate 11.76mW/°C above +70°C) .......... 941mW
SSOP (derate 8.00mW/°C above +70°C) ..................640mW
Operating Temperature Ranges:
MAX530_C_ _ ...................................................0°C to +70°C
MAX530_E_ _ ................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10sec ) .......................... +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: The output may be shorted to VDD, VSS, DGND, or AGND if the continuous package power dissipation and current ratings
are not exceeded. Typical short-circuit currents are 20mA.
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(VDD = 5V ±10%, VSS = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33µF,
RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
CONDITIONS
Bits12NResolution
UNITSMIN TYP MAXSYMBOLPARAMETER
VDD = 5V (Note 2) ±0.5
Guaranteed monotonic LSB±1DNLDifferential Nonlinearity
LSB
±1
INLRelative Accuracy
ppm/°C3TCVOS
VDD = 5V
Unipolar Offset
Temperature Coefficient
LSB018V
OS
Unipolar Offset Error
ppm/°C1Gain-Error Temperature Coefficient
DAC latch = all 1s,
VOUT < VDD - 0.4V
(Note 2) LSB±1GE
4.5V ≤VDD ≤5.5V (Note 3)
Gain Error (Note 2)
VOUT = 2V, load regulation ≤±1LSB kΩ2Resistive Load V0V
DD - 0.4
4.5V ≤VDD ≤5.5V (Note 3)
Output Voltage Range
LSB/V0.4 1PSRRGain-Error Power-Supply Rejection
LSB/V0.4 1PSRR
Unipolar Offset-Error
Power-Supply Rejection
mA20ISC
Short-Circuit Current Ω0.2DC Output Impedance
V0V
DD - 2Reference Input Range
Code dependent (Note 4) pF10 50Reference Input Capacitance Code dependent, minimum at code 555hex kΩ40Reference Input Resistance
(Note 5) dB-80AC Feedthrough
MAX530AC/AE
MAX530BC/BE
MAX530_C/E
MAX530_C/E
STATIC PERFORMANCE
DAC VOLTAGE OUTPUT (VOUT)
REFERENCE INPUT (REFIN)
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(VDD = 5V ±10%, VSS = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33µF,
RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER
Temperature Coefficient
SYMBOL MIN TYP MAX
30
UNITS
Reference Tolerance VREFOUT
ppm/°C
2.013 2.083
DYNAMIC PERFORMANCE
V2.017 2.079
REFERENCE OUTPUT (REFOUT)
Voltage Output Slew Rate
Reference Output Resistance RREFOUT 2Ω
Power-Supply Rejection Ratio PSRR 300 µV/V
0.15 0.25 V/µs
Voltage Output Settling Time
Noise Voltage en400
25
µVp-p
µs
30 50
Digital Feedthrough 5 nV-s
68
Signal-to-Noise Plus
Distortion Ratio SINAD 68 dB
DIGITAL INPUTS (D0-D7,
LDAC
,
CLR
,
CS
,
WR
, A0, A1)
Logic High Input VIH 2.4 V
Logic Low Input VIL 0.8 V
Digital Leakage Current ±1 µA
Digital Input Capacitance 8 pF
POWER SUPPLIES
CONDITIONS
MAX530BE
MAX530BC
(Note 8)
4.5V ≤VDD ≤5.5V
TA= +25°C
To ±0.5LSB, VOUT = 2V
MAX530AC/AE
WR = VDD, digital inputs all 1s to all 0s
Unity gain (Note 5)
Gain = 2 (Note 5)
VIN = 0V or VDD
2.024 2.048 2.072TA= +25°C
VDD = 5.0V
0.1Hz to 10kHz
Positive Supply-Voltage Range VDD (Note 6) 4.5 5.5 V
Positive Supply Current IDD Outputs unloaded, all digital inputs = 0V or VDD 250 400 µA
SWITCHING CHARACTERISTICS
Address to WR Setup tAWS 5 ns
Address to WR Hold tAWH 5 ns
CS to WR Setup tCWS 0 ns
CS to WR Hold tCWH 0 ns
Data to WR Setup tDS 45 ns
Data to WR Hold tDH 0ns
WR Pulse Width tWR 45 ns
LDAC Pulse Width tLDAC 45 ns
CLR Pulse Width tCLR 45 ns
Internal Power-On Reset
Pulse Width tPOR (Note 4) 1.3 10 µs
MAX530BC/BE
Minimum Required External
Capacitor CMIN 3.3 µF
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies
(VDD = 5V ±10%, VSS = -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT,
CREFOUT = 33µF, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
4 _______________________________________________________________________________________
VDD = 5V, VSS = -5V MAX530AC/AE ±0.5
MAX530BC/BE
MAX530_C/E
Guaranteed monotonic LSB±1DNLDifferential Nonlinearity
MAX530_C/E
LSB
±1.5
INLRelative Accuracy
ppm/°C
CONDITIONS
3TCVOS
VDD = 5V, VSS = -5V
Bipolar Offset
Temperature Coefficient
LSB0±8V
OS
Bipolar Offset Error
ppm/°C1TCGain-Error Temperature Coefficient LSB±1
4.5V ≤VDD ≤5.5V
-5.5V ≤VSS ≤-4.5V (Note 3)
Gain Error
VOUT = 2V, load regulation ≤±1LSB kΩ2Resistive Load VVSS + 0.4 VDD - 0.4
4.5V ≤VDD ≤5.5V, -5.5V ≤VSS ≤-4.5V (Note 3)
Output Voltage Range
LSB/V
Bits12NResolution
0.4 1PSRRGain-Error Power-Supply Rejection
LSB/V0.4 1PSRR
Bipolar Offset-Error
Power-Supply Rejection
mA20ISC
Short-Circuit Current Ω0.2DC Output Impedance
VVSS + 2 VDD - 2Reference Input Range
UNITSMIN TYP MAXSYMBOLPARAMETER
Code dependent (Note 4) pF10 50Reference Input Capacitance Code dependent, minimum at code 555hex kΩ40Reference Input Resistance
(Note 5) dB-80AC Feedthrough
(Note 7) V-5.5 -4.5VSS
Negative Supply Voltage
Outputs unloaded, all digital inputs = 0V or VDD µA150 200ISS
Negative Supply Current Outputs unloaded, all digital inputs = 0V or VDD µA250 400IDD
Positive Supply Current
(Note 6) V4.5 5.5VDD
Positive Supply Voltage
STATIC PERFORMANCE
DAC VOLTAGE OUTPUT (VOUT)
REFERENCE INPUT (REFIN)
REFERENCE OUTPUT (REFOUT)—Specifications are identical to those under Single +5V Supply
DYNAMIC PERFORMANCE—Specifications are identical to those under Single +5V Supply
DIGITAL INPUTS (D0-D7,
LDAC
,
CLR
,
CS
,
WR
, A0, A1)—Specifications are identical to those under Single +5V Supply
POWER SUPPLIES
SWITCHING CHARACTERISTICS—Specifications are identical to those under Single +5V Supply
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
_______________________________________________________________________________________
5
0.25
-1.25 012
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE (0–11)
-1.00
MAX530-1
DIGITAL INPUT CODE (DECIMAL)
INTEGRAL NONLINEARITY (LSB)
8
-0.50
2610
0
4
DUAL
SUPPLIES
SINGLE
SUPPLY
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE (11–4095)
11 512 1024 1536 2048 2560 3072 3584 4095
-0.25
0
0.25
INTEGRAL NONLINEARITY (LSB)
DIGITAL INPUT CODE (DECIMAL)
-110
01 10 1k 100k
ANALOG FEEDTHROUGH vs.
FREQUENCY
-30
-70
MAX531-5
FREQUENCY (Hz)
ANALOG FEEDTHROUGH (dB)
100 10k 1M
-100
-90
-80
-60
-50
-40
-20
-10
REFIN = 2Vp-p
CODE = ALL 0s,
DUAL SUPPLIES (±5V)
2.055
2.045 -60 120
REFERENCE VOLTAGE vs.
TEMPERATURE
MAX531-6
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
60
2.050
-20 20 80 100400-40 140
__________________________________________Typical Operating Characteristics
(TA = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted).
12
00 0.8
OUTPUT SINK CAPABILITY vs.
OUTPUT PULL-DOWN VOLTAGE
2
10
MAX531-3
OUTPUT PULL-DOWN VOLTAGE (V)
OUTPUT SINK CAPABILITY (mA)
0.6
6
4
0.2 0.4
8
1.0
14
16
6
004
OUTPUT SOURCE CAPABILITY vs.
OUTPUT PULL-UP VOLTAGE
1
5
MAX531-4
OUTPUT PULL-UP VOLTAGE (V)
OUTPUT SOURCE CAPABILITY (mA)
3
3
2
12
4
5
7
8
Note 2: In single supply, INL and GE are calculated from code 11 to code 4095.
Note 3: Zero Code, Bipolar and Gain Error PSRR are input referred specifications. In Unity Gain, the specification is 500µV.
In Gain = 2 and Bipolar modes, the specification is 1mV.
Note 4: Guaranteed by design.
Note 5: REFIN = 1kHz, 2.0Vp-p.
Note 6: For specified performance, VDD = 5V ±10% is guaranteed by PSRR tests.
Note 7: For specified performance, VSS = -5V ±10% is guaranteed by PSRR tests.
Note 8: Tested at IOUT = 100µA. The reference can typically source up to 5mA (see
Typical Operating Characteristics
).
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)
(VDD = 5V ±10%, VSS = -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT,
CREFOUT = 33µF, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
6 _______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted).
00 500
SUPPLY CURRENT vs. REFIN
50
250
REFIN (mV)
SUPPLY CURRENT (µA)
300
150
100
100 200 400
200
50 150 250 350 450
REFIN = EXTERNAL
REFGND = AGND
REFGND = VDD
MAX530-14
2.0480
2.04500 5.0
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE LOAD CURRENT
2.0455
2.0475
MAX530-15
REFERENCE LOAD CURRENT (mA)
REFERENCE OUTPUT (V)
3.0
2.0465
2.0460
1.0 2.0 4.0
2.0470
0.5 1.5 2.5 3.5 4.5
A: DIGITAL INPUTS RISING EDGE,
B: VOUT, NO LOAD, 1V/div
DUAL SUPPLY (±5V)
LDAC = LOW
BIPOLAR CONFIGURATION
VREFIN = 2V
A
B
SETTLING TIME (RISING)
5µs/div
-200
-300 1
GAIN AND PHASE vs.
FREQUENCY
-100
-100
FREQUENCY (kHz)
GAIN (dB)
10 100
0
-200
800-180
0
180
GAIN
PHASE
(G = 2)
(G = 1)
PHASE SHIFT (Degrees)
MAX530-10
A: DIGITAL INPUTS FALLING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
DUAL SUPPLY (±5V)
LDAC = LOW
BIPOLAR CONFIGURATION
VREFIN = 2V
A
SETTLING TIME (FALLING)
B
5µs/div
DIGITAL FEEDTHROUGH
A
B
A: D0...D7 = 100kHz, 4Vp-p
B: VOUT, 10mV/div
LDAC = CS = HIGH
2µs/div
300
230 -60 -20 60
SUPPLY CURRENT vs. TEMPERATURE
250
280
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
20 100
260
290
270
240
-40 0 40 80
MAX530-7
4
-14 1 100 100k
GAIN vs. FREQUENCY
-12
MAX531-8
FREQUENCY (Hz)
GAIN (dB)
-8
-4
0
2
-2
-6
-10
1k 10k
REFIN = 4Vp-p
DUAL SUPPLIES (±5V)
80
010 1k 100k
AMPLIFIER SIGNAL-TO-NOISE RATIO
10
MAX531-9
FREQUENCY (Hz)
SIGNAL-TO-NOISE RATIO (dB)
20
40
60
30
50
70
10k100
REFIN = 4Vp-p
DUAL SUPPLIES (±5V)
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode.
D0 (LSB) Input Dta when A0 = 0 and A1 = 1, or D8 Input when A0 = A1= 1*
D0/D824
Positive Power Supply (+5V)VDD
23
Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output.ROFS22
Feedback Pin. Op-amp feedback resistor. Always connect to VOUT.RFB21
Voltage Output. Op-amp buffered DAC output.VOUT20
Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation.VSS
19
Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC.REFOUT18
Reference Ground must be connected to AGND when using the internal reference. Connect to VDD
to disable the internal reference and save power.
REFGND17
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input
latch to the DAC latch and updates VOUT.
LDAC16
Clear (active low). A low on CLR resets the DAC latches to all 0s.CLR15
Analog GroundAGND14
Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to
REFOUT (pin 18) to use the internal 2.048V reference.
REFIN13
Digital GroundDGND12
Chip Select (active low). Enables addressing and writing to this chip from common bus lines.CS11
Write Input (active low). Used with CSto load data into the input latch selected by A0 and A1.WR10
Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and
A1 = 0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing.
A19
Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM),
and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.)
A08
D7 Input Dta, or tie to D3 and multiplex when A0 = 1 and A1 = 0*D77
D6 Input Dta, or tie to D2 and multiplex when A0 = 1 and A1 = 0*D66
D5 Input Dta, or tie to D1 and multiplex when A0 = 1 and A1 = 0*D55
D4
D3/D11
D2/D10
D1/D9
NAME
D4 Input Dta, or tie to D0 and multiplex when A0 = 1 and A1 = 0*4
D3 Input Dta, when A0 = 0 and A1 = 1, or D11 (MSB) Input when A0 = A1 =1*3
D2 Input Dta, when A0 = 0 and A1 = 1, or D10 Input when A0 = A1 = 1*2
D1 Input Dta, when A0 = 0 and A1 = 1, or D9 Input when A0 = A1 = 1*1
FUNCTIONPIN
MAX530
________________Detailed Description
The MAX530 consists of a parallel-input logic interface, a
12-bit R-2R ladder, a reference, and an op amp. The
Functional Diagram
shows the control lines and signal
flow through the input data latch to the DAC latch, as well
as the 2.048V reference and output op amp. Total supply
current is typically 250µA with a single +5V supply. This
circuit is ideal for battery-powered, microprocessor-con-
trolled applications where high accuracy, no adjustments,
and minimum component count are key requirements.
R-2R Ladder
The MAX530 uses an “inverted” R-2R ladder network with
a BiCMOS op amp to convert 12-bit digital data to analog
voltage levels. Figure 1 shows a simplified diagram of the
R-2R DAC and op amp. Unlike a standard DAC, the
MAX530 uses an “inverted” ladder network. Normally, the
REFIN pin is the current output of a standard DAC and
would be connected to the summing junction, or virtual
ground, of an op amp. In this standard DAC configura-
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
8 _______________________________________________________________________________________
2R2R 2R 2R 2R
RRR
MSB
OUTPUT
BUFFER
VOUT
RFB
ROFS
MAX530
2R
2R
REFIN
AGND
DAC LATCH
R = 80kΩ
LSB
NBL
INPUT
LATCH
NBH
INPUT
LATCH
NBM
INPUT
LATCH
D0/D8D1/D9
D2/D10 D4
D3/D11 D6
D5 D7
2.048V
REFOUT
REFGND
*SHOWN FOR ALL 1s
*
LSB MSB CLR
Figure 1. Simplified MAX530 DAC Circuit
tion, however, the output voltage would be the inverse of
the reference voltage. The MAX530’s topology makes the
ladder output voltage the same polarity as the reference
input, which makes the device suitable for single-supply
operation. The BiCMOS op amp is then used to buffer,
invert, or amplify the ladder signal.
Ladder resistors are nominally 80kΩto conserve power
and are laser trimmed for gain and linearity. The input
impedance at REFIN is code dependent. When the DAC
register is all 0s, all rungs of the ladder are grounded
and REFIN is open or no load. Maximum loading (mini-
mum REFIN impedance) occurs at code 010101... or
555hex. Minimum reference input impedance at this
code is guaranteed to be not less than 40kΩ.
The REFIN and REFOUT pins allow the user to choose
between driving the R-2R ladder with the on-chip refer-
ence or an external reference. REFIN may be below ana-
log ground when using dual supplies. See the
External
Reference
and
Four-Quadrant Multiplication
sections for
more information.
Internal Reference
The on-chip reference is laser trimmed to generate
2.048V at REFOUT. The output stage can source and
sink current so REFOUT can settle to the correct volt-
age quickly in response to code-dependent loading
changes. Typically source current is 5mA and sink cur-
rent is 100µA.
REFOUT connects the internal reference to the R-2R
DAC ladder at REFIN. The R-2R ladder draws 50µA
maximum load current. If any other connection is made
to REFOUT, ensure that the total load current is less
than 100µA to avoid gain errors.
A separate REFGND pin is provided to isolate refer-
ence currents from other analog and digital ground
currents. To achieve specified noise performance, con-
nect a 33µF capacitor from REFOUT to REFGND (see
Figure 2). Using smaller capacitance values increases
noise, and values less than 3.3µF may compromise the
reference’s stability. For applications requiring the low-
est noise, insert a buffered RC filter between REFOUT
and REFIN. When using the internal reference,
REFGND must be connected to AGND. In applications
not requiring the internal reference, connect REFGND
to VDD, which shuts down the reference and saves typ-
ically 100µA of VDD supply current.
Output Buffer
The output amplifier uses a folded cascode input stage
and a type AB output stage. Large output devices with
low series resistance allow the output to swing to
ground in single-supply operation. The output buffer is
unity-gain stable. Input offset voltage and supply cur-
rent are laser trimmed. Settling time is 25µs to 0.01% of
final value. The output is short-circuit protected and
can drive a 2kΩload with more than 100pF of load
capacitance. The op amp may be placed in unity-gain
(G = 1), in a gain of two (G = 2), or in a bipolar-output
mode by using the ROFS and RFB pins. These pins are
used to define a DAC output voltage range of 0V to
+2.048V, 0V to +4.096V or ±2.048V, by connecting
ROFS to VOUT, GND, or REFIN. RFB is always con-
nected to VOUT. Table 1 summarizes ROFS usage.
External Reference
An external reference in the range (VSS + 2V) to
(VDD - 2V) may be used with the MAX530 in dual-sup-
ply, unity-gain operation. In single-supply, unity-gain
operation, the reference must be positive and may not
exceed (VDD - 2V). The reference voltage determines
the DAC’s full-scale output. Because of the code-
dependent nature of reference input impedances, a
high-quality, low-output-impedance amplifier (such as
the MAX480 low-power, precision op amp) should be
used to drive REFIN.
If an upgrade to the internal reference is required, the
2.5V MAX873A is ideal: ±15mV initial accuracy,
7ppm/°C (max) temperature coefficient.
Power-On Reset
An internal power-on reset (POR) circuit forces the
DAC register to reset to all 0s when VDD is first applied.
The POR pulse is typically 1.3µs; however, it may take
2ms for the internal reference to charge its large filter
capacitor and settle to its trimmed value.
In addition to POR , a clear (CLR) pin, when held low,
sets the DAC register to all 0s. CLR operates asynchro-
nously and independently from chip select (CS). With
the DAC input at all 0s, the op-amp output is at zero for
unity-gain and G = 2 configurations, but it is at -VREF
for the bipolar configuration.
Shutdown Mode
The MAX530 is designed for low power consumption.
Understanding the circuit allows power consumption
management for maximum efficiency. In single-supply
mode (VDD = +5V, VSS = GND) the initial supply cur-
rent is typically only 160µA, including the reference, op
amp, and DAC. This low current occurs when the
power-on reset circuit clears the DAC to all 0s and
forces the op-amp output to zero (unipolar mode only).
See the Supply Current vs. REFIN graph in the
Typical
Operating Characteristics
. Under this condition, there
is no internal load on the reference (DAC = 000hex,
REFIN is open circuit) and the op amp operates at its
minimum quiescent current. The CLR signal resets the
MAX530 to these same conditions and can be used to
control a power-saving mode when the DAC is not
being used by the system.
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
_______________________________________________________________________________________ 9
ROFS
CONNECTED TO: DAC OUTPUT
RANGE OP-AMP
GAIN
VOUT 0V to 2.048V G = 1
AGND 0V to 4.096V G = 2
REFIN -2.048V to +2.048V Bipolar
Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V
Table 1. ROFS Usage
Figure 2. Reference Noise vs. Frequency
300
50
1 10 100
100
MAX531-FIG02
FREQUENCY (kHz)
REFERENCE NOISE (µVRMS)
150
200
250
00.1 1000
TOTAL
REFERERNCE
NOISE
RS
REFOUT
CREFOUT
CS
TEK 7A22
CREFOUT = 3.3µF
CREFOUT = 47µF
SINGLE POLE ROLLOFF 1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
REFERENCE NOISE (mVp-p)
An additional 110µA of supply current can be saved
when the internal reference is not used by connecting
REFGND to VDD. A low on resistance N-channel FET,
such as the 2N7002, can be used to turn off the internal
reference to create a shutdown mode with minimum
current drain (Figure 3). When CLR is high, the transis-
tor pulls REFGND to AGND and the reference and DAC
operate normally. When CLR goes low, REFGND is
pulled up to VDD and the reference is shut down. At the
same time, CLR resets the DAC register to all 0s, and
the op-amp output goes to 0V for unity-gain and G = 2
modes. This reduces the total single-supply operating
current from 250µA (400µA max) to typically 40µA in
shutdown mode.
A small error voltage is added to the reference output
by the reference current flowing through the N-channel
pull-down transistor. The switch’s on resistance should
be less than 5Ω. A typical reference current of 100µA
would add 0.5mV to REFOUT. Since the reference cur-
rent and on resistance increase with temperature, the
overall temperature coefficient will degrade slightly.
As data is loaded into the DAC and the output moves
above GND, the op-amp quiescent current increases to
its nominal value and the total operating current aver-
ages 250µA. Using dual supplies (±5V), the op amp is
fully biased continuously, and the VDD supply current is
more constant at 250µA. The VSS current is typically
150µA.
The MAX530 logic inputs are compatible with TTL and
CMOS logic levels. However, to achieve the lowest
power dissipation, drive the digital inputs with rail-to-rail
CMOS logic. With TTL logic levels, the power require-
ment increases by a factor of approximately 2.
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
10 ______________________________________________________________________________________
MAX530
MAX530
12-BIT DAC LATCH
NBL
INPUT
LATCH
NBH
INPUT
LATCH
NBM
INPUT
LATCH
D0/D8
D1/D9D2/D10 D4
D3/D11 D6
D5 D7
POWER-ON
RESET
CONTROL
LOGIC
DAC
A0
A1
CS
WR
LDAC
CLR
33µF2.048V
REFERENCE
REFOUT REFIN ROFS
RFB
VOUT
+5V
VSS
DGND
2N7002 REFGND
AGND
VDD
Figure 3. Low-Current Shutdown Mode
CLR CS WR LDAC
A0 A1 DATA UPDATED
L X X X X X Reset DAC Latches
H H X H X X No Operation
H X H H X X No Operation
H L L H H H NBH (D8-D11)
H L L H H L NBM (D4-D7)
H L L H L H NBL (D0-D3)
H H H L X X Update DAC Only
H L L X L L DAC NOT UPDATED
H L L L H H NBH and Update DAC
Table 2. Input Latch Addressing
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
______________________________________________________________________________________ 11
VIH
VIL
DATA BITS
(8-BIT BYTE OR
4-BIT NIBBLE)
A0-A1 VIL
VIH
ADDRESS BUS VALID
tAWH
tCWS
tWR
tCWH
tAWS
tDS tDH
DATA BUS
VALID
NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL
2
tCLR
CS
WR
CLR
LDAC tLDAC
Figure 4. MAX530 Write-Cycle Timing Diagram
Parallel Logic Interface
Designed to interface with 4-bit, 8-bit, and 16-bit micro-
processors (µPs), the MAX530 uses 8 data pins and
double-buffered logic inputs to load data as 4 + 4 + 4
or 8 + 4. The 12-bit DAC latch is updated simultane-
ously through the control signal LDAC. Signals A0, A1,
WR, and CS select which input latches to update. The
12-bit data is broken down into nibbles (NB); NBL is
the enable signal for the lowest 4 bits, NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.
Refer to Figure 4 for the MAX530 write-cycle timing
diagram.
Figure 5 shows the circuit configuration for a 4-bit µP
application. Figure 6 shows the corresponding timing
sequence. The 4 low bits (D0-D3) are connected in paral-
lel to the other 4 bits (D4-D7) and then to the µP bus.
Address lines A0 and A1 enable the input data latches
for the high, middle, or low data nibbles. The µP sends
chip select (CS) and write (WR) signals to latch in each of
three nibbles in three cycles when the data is valid.
Figure 7 shows a typical interface to an 8-bit or a 16-bit
µP. Connect 8 data bits from the data bus to pins D0-D7
on the MAX530. With LDAC held high, the user can load
NBH or NBL +NBM in any order. Figure 8a shows the
corresponding timing sequence. For fastest throughput,
use Figure 8b’s sequence. Address lines A0 and A1 are
tied together and the DAC is loaded in 2 cycles as 8 + 4.
In this scheme, with LDAC held low, the DAC latch is
transparent. Always load NBL and NBM first, followed by
NBH.
LDAC is asynchronous with respect to WR. If LDAC is
brought low before or at the same time WR goes high,
LDAC must remain low for at least 50ns to ensure the cor-
rect data is latched. Data is latched into DAC registers on
LDAC’s rising edge.
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
12 ______________________________________________________________________________________
A0 = 1, A1 = 1
NBH
NBM
NBL
CS
WR
LDAC
A0 = 1, A1 = 0
A0 = 0, A1 = 1
DAC UPDATE
Figure 6. 4-Bit µP Timing Sequence
A0 = A1 = 1
A0 = A1 = 0
DAC UPDATE
NBH
NBL & NBM
CS
WR
LDAC
Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC
Figure 5. 4-Bit µP Interface
DATA BUS
D0-D3 D0-D3
D0-D3 D4-D7
MC6800
FROM
SYSTEM
RESET
02
R/W
CLR
WR CS LDAC
EN DECODER
A0-A15 A13-A15
ADDRESS BUS A0, A1
A0, A1
D0-D3
MAX530
Figure 7. 8-Bit and 16-Bit µP Interface
D0-D7 DATA BUS D0-D7
D0-D7
MC6809
FROM
SYSTEM
RESET CLR
A0-A1
WR CS LDAC
E
R/W
A0-A15 A13-A15
A0
ADDRESS BUS
EN DECODER
MAX530
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
______________________________________________________________________________________ 13
A0 = A1 = 0
A0 = A1 = 1
DAC UPDATE
NBH
NBL & NBM
CS
WR
LDAC = 0 (DAC LATCH IS TRANSPARENT)
Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0
Unipolar Configuration
The MAX530 is configured for a 0V to +2.048V unipolar
output range by connecting ROFS and RFB to VOUT
(Figure 9). The converter operates from either single or
dual supplies in this configuration. See Table 3 for the
DAC-latch contents (input) vs. the analog VOUT (output).
In this range, 1LSB = REFIN (2 -12).
A 0V to 4.096V unipolar output range is set up by con-
necting ROFS to AGND and RFB to VOUT (Figure 10).
Table 4 shows the DAC-latch contents vs. VOUT. The
MAX530 operates from either single or dual supplies in
this mode. In this range, 1LSB = (2)(REFIN)(2 -12) =
(REFIN)(2 -11).
33µF
REFIN
REFOUT
AGND
DGND
REFGND
VDD
VSS
ROFS
RFB
VOUT VOUT
0V TO -5V
+5V
G = 1
MAX530
33µF
REFIN
REFOUT
AGND
DGND
REFGND
VDD
VSS
ROFS RFB
VOUT VOUT
0V TO -5V
+5V
G = 2
MAX530
Figure 9. Unipolar Configuration (0V to +2.048V Output) Figure 10. Unipolar Configuration (0V to +4.096V Output)
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
14 ______________________________________________________________________________________
INPUT OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
(VREFIN) 4095
4096
(VREFIN) 2049
4096
(VREFIN) 2048
4096
(VREFIN) 2047
4096
(VREFIN) 1
4096
OV
= +VREFIN/2
Table 3. Unipolar Binary Code Table
(0V to VREFIN Output), Gain = 1
INPUT OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
+2 (VREFIN) 4095
4096
+2 (VREFIN) 2049
4096
+2 (VREFIN) 2048
4096
+2 (VREFIN) 2047
4096
+2 (VREFIN) 1
4096
OV
= +VREFIN
Table 4. Unipolar Binary Code Table
(0V to 2VREFIN Output), Gain = 2
INPUT OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
(+VREFIN) 2047
2048
(+VREFIN) 1
2048
(-VREFIN) 1
2048
(-VREFIN) 2047
2048
0V
(-VREFIN) 2048
2048 = -VREFIN
Table 5. Bipolar (Offset Binary) Code Table
(-VREFIN to +VREFIN Output)
Bipolar Configuration
A -VREFIN to +VREFIN bipolar range is set up by con-
necting ROFS to REFIN and RFB to VOUT, and operat-
ing from dual (±5V) supplies (Figure 11). Table 5
shows the DAC-latch contents (input) vs. VOUT (out-
put). In this range, 1 LSB = REFIN (2 -11).
Four-Quadrant Multiplication
The MAX530 can be used as a four-quadrant multiplier
by connecting ROFS to REFIN and RFB to VOUT and,
using (1) an offset binary digital code, (2) bipolar
power supplies, and (3) a bipolar analog input at
REFIN within the range VSS + 2V to VDD - 2V, as shown
in Figure 12.
In general, a 12-bit DAC’s output is (D)(VREFIN)(G),
where “G” is the gain (1 or 2) and “D” is the binary rep-
resentation of the digital input divided by 212 or 4,096.
This formula is precise for unipolar operation. However,
for bipolar, offset binary operation, the MSB is really a
polarity bit. No resolution is lost, because there is the
same number of steps. The output voltage, however,
has been shifted from a range of, for example, 0V to
4.096V (G = 2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quad-
rant multiplier, the scale is skewed. The negative full
scale is -VREFIN, while the positive full scale is +VREFIN
- 1LSB.
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
______________________________________________________________________________________ 15
33µF
REFIN
REFOUT
AGND
DGND
REFGND
ROFS
RFB
VOUT VOUT
-5V
+5V
MAX530
Figure 11. Bipolar Configuration (-2.048V to +2.048V Output) Figure 12. Four-Quadrant Multiplying Circuit
REFGND
AGND
DGND
REFIN
VDD
VSS
ROFS
RFB
VOUT VOUT
-5V
+5V
REFIN
MAX530
__________Applications Information
Single-Supply Linearity
As with any amplifier, the MAX530’s output op amp offset
can be positive or negative. When the offset is positive, it
is easily accounted for. However, when the offset is nega-
tive, the output cannot follow linearly when there is no
negative supply. In that case, the amplifier output (VOUT)
remains at ground until the DAC voltage is sufficient to
overcome the offset and the output becomes positive.
The resulting transfer function is shown in Figure 13.
Normally, linearity is measured after allowing for zero
error and gain error. Since, in single-supply operation,
the actual value of a negative offset is unknown, it can-
not be accounted for during test. In the MAX530, linear-
ity and gain error are measured from code 11 to code
4095 (see Note 2 under
Electrical Characteristics
). The
output amplifier offset does not affect monotonicity, and
these DACs are guaranteed monotonic starting with
code zero. In dual-supply operation, linearity and gain
error are measured from code 0 to 4095.
Power-Supply Bypassing
and Ground Management
Best system performance is obtained with printed cir-
cuit boards that use separate analog and digital ground
planes. Wire-wrap boards are not recommended. The
two ground planes should be connected together at the
low-impedance power-supply source.
AGND and REFGND should be connected together,
and then to DGND at the chip. For single-supply appli-
cations, connect VSS to AGND at the chip. The best
ground connection may be achieved by connecting
the AGND, REFGND, and DGND pins together and
connecting that point to the system analog ground
plane. If DGND is connected to the system digital
ground, digital noise may get through to the DAC’s ana-
log portion.
Bypass VDD (and VSS in dual-supply mode) with a
0.1µF ceramic capacitor connected between VDD and
AGND (and between VSS and AGND). Mount the
capacitors with short leads close to the device.
AC Considerations
Digital Feedthrough
High-speed data at any of the digital input pins may
couple through the DAC package and cause internal
stray capacitance to appear as noise at the DAC out-
put, even though LDAC and CS are held high (see
Typical Operating Characteristics
). This digital
feedthrough is tested by holding LDAC and CS high
and toggling the data inputs from all 1s to all 0s.
Analog Feedthrough
Because of internal stray capacitance, higher-frequen-
cy analog input signals at REFIN may couple to the
output, even when the input digital code is all 0s, as
shown in the
Typical Operating Characteristics
graph
Analog Feedthrough vs. Frequency. It is tested by set-
ting CLR to low (which sets the DAC latches to all 0s)
and sweeping REFIN.
_Ordering Information (continued)
MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
1
2
3
4
12345678
0
POSITIVE OFFSET
NEGATIVE OFFSET
DAC CODE (LSBs)
OUTPUT (LSBs)
Figure 13. Single-Supply DAC Transfer Function
TRANSISTOR COUNT: 913;
SUBSTRATE CONNECTED TO VDD.
LDAC
REFGND
A0
D4
D3/D11
AGND
0.133"
(3.378mm)
0.087"
(2.210mm)
D5
D6
D7
A1
DGND
CS REFIN
WR
REFOUT
VSS
VOUT
D2/D10
D1/D9
D0/D8
VDD
ROFSRFB
CLR
___________________Chip Topography
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
ERROR
(LSB)
±
1/2
±1
±
1/2
±1
±
1/2
±124 SSOP-40°C to +85°CMAX530BEAG 24 SSOP-40°C to +85°CMAX530AEAG 24 Wide SO-40°C to +85°CMAX530BEWG 24 Wide SO-40°C to +85°CMAX530AEWG 24 Narrow Plastic DIP-40°C to +85°CMAX530BENG 24 Narrow Plastic DIP-40°C to +85°CMAX530AENG
PIN-PACKAGETEMP. RANGEPART
