© Semiconductor Components Industries, LLC, 2019
April, 2019 − Rev. 1
1Publication Order Number:
FGD3040G2−F085V/D
FGD3040G2-F085V
EcoSPARK 2 Ignition IGBT
335 mJ, 400 V, N−Channel Ignition IGBT
Features
•SCIS Energy = 335 mJ at TJ = 25°C
•Logic Level Gate Drive
•AEC−Q101 Qualified and PPAP Capable
•These Device is Pb−Free and are RoHS Compliant
Applications
•Automotive Ignition Coil Driver Circuits
•High Current Ignition System
•Coil on Plug Application
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol Parameter Value Units
BVCER Collector to Emitter Breakdown
Voltage (IC = 1 mA)
400 V
BVECS Emitter to Collector Voltage − Reverse
Battery Condition (IC = 10 mA)
28 V
ESCIS25 Self Clamping Inductive Switching Energy
(Note 1)
335 mJ
ESCIS150 Self Clamping Inductive Switching Energy
(Note 2)
195 mJ
IC25 Collector Current Continuous
at VGE = 4.0 V, TC = 25°C
26.9 A
IC110 Collector Current Continuous
at VGE = 4.0 V, TC = 110°C
25 A
VGEM Gate to Emitter Voltage Continuous ±10 V
PDPower Dissipation Total, TC = 25°C166 W
Power Dissipation Derating, TC > 25°C1.1 W/°C
TJOperating Junction and Storage
Temperature
−40 to +175 °C
TSTG Storage Junction Temperature Range −40 to +175 °C
TLMax. Lead Temperature for Soldering
(Package Body for 10 s)
300 °C
TPKG Max. Lead Temperature for Soldering
(Package Body for 10 s)
260 °C
ESD Electrostatic Discharge Voltage at 100 pF,
1500 W
4kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Self clamped inductive Switching Energy (ESCIS25) of 335 mJ is based on
the test conditions that is starting TJ = 25°C, L = 3 mHy, ISCIS = 15 A,
VCC = 100 V during inductor charging and VCC = 0 V during time in clamp.
2. Self Clamped inductive Switching Energy (ESCIS150) of 195 mJ is based on
the test conditions that is starting TJ = 150°C, L = 3mHy, ISCIS = 11.4 A,
VCC = 100 V during inductor charging and VCC = 0 V during time in clamp.
DPAK (SINGLE GAUGE)
CASE 369C
See detailed ordering and shipping information on page 2
of this data sheet.
ORDERING INFORMATION
www.onsemi.com
MARKING DIAGRAM
AYWW
FGD
3040G2G
GATE
COLLECTOR
EMITTER
R1
R2
12
3
4
A = Assembly Location
Y = Year
WW = Work Week
FGD3040G2= Device Code
G = Pb−Free Package
FGD3040G2−F085V
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2
THERMAL RESISTANCE RATINGS
Characteristic Symbol Max Units
Junction−to−Case – Steady State (Drain) RqJC 1°C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol Parameter Test Conditions Min Typ. Max. Units
OFF CHARACTERISTICS
BVCER Collector to Emitter Breakdown Voltage ICE = 2 mA, VGE = 0 V,
RGE = 1 kW, TJ = −40 to 150°C
370 400 430 V
BVCES Collector to Emitter Breakdown Voltage ICE = 10 mA, VGE = 0 V,
RGE = 0, TJ = −40 to 150°C
390 420 450 V
BVECS Emitter to Collector Breakdown Voltage ICE = −75 mA, VGE = 0 V,
TJ = 25°C
28 − − V
BVGES Gate to Emitter Breakdown Voltage IGES = ±2 mA ±12 ±14 −V
ICER Collector to Emitter Leakage Current VCE = 175 V
RGE = 1 kW
TJ = 25°C− − 25 mA
TJ = 150°C− − 1 mA
IECS Emitter to Collector Leakage Current VEC = 24 V TJ = 25°C− − 1mA
TJ = 150°C− − 40
R1Series Gate Resistance −120 −W
R2Gate to Emitter Resistance 10K −30K W
ON CHARACTERISTICS (Note 5)
VCE(SAT) Collector to Emitter Saturation Voltage ICE = 6 A, VGE = 4 V, TJ = 25°C−1.15 1.25 V
VCE(SAT) Collector to Emitter Saturation Voltage ICE = 10 A, VGE = 4.5 V, TJ = 150°C−1.35 1.50 V
VCE(SAT) Collector to Emitter Saturation Voltage ICE = 15 A, VGE = 5 V, TJ = 150°C−1.68 1.85 V
DYNAMIC CHARACTERISTICS
QG(ON) Gate Charge ICE = 10 A, VCE = 12 V, VGE = 5 V −21 −nC
VGE(TH) Gate to Emitter Threshold Voltage ICE = 1 mA
VCE = VGE
TJ = 25°C 1.3 1.5 2.2 V
TJ = 150°C 0.75 1.2 1.8
VGEP Gate to Emitter Plateau Voltage VCE = 12 V, ICE = 10 A −2.8 −V
SWITCHING CHARACTERISTICS
td(ON)R Current Turn−On Delay Time−Resistive VCE = 14 V, RL = 1 W, VGE = 5 V,
RG = 1 W, TJ = 25°C
−1.0 4 ms
trR Current Rise Time−Resistive −2.0 7
td(OFF)L Current Turn−Off Delay Time−Inductive VCE = 300 V, L = 1 mH, VGE = 5 V,
RG = 1 W, ICE = 6.5 A, TJ = 25°C
−5.3 10
tfL Current Fall Time−Inductive −2.3 15
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
PACKAGE MARKING AND DEVICE ORDERING INFORMATION
Device Marking Device Package Reel Diameter Tape Width Qty†
FGD3040G2 FGD3040G2−F085V DPAK (Pb−Free) 330 mm 16 mm 2500
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
FGD3040G2−F085V
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3
TYPICAL CHARACTERISTICS
Figure 1. Self Clamped Inductive Switching
Current vs. Time in Clamp
Figure 2. Self Clamped Inductive Switching
Current vs. Inductance
Figure 3. Collector to Emitter On−State
Voltage vs. Junction Temperature
Figure 4. Collector to Emitter On−State
Voltage vs. Junction Temperature
Figure 5. Collector to Emitter On−State
Voltage vs. Collector Current
Figure 6. Collector to Emitter On−State
Voltage vs. Collector Current
FGD3040G2−F085V
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4
TYPICAL CHARACTERISTICS (continued)
Figure 7. Collector to Emitter On−State Voltage vs.
Collector Current
Figure 8. Transfer Characteristics
Figure 9. DC Collector Current vs. Case
Temperature
Figure 10. Gate Charge
Figure 11. Threshold Voltage vs. Junction
Temperature
Figure 12. Leakage Current vs. Junction
Temperature
FGD3040G2−F085V
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6
Figure 17. Inductive Switching Test Circuit Figure 18. tON and tOFF Switching Test Circuit
TEST CIRCUIT AND WAVEFORMS
Figure 19. Energy Test Circuit Figure 20. Energy Waveforms
ECOSPARK is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
123
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DET AIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
eBOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
DPAK SINGLE GAUGE SURFACE MOUNT
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001
AADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008
BADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009
CADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009
DRELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010
EADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
06 FEB 2014
FADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA. 21 JUL 2015
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. F Case Outline Number
:
369C
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