ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS840021 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS840021 uses a 25MHz crystal to synthesize 125MHz. The ICS840021 has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS840021 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * 1 LVCMOS/LVTTL output, 7 output impedence ICS * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequency: 125MHz * VCO range: 560MHz to 680MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.34ps (typical) * RMS phase noise at 125MHz (typical) Phase noise: Offset Noise Power 100Hz ............... -96.9 dBc/Hz 1kHz .............. -122.2 dBc/Hz 10kHz .............. -131.1 dBc/Hz 100kHz .............. -129.5 dBc/Hz * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-complaint packages BLOCK DIAGRAM PIN ASSIGNMENT OE 25MHz XTAL_IN OSC XTAL_OUT Phase Detector VCO Q0 /5 VDDA OE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q0 GND nc ICS840021 /25 (fixed) 840021AG 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Type 2 OE Input 5 XTAL_OUT, XTAL_IN nc Unused 6 GND Power 7 Q0 Output 8 VDD Power 3, 4 Description Pullup Input Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 7 output impedence. Power supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor ROUT Output Impedance Minimum VDD, VDDA = 3.465V Typical Maximum 4 pF 24 pF 51 5 Units 7 k 12 TABLE 3. CONTROL FUNCTION TABLE Control Inputs 840021AG Output OE Q0 0 Hi-Z 1 Active www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VDDA Analog Supply Voltage 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 15 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 Minimum Maximum Units 2 Typical VDD + 0.3 V -0.3 0.8 V 5 A -150 A 2.6 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 0.5 V Maximum Units TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter fOUT Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time tjit(O) t R / tF Test Conditions Intergration Range: 1.875MHz to 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. 840021AG Minimum www.icst.com/products/hiperclocks.html 3 Typical 125 MHz 0.34 ps 250 550 ps 48 52 % REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR TYPICAL PHASE NOISE AT 125MHZ 0 -10 10 Gb Ethernet Filter -20 -30 125MHz -40 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.34ps (typical) -50 -60 -80 -90 -100 Raw Phase Noise Data -110 NOISE POWER dBc Hz -70 -120 -130 -140 -150 -160 -170 Phase Noise Result by adding a 10 Gb Ethernet Filter to raw data -180 -190 100k 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840021AG www.icst.com/products/hiperclocks.html 4 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V 5% Phase Noise Plot Noise Power SCOPE V DD Qx LVCMOS Phase Noise Mask GND Offset Frequency f1 -1.65V 5% f2 RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V DD 80% 2 Q0 80% t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840021AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840021 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead. 3.3V VDD .01F 10 V DDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS840021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 840021AG www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR APPLICATION SCHEMATIC output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Figure 3A shows a schematic example of the ICS840021. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz VDD VDDA R2 10 C3 C4 10uF 0.1u U1 OE C2 33pF 1 2 3 4 VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND NC 8 7 6 5 R3 43 VDD Q Zo = 50 Ohm X1 C5 0.1u ICS840021 C1 27pF LVCMOS VDD=3.3V FIGURE 3A. ICS840021 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of ICS840021 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 7. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2, R3 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 3B. ICS840021 PC BOARD LAYOUT EXAMPLE 840021AG www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS840021 is: 1961 840021AG www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR 8 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840021AG www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840021AG 021AG 8 lead TSSOP tube 0C to 70C ICS840021AGT 021AG 8 lead TSSOP 2500 tape & reel 0C to 70C ICS840021AGLF 021AL 8 lead "Lead-Free" TSSOP tube 0C to 70C ICS840021AGLFT 021AL 8 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840021AG www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 7, 2005 ICS840021 Integrated Circuit Systems, Inc. FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page A T10 10 3 8 1 10 A A 840021AG T8 T10 Description of Change Date Ordering Information Table - correct count from 154 to 100. Absolute Maximum Ratings - corrected Package Thermal Impedance air flow. Corrected air flow in table. Features section - added lead-free bullet. Ordering Information Table - added lead-free par t number and marking. www.icst.com/products/hiperclocks.html 11 10/14/04 11/30/04 10/7/05 REV. A OCTOBER 7, 2005