INTEGRATED CIRCUITS DATA Siilleler 74LV273 positive-edge trigger Octal D-type flip-flop with reset; Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook Philips Semiconductors PHILIPS Q 1998 May 29 PHILIPSPhilips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between Voc = 2.7V and Voc = 3.6V Typical Vo_p (output ground bounce) < 0.8V @ Vcc = 3.3V, Tamb = 25C Typical Voyy (output Voy undershoot) > 2V @ Vcc = 3.3V, Tamb = 25C |deal buffer for MOS microprocessor or memory Common clock and master reset Output capability: standard loc category: MSI QUICK REFERENCE DATA GND = OV; Tamb = 25C; t, =t) $2.5 ns DESCRIPTION The 74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The 74LV273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay 42 tpHL/teLH CP to Q,; C_= 15pF ns MR to Q, Voc = 3.3V 13 fmax Maximum clock frequency 110 MHz Cc Input capacitance 3.5 pF Cpp Power dissipation capacitance per flip-flop Notes 1 and 2 20 pF NOTES: 1. Cpp is used to determine the dynamic power dissipation (Pp in uW) Pp =Cpp X Voc? xf, +2 (CL x Voc? X fo) where: f, = input frequency in MHz; C_ = output load capacitance in pF; fy = output frequency in MHz; Vcc = supply voltage in V; Z(CL xX Vec? x fy) = sum of the outputs. 2. The condition is V; = GND to Voc ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL 40C to +125C 74LV273 N 74LV273 N SOT146-1 20-Pin Plastic SO 40C to +125C 74LV273 D 74LV273 D SOT163-1 20-Pin Plastic SSOP Type II 40C to +125C 74LV273 DB 74LV273 DB SOT339-1 20-Pin Plastic TSSOP 40C to +125C 74LV273 PW 74LV273PW DH SOT360-1 1998 May 29 853-1965 19466Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 PIN CONFIGURATION LOGIC SYMBOL " MR Ly VV [20] Voc 3 2 Q [2 3] a7 4 5 Do BI 18] Dz DF FA) De 7 6 a, Fg] ag 8 9 Q fe] iE] Qs 13 12 Do [7] 4] Ds 14 15 Dg [eI EE] D4 17 16 Q3 [2] 12] Q4 18 19 GND [fq fi] cP 1 SV00366 SV00367 PIN DESCRIPTION LOGIC SYMBOL (IEEE/IEC) PIN NUMBER SYMBOL FUNCTION 1 MR Master reset input (active-LOW) ts 16 7, 2, Qo to Q7_| Flip-flop outputs ty f 3, Do to D7 Data inputs 10 GND Ground (OV) 11 CP Clock input (LOW-to-HIGH, edge- triggered) 20 Voc Positive supply voltage SV00368 1998 May 29 3Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 FUNCTIONAL DIAGRAM FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR CP Dn Qo to Q7 3 2 Reset (clear) L x x L Load (1) H tT h H 4 5 Load (0) H tT I L 6 H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition 13 12 L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition tT = LOW-to-HIGH clock transition x = Dontcare 18 19 1 1 SV00369 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT Voc DC supply voltage See Note1 1.0 3.3 5.5 Vv V| Input voltage 0 - Voc Vv Vo Output voltage 0 - Voc Vv T. Operating ambient temperature range in free See DC and AC -40 +85 C amb air characteristics 40 +125 Voc = 1.0V to 2.0V _ - 500 . : Voc = 2.0V to 2.7V _ - 200 t,t Input rise and fall times Veo =2.7V to 3.6V 7 _ 100 ns/V Voc = 3.6V to 5.5V - 50 NOTES: 1. The LV is guaranteed to function down to Voc = 1.0V (input levels GND or Voc); DC characteristics are guaranteed from Voc = 1.2V to Voc = 5.5V. 1998 May 29Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 ABSOLUTE MAXIMUM RATINGS! 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = OV) SYMBOL PARAMETER CONDITIONS RATING UNIT Voc DC supply voltage 0.5 to +7.0 Vv +k DC input diode current V, <-0.5 or Vi > Voc + 0.5V 20 mA +lox DC output diode current Vo < 0.5 or Vo > Veco + 0.5V 50 mA DC output source or sink current 4 tlo standard outputs 0.5V< Vo < Vec + 0.5V 25 mA DC Vcc or GND current for types with gue standard outputs 50 mA Tstg Storage temperature range 65 to +150 C Power dissipation per package for temperature range: 40 to +125C P plastic DIL above +70C derate linearly with 12mW/K 750 Ww TOT plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 m plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 400 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = OV) LIMITS SYMBOL PARAMETER TEST CONDITIONS -40C to +85C -40C to +125C UNIT MIN TYP! MAX MIN MAX Voc = 1.2V 0.9 0.9 Vin HIGH level Input = | Voc = 2.0V 1.4 1.4 V voltage Voc = 2.7 to 3.6V 2.0 2.0 Voc = 4.5 to 5.5V 0.7*Voc 0.7*Voc Voc = 1.2V 0.3 0.3 V LOW level Input Voc = 2.0V 0.6 0.6 Vv I | voltage Voc =2.7 to 3.6V 08 08 Voc = 4.5 to 5.5 0.3Voc 0.3Voc Vec = 1.2V; V| = Vin or VIL; -lo = 100A 1.2 Vec = 2.0V; V| = Vin or VIL; -lo = 100A 1.8 2.0 18 HIGH level output ve 7 voltage; all outputs Vec =2.7V; V| = Vin or VIL; lo = 100A 2.5 2.7 2.5 Vv Vec =3.0V; V| = Vin or VIL; -lo = 100A 2.8 3.0 2.8 Vou Veco = 4.5V;V) = Vin or ViL-lo = 100pA 4.3 4.5 43 HIGH level output | vg = 3.0V;V) = Viy or Vii;-lo = 6MA 2.40 | 2.82 2.20 voltage; : Vv STANDARD outputs Vec = 4.5V;V| = Vin or VIL; -lo =12mA 3.60 4.20 3.50 Vec = 1.2V; V| = Vin or VIL; lo = 100A 0 Vec = 2.0V; V| = Vin or VIL; lo = 100A 0 0.2 0.2 LOW level output yo voltage; all outputs Vec =2.7V; V| = Vin or VIL; lo = 100A 0 0.2 0.2 Vv Vec = 3.0V;V| = Vin or VIL; lo = 100A 0 0.2 0.2 VoL Voo = 4.5V;V) = Vin or Viz Io = 100UA 0 0.2 0.2 LOW level output | Vgg = 3.0V:V) = Viq oF Vit; lo = 6mA 0.25 | 0.40 0.50 voltage; : Vv STANDARD outputs Vec = 4.5V;V| = Vin or VIL; lo = 12mA 0.35 0.55 0.65 1998 May 29Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 DC CHARACTERISTICS FOR THE LV FAMILY (Continued) Over recommended operating conditions voltages are referenced to GND (ground = OV) LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT -40C to +85C -40C to +125C Input leakage I current Voc = 5.5V; Vi = Voc or GND 1.0 1.0 LA Quiescent supply _ Vie a loc current: MSI Vec = 5.5V; V| = Vec or GND; lo =0 20.0 160 pA Additional Alec quiescent supply Voc = 2.7V to 3.6V; V| = Voc 0.6V 500 850 pA current per input NOTE: 1. All typical values are measured at Tamp = 25C. AC CHARACTERISTICS GND = OV; t, = t} = 2.5ns; C_ = 50pF; RL = 1KQ LIMITS LIMITS CONDITION 6 SYMBOL PARAMETER WAVEFORM A0 to +85 C 740 to +125 C | UNIT Vec(V) MIN TYP! MAX | MIN MAX 1.2 - 75 - - - ; 2.0 - 26 32 - 41 tpuutern | op pagation delay Figure 1 27 = 19 24 | 30 ns n 3.0 to 3.6 - 142 19 - 24 4.5 to 5.5 - - 16 - 20 1.2 - 80 - - - 2.0 - 27 44 - 56 Propagation delay . tPHL MR to Q, Figure 2 2.7 20 33 41 ns 3.0 to 3.6 - 154 26 - 33 4.5 to 5.5 - - 22 - 28 ; 2.0 34 9 - 4 - tw vig Pulse with Figure 1 27 25 6 | 30 = ns 3.0 to 3.6 20 52 - 24 - 2.0 34 10 - 4 - Master reset pulse . tw width LOW - Figure 2 27 25 8 = 30 - ns 3.0 to 3.6 20 62 - 24 - 1.2 - -10 - - - Removal time 2.0 5 4 ~ 5 ~ trem MR to CP Figure 2 a7 5 3 = 5 = ns 3.0 to 3.6 5 22 - 5 - 1.2 - 20 - - - Set-up time 2.0 22 7 ~ 26 ~ t Figure 3 ns * D, to CP 9 2.7 16 5 - 19 - 3.0 to 3.6 13 42 - 15 - 1.2 - -10 - - - Hold time . 2.0 5 4 - 5 _ t Figure 3 ns " Dy to CP 9 27 5 =3 = 5 = 3.0 to 3.6 5 22 - 5 - 2.0 14 40 - 12 - Maximum clock . fmax pulse frequency Figure 1 2.7 19 75 - 16 - MHz 3.0 to 3.6 24 1002 - 20 - NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at Voc = 3.3V. 3. Typical value measured at Voc = 5.0V. 1998 May 29 6Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 AC WAVEFORMS Vu = 1.5V at Voc = 2.7V s 3.6V Vu = 0.5V * Voc at Voc < 2.7V and = 4.5V Vo and Voy are the typical output voltage drop that occur with the output load. vi cP INPUT GND ---- Vo--- cP INPUT GND VoH =< eee eee eee ee eee Qn OUTPUT Vou Qn OUTPUT Vo SV00371 Figure 3. Data set-up and hold times for the data input (D,) SV00370 NOTE: The shaded areas indicate when the input is permitted to change for Figure 1. The clock (CP) to output (Q,) propagation delays, the predictable output performance. clock pulse width and the maximum clock pulse frequency TEST CIRCUIT Veo vi Vo V PULSE \ / GENERATOR D.U.T. MR INPUT 50pF \ vm Vm ) Rr ok R= 1k GND | I t tw trem = = = = = = Vet rp le CP INPUT Vu Test Circuit for Outputs GND DEFINITIONS m tPHL R_ = Load resistor Vou C. = Load capacitance includes jig and probe capacitiance Qn OUTPUT Ry = Termination resistance should be equal to Zour of pulse generators. Vol - ----------- eer TEST Vec vi teLHAPHL <2.7V Voc 2.7-3.6V 2.7V 24.5V Voc $V00372 svo0902 Figure 2. The master reset (MR) pulse width, the master reset Figure 4. Load circuitry for switching times to output (Q,,) propagations delay and the master reset to clock (CP) removal time 1998 May 29 7Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ~< D |< seating plane 2aaapleaban A een 1 index | Ip - - - - oe - a | E | I be UU GG A a 1 | 10 0 5 10 mm be scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ag (1) (1) z) UNIT | max. | min. | max. b by D E e 1 L Me Mu w max. 1.73 0.53 0.36 26.92 6.40 3.60 8.25 10.0 mm 42) 051 | 32 1 430 | 038 | 0.23 | 2654] 622 | 254 | 762 | 305 | 780 | 33 | 2254 | 20 . 0.068 0.021 0.014 1.060 0.25 0.14 0.32 0.39 inches | 0.17 | 0.020 | 0.13 | 951 | 0.015 | 0.009 | 1.045 | 0.24 | %19 | 939 | 42 | 0.31 | 033 | OOF | 2.078 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ $OT146-1 $C603 | oe on og 1998 May 29 8Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 $020: plastic small outline package; 20 leads; body width 7.5 mm SOT 163-1 - p - +4] fa oo 7 inn an) iT; -oS = = = = c= My Nee GI y | . He ve =lv OA] male 20 4 I 1 | \ Qa a | a | A2 Ay a Poa A pin 1 index 8 L t ~! Lp oF you 1 4 10 detail X [e] + | p 0 5 10mm L 1 1 1 1 l 1 1 1 1 J scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | vax. | 41 | Az | As | bp ce | DM] EM) 6 He L Lp Q v w y | 2M] 6 0.30 | 2.45 0.49 | 0.32 | 13.0] 7.6 10.65 11 11 0.9 2.65 mm o.10 | 225 | ?8 | o36 | 023] 126] 74 | 17 | 1000] 14 | o4 1.0 | O25 | 025 | 01 0.4 8 o / 0.012 | 0.096 0.019 | 0.013} 0.51 | 0.30 0.42 0.043 | 0.043 0.035 | 0 0.10 inches 0.004 | 0.089 | " | 0.014 | 0.009] 0.49 | 0.29 | 295] o.a9 | 9-9 | oo16 | 0.039} O07 | O01 | 9-94 | gore Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUE DATE IEC JEDEC EIAJ See SOT163-1 O75E04 MS-013AC a Oso ba 1998 May 29Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E ~p>a] LTT iJ pL! ly He =v oA) | *HARARIAARAR Ou t | we Fe | ct TWEHOEE.. 0 2.5 5mm oot DIMENSIONS (mm are the original dimensions) UNIT max. A; | Ao | As | bp c pM | eM | e HE L Lp Q v w y Zz | 6 mm | 20 | 505 | 165 | 92 | 025 | 009 | 70 | s2 |] 76 | 128] oes | or | 2 1] ot | os | oe Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAu PROJECTION SOT339-1 MO-150AE | oe pos ISSUE DATE 1998 May 29 10Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger 74LV273 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 rl He S~< =|V@/A| shooadl ; po ! a a Az [> FAs) A pin 1 index I t 1 rye | OOH BOON Ds [e] a Pp 0 2.5 Smm root DIMENSIONS (mm are the original dimensions) unit | | Ar | Az | As | bp | | DM) e@] e | He | Le | ue} a] v | wi y | 2M] 6 nm | +10 | 938 | 985 [ozs] 0%] 92 | 85 | 48 [ows] 68 | 10 [975] 24 [oa [ow] or | 98 | & Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT360-1 MO-153AC os } Oo be ISSUE DATE 1998 May 29 11Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edgetrigger 74LV273 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published ata later date. Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. aps ar . This data sheet contains Final Specifications. Philips Semiconductors reserves the rightto make changes Product Specification Full Production . . an . . F at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. 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