Features * 64-Mbit Flash and 16-Mbit PSRAM * Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package * 2.7V to 3.1V Operating Voltage Flash * Single Voltage Read/Write Operation: 2.65V to 3.6V * Access Time - 70 ns * Sector Erase Architecture * * * * * * * * * * * * - One Hundred Twenty-seven 32K Word Sectors with Individual Write Lockout - Eight 4K Word Sectors with Individual Write Lockout Fast Word Program Time - 10 s Typical Sector Erase Time: 32K Word Sectors - 700 ms; 4K Word Sectors - 100 ms Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 10 mA Active - 15 A Standby VPP Pin for Write Protection and Accelerated Program Operation WP Pin for Sector Protection RESET Input for Device Initialization Flexibel Sector Protection Top or Bottom Boot Block Configuration Available 128-bit Protection Register Minimum 100,000 Erase Cycles Common Flash Interface (CFI) 64-megabit Flash + 16-megabit PSRAM Stack Memory AT52BC6402D AT52BC6402DT Preliminary PSRAM * 16-megabit (1M x 16) * 2.7V to 3.1V VCC * 70 ns Access Time Device Number AT52BC6402D AT52BC6402DT Flash Boot Location Flash Plane Configuration PSRAM Configuration Bottom 64M (4M x 16) 16M (1M x 16) Top 64M (4M x 16) 16M (1M x 16) Flash & PSRAM Datasheets Datasheets PDF File 64M Flash Memory: AT49BV640D(T) Acrobat Document 16M PSRAM: 2FHY64UD16161B Acrobat Document 3619A-STKD-7/06 1. Pin Configuration Pin Name Function A0 - A19, A21 Common Address Input for 16M PSRAM/Flash, Flash Address Input CE Flash Chip Enable OE Flash Output Enable WE Flash Write Enable RESET Flash Reset PW Flash Write Protect VPP Flash Power Supply for Accelerated Program Operation VCC Flash Power GND Flash Ground I/O0 - I/O15 Data Inputs/Outputs NC No Connect LB PSRAM Lower Byte UB PSRAM Upper Byte PVCC PSRAM Power PGND PSRAM Ground PCS1 PSRAM Chip Select 1 PCS2 Low Power Modes PWE PSRAM Write Enable POE PSRAM Output Enable 2. AT52BC6402D(T) (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 NC NC A20 A11 A15 A14 A13 A12 GND NC NC NC A16 A8 A10 A9 I/O15 PWE I/O14 I/O7 I/O13 I/O6 I/O5 NC NC A B C WE A21 I/O4 D PGND RESET I/O12 PCS2 PVCC VCC E WP VPP A19 LB UB POE A18 A17 A7 NC A5 A4 I/O11 I/O10 I/O2 I/O3 I/O9 I/O8 I/O0 I/O1 A6 A3 A2 A1 PCS1 A0 CE GND OE NC F G H NC 2 NC AT52BC6402D(T) Preliminary 3619A-STKD-7/06 AT52BC6402D(T) Preliminary 3. Block Diagram ADDRESS OE WE POE PWE RESET CE VPP PW 16-Mbit PSRAM 64-Mbit FLASH LB UB PCS1 PCS2 DATA 4. Description The AT52BC6402D(T) combines a 64-megabit Flash (4M x 16) and an 16-megabit PSRAM (organized as 1M x 16) in a stacked 66-ball CBGA package. The stacked modules operate at 2.7V to 3.1V in the extended temperature range. 5. Absolute Maximum Ratings Temperature under Bias ................................. -55 C to +85 C Storage Temperature .................................... -55 C to +150 C All Input Voltages except VPP (including NC Pins) with Respect to Ground ..............................-0.2V to VCC +0.3V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on VPP with Respect to Ground ..................................-0.2V to + 10.0V All Output Voltages with Respect to Ground ..............................-0.2V to VCC +0.3V 6. DC and AC Operating Range AT52BC6402D(T)-70CU Operating Temperature (Case) -30 C - 85 C VCC Power Supply 2.7V to 3.1V 3 3619A-STKD-7/06 7. Flash Operating Modes Mode CE OE WE RESET VPP(2) Ai I/O Read VIL VIL VIH VIH X Ai DOUT Ai DIN Program/Erase Program Inhibit Software Product Identification VIL VIH VIL VIH VIL X VIH VIH X VIL X X X VILPP(4) VIL Standby/Program Inhibit VIL VIH VIHPP VIH PSRAM Must Be High-Z X VIH X(1) X VIH X Output Disable X VIH X VIH X Reset X X X VIL X Notes: (3) PSRAM Operation A0 = VIL, A1 - A19 = VIL Manufacturer Code A0 = VIH, A1 - A19 = VIL Device Code X High Z High Z X Any PSRAM Operation is Allowed High Z 1. X can be VIL or VIH 2. The VPP pin can be tied to VCC. For faster program operations, VPP can be set to 9.5V 0.5V. 3. VIHPP (min) = 1.65V 4. VILPP (max) = 0.4V 8. Functional Description PCS1 PCS2 POE PWE LB UB I/O0 - 7 I/O8 - 15 Mode Power H H X(1) X(1) X(1) X(1) High-Z High-Z Deselected Standby (1) L X (1) (1) (1) (1) L(1) H X(1) X X X(1) High-Z Deselected High-Z High-Z Output Disabled Active (1) High-Z High-Z Output Disabled Active H L H H H X(1) L High-Z High-Z Output Disabled Active L H DOUT High-Z Lower Byte Read Active H L High-Z DOUT Upper Byte Read Active L L DOUT DOUT Word Read Active L H DIN High-Z Lower Byte Write Active H L High-Z DIN Upper Byte Write Active L L DIN DIN Word Write Active H X H X(1) 4 H High-Z H L Note: H X H L L X Low-power Modes L Flash Operation Any Flash Operation Allowed Flash Must Be High Z 1. X means don't care (must be low or high state). AT52BC6402D(T) Preliminary 3619A-STKD-7/06 AT52BC6402D(T) Preliminary 9. Ordering Information 9.1 Green Package (Pb/Halide-free) tACC (ns) Ordering Code AT52BC6402D-70CU Flash Boot Block Flash Plane Architecture Bottom 64M - Single Bank 70 AT52BC6402DT-70CU Top 64M - Single Bank PSRAM Package Operation Range 1M x 16 66C7 Extended (-30 to 85 C) Package Type 66C7 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 5 3619A-STKD-7/06 10. Packaging Information 10.1 66C7 - CBGA 0.12 C E C Seating Plane Marked A1 Identifier D Side View A1 Top View A 0.60 REF E1 A1 Ball Corner e 1.20 REF A B C D D1 E COMMON DIMENSIONS (Unit of Measure = mm) F G MIN NOM MAX E 9.90 10.00 10.10 E1 8.75 8.80 8.85 D 7.90 8.00 8.10 D1 5.55 5.60 5.65 A - - 1.20 A1 0.25 - - SYMBOL H e 12 11 10 9 8 7 6 5 4 3 2 1 Ob Bottom View e Ob NOTE 0.80 TYP - 0.40 - 5/01/06 R 6 2325 Orchard Parkway San Jose, CA 95131 TITLE 66C7, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 66C7 REV. A AT52BC6402D(T) Preliminary 3619A-STKD-7/06 AT52BC6402D(T) Preliminary 11. Revision History Revision No. History Revision A - July 2006 * Initial Release 7 3619A-STKD-7/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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