InvenSense Inc. 1197 Borregas Ave, Sunnyvale, CA 94089 U.S.A. Tel: +1 (408) 988-7339 Fax: +1 (408) 988-8104 Website: www.invensense.com Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification Revision 1.4 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 CONTENTS 1 DOCUMENT INFORMATION .............................................................................................................................. 4 1.1 1.2 1.3 1.4 REVISION HISTORY ............................................................................................................................................. 4 PURPOSE AND SCOPE ........................................................................................................................................... 5 PRODUCT OVERVIEW .......................................................................................................................................... 5 APPLICATIONS ..................................................................................................................................................... 5 2 FEATURES ............................................................................................................................................................... 6 3 ELECTRICAL CHARACTERISTICS .................................................................................................................. 7 3.1 3.2 3.3 3.4 3.5 3.6 4 APPLICATIONS INFORMATION ......................................................................................................................13 4.1 4.2 4.3 4.4 5 PIN OUT AND SIGNAL DESCRIPTION ...................................................................................................................13 TYPICAL OPERATING CIRCUIT ............................................................................................................................14 BILL OF MATERIALS FOR EXTERNAL COMPONENTS ...........................................................................................14 RECOMMENDED POWER-ON PROCEDURE...........................................................................................................15 FUNCTIONAL OVERVIEW .................................................................................................................................16 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 6 SENSOR SPECIFICATIONS ..................................................................................................................................... 7 ELECTRICAL SPECIFICATIONS .............................................................................................................................. 8 ELECTRICAL SPECIFICATIONS, CONTINUED ......................................................................................................... 9 ELECTRICAL SPECIFICATIONS, CONTINUED ........................................................................................................10 I2C TIMING CHARACTERIZATION........................................................................................................................11 ABSOLUTE MAXIMUM RATINGS .........................................................................................................................12 BLOCK DIAGRAM ...............................................................................................................................................16 OVERVIEW .........................................................................................................................................................16 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING ..........................................16 I2C SERIAL COMMUNICATIONS INTERFACE ........................................................................................................17 CLOCKING ..........................................................................................................................................................17 SENSOR DATA REGISTERS ..................................................................................................................................17 INTERRUPTS .......................................................................................................................................................17 DIGITAL-OUTPUT TEMPERATURE SENSOR .........................................................................................................17 BIAS AND LDO...................................................................................................................................................17 CHARGE PUMP ...................................................................................................................................................17 DIGITAL INTERFACE .........................................................................................................................................18 6.1 I2C SERIAL INTERFACE .......................................................................................................................................18 7 REGISTER MAP ....................................................................................................................................................22 8 REGISTER DESCRIPTION ..................................................................................................................................23 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 REGISTER 0 - WHO AM I ....................................................................................................................................23 REGISTER 21 - SAMPLE RATE DIVIDER ..............................................................................................................23 REGISTER 22 - DLPF, FULL SCALE ....................................................................................................................24 REGISTER 23 - INTERRUPT CONFIGURATION ......................................................................................................26 REGISTER 26 - INTERRUPT STATUS ....................................................................................................................26 REGISTERS 27 TO 34 - SENSOR REGISTERS.........................................................................................................27 REGISTER 62 - POWER MANAGEMENT ...............................................................................................................27 ASSEMBLY .............................................................................................................................................................29 9.1 9.2 9.3 9.4 ORIENTATION .....................................................................................................................................................29 PACKAGE DIMENSIONS.......................................................................................................................................30 PACKAGE MARKING SPECIFICATION ..................................................................................................................31 TAPE & REEL SPECIFICATION .............................................................................................................................31 2 of 39 ITG-3200 Product Specification 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 10 10.1 10.2 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 LABEL ................................................................................................................................................................33 PACKAGING ........................................................................................................................................................33 SOLDERING EXPOSED DIE PAD ...........................................................................................................................34 COMPONENT PLACEMENT ..................................................................................................................................34 PCB MOUNTING AND CROSS-AXIS SENSITIVITY ................................................................................................34 MEMS HANDLING INSTRUCTIONS .....................................................................................................................35 GYROSCOPE SURFACE MOUNT GUIDELINES .......................................................................................................35 REFLOW SPECIFICATION .....................................................................................................................................35 STORAGE SPECIFICATIONS .................................................................................................................................37 RELIABILITY ....................................................................................................................................................38 QUALIFICATION TEST POLICY ............................................................................................................................38 QUALIFICATION TEST PLAN ...............................................................................................................................38 3 of 39 ITG-3200 Product Specification 1 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Document Information 1.1 Revision History Revision Date Revision 10/23/09 1.0 Initial Release 10/28/09 1.1 02/12/2010 1.2 Edits for readability Changed full-scale range and sensitivity scale factor (Sections 2, 3.1, 5.3, and 8.3) Changed sensitivity scale factor variation over temperature (Section 3.1) Changed total RMS noise spec (Section 3.1) Added range for temperature sensor (Section 3.1) Updated VDD Power-Supply Ramp Rate specification (Sections 3.2 and 4.4) Added VLOGIC Voltage Range condition (Section 3.2) Added VLOGIC Reference Voltage Ramp Rate specification (Sections 3.2 and 4.4) Updated Start-Up Time for Register Read/Write specification (Section 3.2) Updated Input logic levels for AD0 and CLKIN (Section 3.2) Updated Level IOL specifications for the I2C interface (Section 3.3) Updated Frequency Variation Over Temperature specification for internal clock source (Section 3.4) Updated VLOGIC conditions for I2C Characterization (Section 3.5) Updated ESD specification (Section 3.6) Added termination requirements for CLKIN if unused (Section 4.1) Added recommended power-on procedure diagram (Section 4.4) Changed DLPF_CFG setting 7 to reserved (Section 8.3) Changed Reflow Specification description (Section 9.12) Removed errata specifications Description 03/05/2010 1.3 Updated temperature sensor linearity spec (Section 3.1) Updated VDD Power-Supply Ramp Rate timing figure (Sections 3.2 and 4.4) Updated VLOGIC Reference Voltage timing figure (Section 4.4) Added default values to registers (all of Section 8) Updated FS_SEL description (Section 8.3) Updated package outline drawing and dimensions (Section 9.2) Updated Reliability (Section 10.1 and 10.2) Removed Environmental Compliance (Section 11) 03/30/2010 1.4 Removed confidentiality mark 4 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 1.2 Purpose and Scope This document is a preliminary product specification, providing a description, specifications, and design related information for the ITG-3200TM. Electrical characteristics are based upon simulation results and limited characterization data of advanced samples only. Specifications are subject to change without notice. Final specifications will be updated based upon characterization of final silicon. 1.3 Product Overview The ITG-3200 is the world's first single-chip, digital-output, 3-axis MEMS gyro IC optimized for gaming, 3D mice, and 3D remote control applications. The part features enhanced bias and sensitivity temperature stability, reducing the need for user calibration. Low frequency noise is lower than previous generation devices, simplifying application development and making for more-responsive remote controls. The ITG-3200 features three 16-bit analog-to-digital converters (ADCs) for digitizing the gyro outputs, a user-selectable internal low-pass filter bandwidth, and a Fast-Mode I2C (400kHz) interface. Additional features include an embedded temperature sensor and a 2% accurate internal oscillator. This breakthrough in gyroscope technology provides a dramatic 67% package size reduction, delivers a 50% power reduction, and has inherent cost advantages compared to competing multi-chip gyro solutions. By leveraging its patented and volume-proven Nasiri-Fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the ITG-3200 package size down to a revolutionary footprint of 4x4x0.9mm (QFN), while providing the highest performance, lowest noise, and the lowest cost semiconductor packaging required for handheld consumer electronic devices. The part features a robust 10,000g shock tolerance, as required by portable consumer equipment. For power supply flexibility, the ITG-3200 has a separate VLOGIC reference pin, in addition to its analog supply pin, VDD, which sets the logic levels of its I2C interface. The VLOGIC voltage may be anywhere from 1.71V min to VDD max. 1.4 Applications Motion-enabled game controllers Motion-based portable gaming Motion-based 3D mice and 3D remote controls "No Touch" UI Health and sports monitoring 5 of 39 ITG-3200 Product Specification 2 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Features The ITG-3200 triple-axis MEMS gyroscope includes a wide range of features: Digital-output X-, Y-, and Z-Axis angular rate sensors (gyros) on one integrated circuit with a sensitivity of 14.375 LSBs per /sec and a full-scale range of 2000/sec Three integrated 16-bit ADCs provide simultaneous sampling of gyros while requiring no external multiplexer Enhanced bias and sensitivity temperature stability reduces the need for user calibration Low frequency noise lower than previous generation devices, simplifying application development and making for more-responsive motion processing Digitally-programmable low-pass filter Low 6.5mA operating current consumption for long battery life Wide VDD supply voltage range of 2.1V to 3.6V Flexible VLOGIC reference voltage allows for I2C interface voltages from 1.71V to VDD Standby current: 5A Smallest and thinnest package for portable devices (4x4x0.9mm QFN) No high pass filter needed Turn on time: 50ms Digital-output temperature sensor Factory calibrated scale factor 10,000 g shock tolerant Fast Mode I2C (400kHz) serial interface On-chip timing generator clock frequency is accurate to +/-2% over full temperature range Optional external clock inputs of 32.768kHz or 19.2MHz to synchronize with system clock MEMS structure hermetically sealed and bonded at wafer level RoHS and Green compliant 6 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 3 Electrical Characteristics 3.1 Sensor Specifications Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25C. Parameter GYRO SENSITIVITY Full-Scale Range Gyro ADC Word Length Sensitivity Scale Factor Sensitivity Scale Factor Tolerance Sensitivity Scale Factor Variation Over Temperature Nonlinearity Cross-Axis Sensitivity Unit Note 10 /s Bits LSB/(/s) % % 4 3 3 1 2 0.2 2 % % 6 6 -40C to +85C Sine wave, 100mVpp; VDD=2.2V Sine wave, 100mVpp; VDD=2.2V Sine wave, 100mVpp; VDD=2.2V Static 40 40 0.2 0.2 4 0.1 /s /s /s /s /s /s/g 1 2 5 5 5 6 GYRO NOISE PERFORMANCE Total RMS noise Rate Noise Spectral Density GYRO MECHANICAL FREQUENCIES X-Axis Y-Axis Z-Axis Frequency Separation FS_SEL=3 100Hz LPF (DLPFCFG=2) At 10Hz 0.38 0.03 /s-rms /s/Hz 1 kHz kHz kHz kHz 1 1 1 1 GYRO START-UP TIME ZRO Settling TEMPERATURE SENSOR Range Sensitivity Temperature Offset Initial Accuracy Linearity DLPFCFG=0 to 1/s of Final 50 ms 6 -30 to +85 280 -13,200 TBD 1 C LSB/C LSB C C 2 2 1 GYRO ZERO-RATE OUTPUT (ZRO) Initial ZRO Tolerance ZRO Variation Over Temperature Power-Supply Sensitivity (1-10Hz) Power-Supply Sensitivity (10 - 250Hz) Power-Supply Sensitivity (250Hz - 100kHz) Linear Acceleration Sensitivity TEMPERATURE RANGE Specified Temperature Range Notes: 1. 2. 3. 4. 5. 6. Conditions Min FS_SEL=3 FS_SEL=3 25C Max 2000 16 14.375 -6 Best fit straight line; 25C Between any two axes Typical 30 27 24 1.7 35oC 35oC Best fit straight line (-30C to +85C) -40 +6 33 30 27 36 33 30 85 C Tested in production Based on characterization of 30 pieces over temperature on evaluation board or in socket Based on design, through modeling and simulation across PVT Typical. Randomly selected part measured at room temperature on evaluation board or in socket Based on characterization of 5 pieces over temperature Tested on 5 parts at room temperature 7 of 39 2 2, 5 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 3.2 Electrical Specifications Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25C. Parameters VDD POWER SUPPLY Operating Voltage Range Power-Supply Ramp Rate Conditions Monotonic ramp. Ramp rate is 10% to 90% of the final value (see Figure in Section 4.4) Min 2.1 0 Normal Operating Current Sleep Mode Current VLOGIC REFERENCE VOLTAGE Voltage Range VLOGIC Ramp Rate Typical Max Units Notes 3.6 5 V ms 2 2 mA A 1 5 6.5 5 VLOGIC must be VDD at all times Monotonic ramp. Ramp rate is 10% to 90% of the final value (see Figure in Section 4.4) 1.71 VDD V 1 ms Normal Operating Current 100 A START-UP TIME FOR REGISTER READ/WRITE 20 ms 2 I C ADDRESS AD0 = 0 AD0 = 1 DIGITAL INPUTS (AD0, CLKIN) VIH, High Level Input Voltage VIL, Low Level Input Voltage CI, Input Capacitance DIGITAL OUTPUT (INT) VOH, High Level Output Voltage VOL, Low Level Output Voltage VOL.INT1, INT Low-Level Output Voltage Output Leakage Current tINT, INT Pulse Width Notes: 1. 2. 4. 5. 6. 1101000 1101001 OPEN=1 LATCH_INT_EN=0 0.1*VLOGIC 5 V V pF 5 5 7 0.1*VLOGIC V V 2 2 0.1 V 2 nA s 4 4 0.9*VLOGIC OPEN=1, 0.3mA sink current 5 6 6 0.9*VLOGIC OPEN=0, Rload=1M OPEN=0, Rload=1M 6 100 50 Tested in production Based on characterization of 30 pieces over temperature on evaluation board or in socket Typical. Randomly selected part measured at room temperature on evaluation board or in socket Based on characterization of 5 pieces over temperature Guaranteed by design 8 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 3.3 Electrical Specifications, continued Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, T A=25C. Parameters I2C I/O (SCL, SDA) VIL, LOW-Level Input Voltage VIH, HIGH-Level Input Voltage Vhys, Hysteresis VOL1, LOW-Level Output Voltage IOL, LOW-Level Output Current Output Leakage Current tof, Output Fall Time from VIHmax to VILmax CI, Capacitance for Each I/O pin Conditions 3mA sink current VOL = 0.4V VOL = 0.6V Cb bus cap. in pF Typical Units Notes -0.5 to 0.3*VLOGIC 0.7*VLOGIC to VLOGIC + 0.5V 0.1*VLOGIC 0 to 0.4 3 6 100 V V V V mA mA nA 2 2 2 2 2 2 4 20+0.1Cb to 250 ns 2 10 pF 5 Notes: 2. Based on characterization of 5 pieces over temperature. 4. Typical. Randomly selected part measured at room temperature on evaluation board or in socket 5. Guaranteed by design 9 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 3.4 Electrical Specifications, continued Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25C. Parameters Conditions INTERNAL CLOCK SOURCE Sample Rate, Fast CLKSEL=0, 1, 2, or 3 DLPFCFG=0 SAMPLERATEDIV = 0 Sample Rate, Slow DLPFCFG=1,2,3,4,5, or 6 SAMPLERATEDIV = 0 Clock Frequency Initial Tolerance CLKSEL=0, 25C CLKSEL=1,2,3; 25C CLKSEL=0 CLKSEL=1,2,3 CLKSEL=1,2,3 Frequency Variation over Temperature PLL Settling Time EXTERNAL 32.768kHz CLOCK External Clock Frequency External Clock Jitter Sample Rate, Fast CLKSEL=4 Sample Rate, Slow DLPFCFG=1,2,3,4,5, or 6 SAMPLERATEDIV = 0 Cycle-to-cycle rms DLPFCFG=0 SAMPLERATEDIV = 0 PLL Settling Time EXTERNAL 19.2MHz CLOCK External Clock Frequency Sample Rate, Fast CLKSEL=5 Sample Rate, Slow DLPFCFG=1,2,3,4,5, or 6 SAMPLERATEDIV = 0 DLPFCFG=0 SAMPLERATEDIV = 0 PLL Settling Time Charge Pump Clock Frequency Frequency Notes: 1. 2. 3. 4. 5. 1st Stage, 25C 2nd Stage, 25C Over temperature Min Typical Units Notes 8 kHz 4 1 kHz 4 -15 to +10 +/-1 1 % % % % ms 1 1 2 2 3 32.768 1 to 2 8.192 kHz s kHz 3 3 3 1.024 kHz 3 1 ms 3 19.2 8 MHz kHz 3 3 1 kHz 3 1 ms 3 8.5 68 +/-15 MHz MHz % 5 5 5 -2 -1 Max +2 +1 Tested in production Based on characterization of 30 pieces over temperature on evaluation board or in socket Based on design, through modeling and simulation across PVT Typical. Randomly selected part measured at room temperature on evaluation board or in socket Based on characterization of 5 pieces over temperature. 10 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 2 3.5 I C Timing Characterization Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.8V5%, 2.5V5%, 3.0V5%, or 3.3V5%, TA=25C. Parameters I2C TIMING fSCL, SCL Clock Frequency Conditions I2C FAST-MODE Min 0 Typical Max Units Notes 400 kHz 1 tHD.STA, (Repeated) START Condition Hold Time 0.6 us 1 tLOW, SCL Low Period 1.3 us 1 tHIGH, SCL High Period 0.6 us 1 tSU.STA, Repeated START Condition Setup Time 0.6 us 1 tHD.DAT, SDA Data Hold Time 0 us 1 tSU.DAT, SDA Data Setup Time 100 ns 1 tr, SDA and SCL Rise Time Cb bus cap. from 10 to 400pF 20+0.1Cb 300 ns 1 tf, SDA and SCL Fall Time Cb bus cap. from 10 to 400pF 20+0.1Cb 300 ns 1 tSU.STO, STOP Condition Setup Time 0.6 us 1 tBUF, Bus Free Time Between STOP and START Condition Cb, Capacitive Load for each Bus Line 1.3 us 1 400 pF 2 tVD.DAT, Data Valid Time 0.9 us 1 tVD.ACK, Data Valid Acknowledge Time 0.9 us 1 Notes: 1. Based on characterization of 5 pieces over temperature on evaluation board or in socket 2. Guaranteed by design I2C Bus Timing Diagram 11 of 39 ITG-3200 Product Specification 3.6 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Absolute Maximum Ratings Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. Absolute Maximum Ratings Parameter Rating Supply Voltage, VDD -0.5V to +6V VLOGIC Input Voltage Level -0.5V to VDD + 0.5V REGOUT -0.5V to 2V Input Voltage Level (CLKIN, AD0) -0.5V to VDD + 0.5V SCL, SDA, INT -0.5V to VLOGIC + 0.5V CPOUT (2.1V VDD 3.6V ) -0.5V to 30V Acceleration (Any Axis, unpowered) 10,000g for 0.3ms Operating Temperature Range -40C to +105C Storage Temperature Range -40C to +125C 1.5kV (HBM); 200V (MM) Electrostatic Discharge (ESD) Protection 12 of 39 ITG-3200 Product Specification 4 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Applications Information 4.1 Pin Out and Signal Description Number Pin Pin Description 1 CLKIN 8 VLOGIC Optional external reference clock input. Connect to GND if unused. 9 AD0 10 REGOUT 12 INT Interrupt digital output (totem pole or open-drain) 13 VDD Power supply voltage 18 GND Power supply ground Digital IO supply voltage. VLOGIC must be VDD at all times. I2C Slave Address LSB Regulator filter capacitor connection 11 RESV-G 6, 7, 19, 21, 22 RESV Reserved - Connect to ground. 20 CPOUT 23 SCL I2C serial clock 24 SDA I2C serial data 2, 3, 4, 5, 14, 15, 16, 17 NC Not internally connected. May be used for PCB trace routing. Reserved. Do not connect. Charge pump capacitor connection Top View SDA SCL RESV RESV CPOUT RESV 24 23 22 21 20 19 CLKIN 1 18 GND NC 2 17 NC NC 3 16 NC NC 4 15 NC NC 5 14 NC RESV 6 13 VDD +Z +Y ITG-3200 7 8 9 10 11 12 RESV VLOGIC AD0 REGOUT RESV-G INT QFN Package 24-pin, 4mm x 4mm x 0.9mm ITG -32 00 +X Orientation of Axes of Sensitivity and Polarity of Rotation 13 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 4.2 Typical Operating Circuit SDA SCL CLKIN 24 23 GND C1 2.2nF 22 21 20 19 1 18 2 17 3 16 GND ITG-3200 4 15 VDD 5 14 6 13 7 8 9 10 11 12 C2 0.1F VLOGIC GND GND INT C3 0.1F AD0 C4 10nF GND GND Typical Operating Circuit 4.3 Bill of Materials for External Components Component Label Specification Quantity Charge Pump Capacitor C1 Ceramic, X7R, 2.2nF 10%, 50V 1 VDD Bypass Capacitor C2 Ceramic, X7R, 0.1F 10%, 4V 1 Regulator Filter Capacitor C3 Ceramic, X7R, 0.1F 10%, 2V 1 VLOGIC Bypass Capacitor C4 Ceramic, X7R, 10nF 10%, 4V 1 14 of 39 ITG-3200 Product Specification Recommended Power-On Procedure All Voltages at 0V 4.4 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Power-Up Sequencing 1. TVDDR is VDD rise time: Time for VDD to rise from 10% to 90% of its final value TVDDR 2. TVDDR is 5msec 90% VDD 3. TVLGR is VLOGIC rise time: Time for VLOGIC to rise from 10% to 90% of its final value 10% TVLGR 90% VLOGIC 10% TVLG - VDD 4. TVLGR is 1msec 5. TVLG-VDD is the delay from the start of VDD ramp to the start of VLOGIC rise 6. TVLG-VDD is 0 to 20msec but VLOGIC amplitude must always be VDD amplitude 7. VDD and VLOGIC must be monotonic ramps 15 of 39 ITG-3200 Product Specification 5 5.1 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Functional Overview Block Diagram Optional 1 CLOCK ITG-3200 Clock X Gyro Signal Conditioning ADC Y Gyro Interrupt Status Register Config Register Signal Conditioning ADC Sensor Register Z Gyro Signal Conditioning ADC Temp Sensor Charge Pump 20 CPOUT Interrupt 12 9 2 I C Serial Interface 23 24 INT AD0 SCL SDA FIFO ADC Factory Cal Bias & LDO 13 VDD 8 VLOGIC 18 GND 10 REGOUT 5.2 Overview The ITG-3200 consists of the following key blocks and functions: Three-axis MEMS rate gyroscope sensors with individual 16-bit ADCs and signal conditioning I2C serial communications interface Clocking Sensor Data Registers Interrupts Digital-Output Temperature Sensor Bias and LDO Charge Pump 5.3 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning The ITG-3200 consists of three independent vibratory MEMS gyroscopes, which detect rotational rate about the X (roll), Y (pitch), and Z (yaw) axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a deflection that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors is preset to 2000 degrees per second (/s). The ADC output rate is programmable up to a maximum of 8,000 samples per second down to 3.9 samples per second, and user-selectable lowpass filters enable a wide range of cut-off frequencies. 16 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 2 5.4 I C Serial Communications Interface The ITG-3200 communicates to a system processor using the I2C serial interface, and the device always acts as a slave when communicating to the system processor. The logic level for communications to the master is set by the voltage on the VLOGIC pin. The LSB of the of the I2C slave address is set by pin 9 (AD0). 5.5 Clocking The ITG-3200 has a flexible clocking scheme, allowing for a variety of internal or external clock sources for the internal synchronous circuitry. This synchronous circuitry includes the signal conditioning, ADCs, and various control circuits and registers. An on-chip PLL provides flexibility in the allowable inputs for generating this clock. Allowable internal sources for generating the internal clock are: An internal relaxation oscillator (less accurate) Any of the X, Y, or Z gyros' MEMS oscillators (with an accuracy of 2% over temperature) Allowable external clocking sources are: 32.768kHz square wave 19.2MHz square wave Which source to select for generating the internal synchronous clock depends on the availability of external sources and the requirements for clock accuracy. There are also start-up conditions to consider. When the ITG-3200 first starts up, the device operates off of its internal clock until programmed to operate from another source. This allows the user, for example, to wait for the MEMS oscillators to stabilize before they are selected as the clock source. 5.6 Sensor Data Registers The sensor data registers contain the latest gyro and temperature data. They are read-only registers, and are accessed via the Serial Interface. Data from these registers may be read at any time, however, the interrupt function may be used to determine when new data is available. 5.7 Interrupts Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock sources); and (2) new data is available to be read from the Data registers. The interrupt status can be read from the Interrupt Status register. 5.8 Digital-Output Temperature Sensor An on-chip temperature sensor and ADC are used to measure the ITG-3200 die temperature. The readings from the ADC can be read from the Sensor Data registers. 5.9 Bias and LDO The bias and LDO sections take in an unregulated VDD supply from 2.1V to 3.6V and generate the internal supply and the references voltages and currents required by the ITG-3200. The LDO output is bypassed by a capacitor at REGOUT. Additionally, the part has a VLOGIC reference voltage which sets the logic levels for its I2C interface. 5.10 Charge Pump An on-board charge pump generates the high voltage (25V) required to drive the MEMS oscillators. Its output is bypassed by a capacitor at CPOUT. 17 of 39 ITG-3200 Product Specification 6 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Digital Interface 2 6.1 I C Serial Interface The internal registers and memory of the ITG-3200 can be accessed using I2C at up to 400kHz. Serial Interface Pin Number Pin Name Pin Description 8 VLOGIC Digital IO supply voltage. VLOGIC must be VDD at all times. 9 AD0 I2C Slave Address LSB 23 SCL I2C serial clock 24 SDA I2C serial data 2 6.1.1 I C Interface I2C is a two wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master. The ITG-3200 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400kHz. The slave address of the ITG-3200 devices is b110100X which is 7 bits long. The LSB bit of the 7 bit address is determined by the logic level on pin 9. This allows two ITG-3200 devices to be connected to the same I2C bus. When used in this configuration, the address of the one of the devices should be b1101000 (pin 9 is logic low) and the address of the other should be b1101001 (pin 9 is logic high). The I2C address is stored in register 0 (WHO_AM_I register). I2C Communications Protocol START (S) and STOP (P) Conditions Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below). Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition. SDA SCL S P START condition STOP condition START and STOP Conditions 18 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Data Format / Acknowledge I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse. If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line (see figure below). DATA OUTPUT BY TRANSMITTER (SDA) not acknowledge DATA OUTPUT BY RECEIVER (SDA) acknowledge SCL FROM MASTER 1 2 8 9 clock pulse for acknowledgement START condition Acknowledge on the I2C Bus Communications After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the exception of start and stop conditions. SDA SCL 1-7 8 1-7 9 8 9 1-7 8 9 S START ADDRESS condition P R/W ACK DATA ACK DATA ACK STOP condition Complete I2C Data Transfer 19 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification To write the internal ITG-3200 device registers, the master transmits the start condition (S), followed by the I2C address and the write bit (0). At the 9th clock cycle (when the clock is high), the ITG-3200 device acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the ITG-3200 acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ITG-3200 device automatically increments the register address and loads the data to the appropriate register. The following figures show single and two-byte write sequences. Single-Byte Write Sequence Master Slave S AD+W RA ACK DATA P ACK ACK Burst Write Sequence Master Slave S AD+W RA ACK DATA ACK DATA ACK P ACK To read the internal ITG-3200 device registers, the master first transmits the start condition (S), followed by the I2C address and the write bit (0). At the 9th clock cycle (when clock is high), the ITG acknowledges the transfer. The master then writes the register address that is going to be read. Upon receiving the ACK signal from the ITG-3200, the master transmits a start signal followed by the slave address and read bit. As a result, the ITG-3200 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9 th clock cycle. To read multiple bytes of data, the master can output an acknowledge signal (ACK) instead of a not acknowledge (NACK) signal. In this case, the ITG3200 automatically increments the register address and outputs data from the appropriate register. The following figures show single and two-byte read sequences. Single-Byte Read Sequence Master Slave S AD+W RA ACK S AD+R ACK NACK ACK P DATA Burst Read Sequence Master Slave S AD+W RA ACK S ACK AD+R ACK ACK DATA NACK P DATA 20 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 I2C Terms Signal S Description Start Condition: SDA goes from high to low while SCL is high AD Slave I2C address W Write bit (0) R Read bit (1) ACK NACK RA DATA P Acknowledge: SDA line is low while the SCL line is high at the 9 th clock cycle Not-Acknowledge: SDA line stays high at the 9th clock cycle ITG-3200 internal register address Transmit or received data Stop condition: SDA going from low to high while SCL is high 21 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 7 Register Map Addr Hex Addr Decimal Register Name R/W Bit7 0 0 WHO_AM_I R/W - 15 21 SMPLRT_DIV R/W 16 22 DLPF_FS R/W Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ID Bit0 - SMPLRT_DIV - - - FS_SEL DLPF_CFG 17 23 INT_CFG R/W ACTL OPEN LATCH_ INT_EN INT_ ANYRD_ 2CLEAR 1A 26 INT_STATUS R - - - - 1B 27 TEMP_OUT_H R 1C 28 TEMP_OUT_L R TEMP_OUT_L 1D 29 GYRO_XOUT_H R GYRO_XOUT_H 1E 30 GYRO_XOUT_L R GYRO_XOUT_L 1F 31 GYRO_YOUT_H R GYRO_YOUT_H 20 32 GYRO_YOUT_L R GYRO_YOUT_L 21 33 GYRO_ZOUT_H R GYRO_ZOUT_H 22 34 GYRO_ZOUT_L R GYRO_ZOUT_L 3E 62 PWR_MGM R/W - - ITG_RDY _EN ITG_RDY - RAW_ RDY_ EN - RAW_ DATA_ RDY TEMP_OUT_H H_RESET SLEEP STBY_XG STBY_YG STBY_ZG CLK_SEL 22 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 8 Register Description This section details each register within the InvenSense ITG-3200 gyroscope. Note that any bit that is not defined should be set to zero in order to be compatible with future InvenSense devices. The register space allows single-byte reads and writes, as well as burst reads and writes. When performing burst reads or writes, the memory pointer will increment until either (1) reading or writing is terminated by the master, or (2) the memory pointer reaches certain reserved registers between registers 33 and 60. 8.1 Register 0 - Who Am I Type: Read/Write Register (Hex) 0 Register (Decimal) 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ID - Bit0 - Description: This register is used to verify the identity of the device. Parameters: ID Contains the I2C address of the device, which can also be changed by writing to this register. The Power-On-Reset value of Bit6: Bit1 is 110 100. 8.2 Register 21 - Sample Rate Divider Type: Read/Write Register (Hex) 15 Register (Decimal) 21 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SMPLRT_DIV Default Value 00h Description: This register determines the sample rate of the ITG-3200 gyros. The gyros outputs are sampled internally at either 1kHz or 8kHz, determined by the DLPF_CFG setting (see register 22). This sampling is then filtered digitally and delivered into the sensor registers after the number of cycles determined by this register. The sample rate is given by the following formula: Fsample = Finternal / (divider+1), where Finternal is either 1kHz or 8kHz As an example, if the internal sampling is at 1kHz, then setting this register to 7 would give the following: Fsample = 1kHz / (7 + 1) = 125Hz, or 8ms per sample Parameters: SMPLRT_DIV Sample rate divider: 0 to 255 23 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 8.3 Register 22 - DLPF, Full Scale Type: Read/Write Register (Hex) 16 Register (Decimal) 22 Bit7 Bit6 Bit5 - Bit4 Bit3 Bit2 FS_SEL Bit1 Bit0 DLPF_CFG Default Value 00h Description: This register configures several parameters related to the sensor acquisition. The FS_SEL parameter allows setting the full-scale range of the gyro sensors, as described in the table below. The power-on-reset value of FS_SEL is 00h. Set to 03h for proper operation. FS_SEL FS_SEL Gyro Full-Scale Range 0 1 2 3 Reserved Reserved Reserved 2000/sec The DLPF_CFG parameter sets the digital low pass filter configuration. It also determines the internal sampling rate used by the device as shown in the table below. DLPF_CFG Parameters: FS_SEL DLPF_CFG DLPF_CFG Low Pass Filter Bandwidth Internal Sample Rate 0 1 2 3 4 5 6 7 256Hz 188Hz 98Hz 42Hz 20Hz 10Hz 5Hz Reserved 8kHz 1kHz 1kHz 1kHz 1kHz 1kHz 1kHz Reserved Full scale selection for gyro sensor data Digital low pass filter configuration and internal sampling rate configuration 24 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification DLPF Characteristics: The gain and phase responses of the digital low pass filter settings (DLPF_CFG) are shown below: Bode Diagram Magnitude (dB) 0 -10 6 5 4 3 21 0 -20 -30 -40 -50 Phase (deg) 0 -45 6 5 4 3 2 1 0 -90 0 1 10 2 10 3 10 10 Frequency (Hz) Gain and Phase vs. Digital Filter Setting Bode Diagram 2 Magnitude (dB) 0 -2 6 5 4 3 2 1 0 -4 -6 Phase (deg) 0 -5 -10 -15 6 0 10 5 4 3 2 1 1 10 0 2 10 3 10 Frequency (Hz) Gain and Phase vs. Digital Filter Setting, Showing Passband Details 25 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 8.4 Register 23 - Interrupt Configuration Type: Read/Write Register (Hex) Register (Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default Value 17 23 ACTL OPEN LATCH_ INT_EN INT_ ANYRD_ 2CLEAR 0 ITG_RDY_ EN 0 RAW_ RDY_ EN 00h Description: This register configures the interrupt operation of the device. The interrupt output pin (INT) configuration can be set, the interrupt latching/clearing method can be set, and the triggers for the interrupt can be set. Note that if the application requires reading every sample of data from the ITG-3200 part, it is best to enable the raw data ready interrupt (RAW_RDY_EN). This allows the application to know when new sample data is available. Parameters: ACTL OPEN LATCH_INT_EN INT_ANYRD_2CLEAR ITG_RDY_EN RAW_RDY_EN 0 8.5 Logic level for INT output pin - 1=active low, 0=active high Drive type for INT output pin - 1=open drain, 0=push-pull Latch mode - 1=latch until interrupt is cleared, 0=50us pulse Latch clear method - 1=any register read, 0=status register read only Enable interrupt when device is ready (PLL ready after changing clock source) Enable interrupt when data is available Load zeros into Bits 1 and 3 of the Interrupt Configuration register. Register 26 - Interrupt Status Type: Read only Register (Hex) Register (Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default Value 1A 26 - - - - - ITG_RDY - RAW_ DATA_ RDY 00h Description: This register is used to determine the status of the ITG-3200 interrupts. Whenever one of the interrupt sources is triggered, the corresponding bit will be set. The polarity of the interrupt pin (active high/low) and the latch type (pulse or latch) has no affect on these status bits. Use the Interrupt Configuration register (23) to enable the interrupt triggers. If the interrupt is not enabled, the associated status bit will not get set. In normal use, the RAW_DATA_RDY interrupt is used to determine when new sensor data is available in either the sensor registers (27 to 32). Interrupt Status bits get cleared as determined by INT_ANYRD_2CLEAR in the interrupt configuration register (23). Parameters: ITG_RDY RAW_DATA_RDY PLL ready Raw data is ready 26 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 8.6 Registers 27 to 34 - Sensor Registers Type: Read only Register (Hex) Register (Decimal) 1B 1C 1D 1E 1F 20 21 22 27 28 29 30 31 32 33 34 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TEMP_OUT_H TEMP_OUT_L GYRO_XOUT_H GYRO_XOUT_L GYRO_YOUT_H GYRO_YOUT_L GYRO_ZOUT_H GYRO_ZOUT_L Description: These registers contain the gyro and temperature sensor data for the ITG-3200 parts. At any time, these values can be read from the device; however it is best to use the interrupt function to determine when new data is available. Parameters: TEMP_OUT_H/L GYRO_XOUT_H/L GYRO_YOUT_H/L GYRO_ZOUT_H/L 8.7 16-bit temperature data (2's complement format) 16-bit X gyro output data (2's complement format) 16-bit Y gyro output data (2's complement format) 16-bit Y gyro output data (2's complement format) Register 62 - Power Management Type: Read/Write Register (Hex) Register (Decimal) Bit7 Bit6 Bit5 3E 62 H_RESET SLEEP STBY _XG Bit4 Bit3 STBY _YG STBY _ZG Bit2 Bit1 CLK_SEL Bit0 Default Value 00h Description: This register is used to manage the power control, select the clock source, and to issue a master reset to the device. Setting the SLEEP bit in the register puts the device into very low power sleep mode. In this mode, only the serial interface and internal registers remain active, allowing for a very low standby current. Clearing this bit puts the device back into normal mode. To save power, the individual standby selections for each of the gyros should be used if any gyro axis is not used by the application. The CLK_SEL setting determines the device clock source as follows: CLK_SEL CLK_SEL 0 1 2 3 4 5 6 7 Clock Source Internal oscillator PLL with X Gyro reference PLL with Y Gyro reference PLL with Z Gyro reference PLL with external 32.768kHz reference PLL with external 19.2MHz reference Reserved Reserved On power up, the ITG-3200 defaults to the internal oscillator. It is highly recommended that the device is configured to use one of the gyros (or an external clock) as the clock reference, due to the improved stability. 27 of 39 ITG-3200 Product Specification Parameters: H_RESET SLEEP STBY_XG STBY_YG STBY_ZG CLK_SEL Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Reset device and internal registers to the power-up-default settings Enable low power sleep mode Put gyro X in standby mode (1=standby, 0=normal) Put gyro Y in standby mode (1=standby, 0=normal) Put gyro Z in standby mode (1=standby, 0=normal) Select device clock source 28 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 9 9.1 Assembly Orientation The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. +Z +Y ITG -32 00 +X Orientation of Axes of Sensitivity and Polarity of Rotation 29 of 39 ITG-3200 Product Specification 9.2 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Package Dimensions Top View Bottom View Package Dimensions 30 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 9.3 Package Marking Specification TOP VIEW InvenSense ITG-3200 XXXXXX-XX XX YYWW X Part number Lot traceability code Foundry code Package Vendor Code Rev Code YY = Year Code WW = Work Week Package Marking Specification 9.4 Tape & Reel Specification Tape Dimensions 31 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification Reel Outline Drawing Reel Dimensions and Package Size REEL (mm) PKG SIZE L V W Z 4x4 330 100 13.2 2.2 User Direction of Feed Package Orientation Cover Tape (Anti-Static) Carrier Tape (Anti-Static) Label Pin 1 Terminal Tape Reel Tape and Reel Specification Reel Specifications Quantity Per Reel 5,000 Reels per Box 1 Boxes Per Carton (max) 3 full pizza boxes packed in the center of the carton, buffered by two empty pizza boxes (front and back). Pcs/Carton (max) 15,000 32 of 39 ITG-3200 Product Specification 9.5 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Label Location of Label 9.6 Packaging Anti-static Label Moisture-Sensitive Caution Label Tape & Reel Label Moisture Barrier Bag With Labels Reel in Box Moisture-Sensitive Caution Label Box with Tape & Reel Label 33 of 39 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 ITG-3200 Product Specification 9.7 Soldering Exposed Die Pad The ITG-3200 has very low active and standby current consumption. The exposed die pad is not required for heat sinking, and should not be soldered to the PCB since soldering to it contributes to performance changes due to package thermo-mechanical stress. 9.8 Component Placement Testing indicates that there are no specific design considerations other than generally accepted industry design practices for component placement near the ITG-3200 multi-axis gyroscope to prevent noise coupling, and thermo-mechanical stress. 9.9 PCB Mounting and Cross-Axis Sensitivity Orientation errors of the gyroscope mounted to the printed circuit board can cause cross-axis sensitivity in which one gyro responds to rotation about another axis, for example, the X-axis gyroscope responding to rotation about the Y or Z axes. The orientation mounting errors are illustrated in the figure below. Z Y ITG - 32 00 Package Gyro Axes ( ) Relative to PCB Axes ( X ) with Orientation Errors ( and ) The table below shows the cross-axis sensitivity as a percentage of the specified gyroscope's sensitivity for a given orientation error. Cross-Axis Sensitivity vs. Orientation Error Orientation Error Cross-Axis Sensitivity ( or ) (sin or sin) 0 0% 0.5 0.87% 1 1.75% The specification for cross-axis sensitivity in Section 3 includes the effect of the die orientation error with respect to the package. 34 of 39 ITG-3200 Product Specification 9.10 Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 MEMS Handling Instructions MEMS (Micro Electro-Mechanical Systems) are a time-proven, robust technology used in hundreds of millions of consumer, automotive and industrial products. MEMS devices consist of microscopic moving mechanical structures. They differ from conventional IC products even though they can be found in similar packages. Therefore, MEMS devices require different handling precautions than conventional ICs prior to mounting onto printed circuit boards (PCBs). The ITG-3200 gyroscope has a shock tolerance of 10,000g. InvenSense packages its gyroscopes as it deems proper for protection against normal handling and shipping. It recommends the following handling precautions to prevent potential damage. Individually packaged or trays of gyroscopes should not be dropped onto hard surfaces. Components placed in trays could be subject to g-forces in excess of 10,000g if dropped. Printed circuit boards that incorporate mounted gyroscopes should not be separated by manually snapping apart. This could also create g-forces in excess of 10,000g. 9.11 Gyroscope Surface Mount Guidelines Any material used in the surface mount assembly process of the MEMS gyroscope should be free of restricted RoHS elements or compounds. Pb-free solders should be used for assembly. In order to assure gyroscope performance, several industry standard guidelines need to be considered for surface mounting. These guidelines are for both printed circuit board (PCB) design and surface mount assembly and are available from packaging and assembly houses. When using MEMS gyroscope components in plastic packages, package stress due to PCB mounting and assembly could affect the output offset and its value over a wide range of temperatures. This is caused by the mismatch between the Coefficient Temperature Expansion (CTE) of the package material and the PCB. Care must be taken to avoid package stress due to mounting. 9.12 Reflow Specification The approved solder reflow curve shown in the figure below conforms to IPC/JEDEC J-STD-020D.01 (Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices) with a maximum peak temperature (Tc = 260C). This is specified for component-supplier reliability qualification testing using lead-free solder for package thicknesses less than 1.6 mm. The reliability qualification pre-conditioning used by InvenSense incorporates three of these conforming reflow cycles. All temperatures refer to the topside of the QFN package, as measured on the package body surface. Customer solder-reflow processes should use the solder manufacturer's recommendations, making sure to never exceed the constraints listed in the table and figure below, as these represent the maximum tolerable ratings for the device. For optimum results, production solder reflow processes should use lower temperatures, reduced exposure times to high temperatures, and lower ramp-up and ramp-down rates than those listed below. 35 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 Approved IR/Convection Solder Reflow Curve Temperature Set Points for IR / Convection Reflow Corresponding to Figure Above Step Setting A B C D Troom TSmin TSmax TLiquidus TPmin E Temp (C) 25 150 200 217 CONSTRAINTS Time (sec) Rate (C/sec) 60 < tBC < 120 r(TLiquidus-TPmax) < 3 255 r(TLiquidus-TPmax) < 3 [< TPmax-5C, 250C] F TPmax 260 tAF < 480 r(TLiquidus-TPmax) < 3 255 tEG < 30 r(TPmax-TLiquidus) < 4 217 25 60 < tDH < 120 [< TPmax, 260C] G TPmin [< TPmax-5C, 250C] H I TLiquidus Troom 36 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 9.13 Storage Specifications The storage specification of the ITG-3200 gyroscope conforms to IPC/JEDEC J-STD-020C Moisture Sensitivity Level (MSL) 3. Storage Specifications for ITG-3200 Calculated shelf-life in moisture-sealed bag 12 months -- Storage conditions: <40C and <90% RH After opening moisture-sealed bag 168 hours -- Storage conditions: ambient 30C at 60% RH 37 of 39 ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 10 Reliability 10.1 Qualification Test Policy InvenSense's products complete a Qualification Test Plan before being released to production. The Qualification Test Plan follows the JEDEC 47D Standards, "Stress-Test-Driven Qualification of Integrated Circuits," with the individual tests described below. 10.2 Qualification Test Plan Accelerated Life Tests TEST High Temperature Operating Life (HTOL/LFR) Steady-State Temperature Humidity Bias Life (1) High Temperature Storage Life Method/Condition JEDEC JESD22-A108C, Dynamic, 3.63V biased, Tj>125C [read-points 168, 500, 1000 hours] JEDEC JESD22-A101C, 85C/85%RH [read-points 168, 500 hours], Information Only 1000 hours] JEDEC JESD22-A103C, Cond. A, 125C Non-Bias Bake [read-points 168, 500, 1000 hours] Lot Quantity Sample / Lot Acc / Reject Criteria 3 77 (0/1) 3 77 (0/1) 77 (0/1) 3 Device Component Level Tests Method/Condition Lot Quantity Sample / Lot Acc / Reject Criteria ESD-HBM JEDEC JESD22-A114F, Class 2 (1.5KV) 1 3 (0/1) ESD-MM JEDEC JESD22-A115-A, Class B (200V) 1 3 (0/1) Latch Up JEDEC JESD78B Level 2, 125C, +/- 100mA 1 6 (0/1) JEDEC JESD22-B104C, Mil-Std-883, method 2002, Cond. D, 10,000g's, 0.3ms, X,Y,Z - 6 directions, 5 times/direction JEDEC JESD22-B103B, Variable Frequency (random), Cond. B, 5-500Hz, X,Y,Z - 4 times/direction JEDEC JESD22-A104D Condition N, -40C to +85C, Soak Mode 2, 100 cycles 3 5 (0/1) 3 5 (0/1) 3 77 (0/1) Lot Quantity Sample / Lot Acc / Reject Criteria 1 5 1 40 TEST Mechanical Shock Vibration Temperature Cycling (1) Board Level Tests TEST Method/Condition/ Board Mechanical Shock JEDEC JESD22-B104C,Mil-Std-883, method 2002, Cond. D, 10,000g's, 0.3ms, +-X,Y,Z - 6 directions, 5 times/direction JEDEC JESD22-A104D Condition N, -40C to +85C, Soak Mode 2, 100 cycles Board T/C (1) - Tests are preceded by MSL3 Preconditioning in accordance with JEDEC JESD22-A113F 38 of 39 (0/1) (0/1) ITG-3200 Product Specification Document Number: PS-ITG-3200A-00-01.4 Revision: 1.4 Release Date: 03/30/2010 This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights. Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment. InvenSense, InvenSense logo, ITG, and ITG-3200 are trademarks of InvenSense, Inc. (c)2009 InvenSense, Inc. All rights reserved. 39 of 39