InvenSense Inc.
1197 Borregas Ave, Sunnyvale, CA 94089 U.S.A.
Tel: +1 (408) 988-7339 Fax: +1 (408) 988-8104
Website: www.invensense.com
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
ITG-3200
Product Specification
Revision 1.4
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
2 of 39
CONTENTS
1 DOCUMENT INFORMATION .............................................................................................................................. 4
1.1 REVISION HISTORY ............................................................................................................................................. 4
1.2 PURPOSE AND SCOPE ........................................................................................................................................... 5
1.3 PRODUCT OVERVIEW .......................................................................................................................................... 5
1.4 APPLICATIONS ..................................................................................................................................................... 5
2 FEATURES ............................................................................................................................................................... 6
3 ELECTRICAL CHARACTERISTICS .................................................................................................................. 7
3.1 SENSOR SPECIFICATIONS ..................................................................................................................................... 7
3.2 ELECTRICAL SPECIFICATIONS .............................................................................................................................. 8
3.3 ELECTRICAL SPECIFICATIONS, CONTINUED ......................................................................................................... 9
3.4 ELECTRICAL SPECIFICATIONS, CONTINUED ........................................................................................................10
3.5 I2C TIMING CHARACTERIZATION........................................................................................................................11
3.6 ABSOLUTE MAXIMUM RATINGS .........................................................................................................................12
4 APPLICATIONS INFORMATION ......................................................................................................................13
4.1 PIN OUT AND SIGNAL DESCRIPTION ...................................................................................................................13
4.2 TYPICAL OPERATING CIRCUIT ............................................................................................................................14
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS ...........................................................................................14
4.4 RECOMMENDED POWER-ON PROCEDURE ...........................................................................................................15
5 FUNCTIONAL OVERVIEW .................................................................................................................................16
5.1 BLOCK DIAGRAM ...............................................................................................................................................16
5.2 OVERVIEW .........................................................................................................................................................16
5.3 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING ..........................................16
5.4 I2C SERIAL COMMUNICATIONS INTERFACE ........................................................................................................17
5.5 CLOCKING ..........................................................................................................................................................17
5.6 SENSOR DATA REGISTERS ..................................................................................................................................17
5.7 INTERRUPTS .......................................................................................................................................................17
5.8 DIGITAL-OUTPUT TEMPERATURE SENSOR .........................................................................................................17
5.9 BIAS AND LDO ...................................................................................................................................................17
5.10 CHARGE PUMP ...................................................................................................................................................17
6 DIGITAL INTERFACE .........................................................................................................................................18
6.1 I2C SERIAL INTERFACE .......................................................................................................................................18
7 REGISTER MAP ....................................................................................................................................................22
8 REGISTER DESCRIPTION ..................................................................................................................................23
8.1 REGISTER 0 – WHO AM I ....................................................................................................................................23
8.2 REGISTER 21 – SAMPLE RATE DIVIDER ..............................................................................................................23
8.3 REGISTER 22 – DLPF, FULL SCALE ....................................................................................................................24
8.4 REGISTER 23 – INTERRUPT CONFIGURATION ......................................................................................................26
8.5 REGISTER 26 – INTERRUPT STATUS ....................................................................................................................26
8.6 REGISTERS 27 TO 34 – SENSOR REGISTERS.........................................................................................................27
8.7 REGISTER 62 – POWER MANAGEMENT ...............................................................................................................27
9 ASSEMBLY .............................................................................................................................................................29
9.1 ORIENTATION .....................................................................................................................................................29
9.2 PACKAGE DIMENSIONS .......................................................................................................................................30
9.3 PACKAGE MARKING SPECIFICATION ..................................................................................................................31
9.4 TAPE & REEL SPECIFICATION .............................................................................................................................31
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
3 of 39
9.5 LABEL ................................................................................................................................................................33
9.6 PACKAGING ........................................................................................................................................................33
9.7 SOLDERING EXPOSED DIE PAD ...........................................................................................................................34
9.8 COMPONENT PLACEMENT ..................................................................................................................................34
9.9 PCB MOUNTING AND CROSS-AXIS SENSITIVITY ................................................................................................34
9.10 MEMS HANDLING INSTRUCTIONS .....................................................................................................................35
9.11 GYROSCOPE SURFACE MOUNT GUIDELINES .......................................................................................................35
9.12 REFLOW SPECIFICATION .....................................................................................................................................35
9.13 STORAGE SPECIFICATIONS .................................................................................................................................37
10 RELIABILITY ....................................................................................................................................................38
10.1 QUALIFICATION TEST POLICY ............................................................................................................................38
10.2 QUALIFICATION TEST PLAN ...............................................................................................................................38
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
4 of 39
1 Document Information
1.1 Revision History
Revision
Date
Revision
Description
10/23/09
1.0
Initial Release
10/28/09
1.1
Edits for readability
02/12/2010
1.2
Changed full-scale range and sensitivity scale factor (Sections 2, 3.1, 5.3, and 8.3)
Changed sensitivity scale factor variation over temperature (Section 3.1)
Changed total RMS noise spec (Section 3.1)
Added range for temperature sensor (Section 3.1)
Updated VDD Power-Supply Ramp Rate specification (Sections 3.2 and 4.4)
Added VLOGIC Voltage Range condition (Section 3.2)
Added VLOGIC Reference Voltage Ramp Rate specification (Sections 3.2 and 4.4)
Updated Start-Up Time for Register Read/Write specification (Section 3.2)
Updated Input logic levels for AD0 and CLKIN (Section 3.2)
Updated Level IOL specifications for the I2C interface (Section 3.3)
Updated Frequency Variation Over Temperature specification for internal clock source
(Section 3.4)
Updated VLOGIC conditions for I2C Characterization (Section 3.5)
Updated ESD specification (Section 3.6)
Added termination requirements for CLKIN if unused (Section 4.1)
Added recommended power-on procedure diagram (Section 4.4)
Changed DLPF_CFG setting 7 to reserved (Section 8.3)
Changed Reflow Specification description (Section 9.12)
Removed errata specifications
03/05/2010
1.3
Updated temperature sensor linearity spec (Section 3.1)
Updated VDD Power-Supply Ramp Rate timing figure (Sections 3.2 and 4.4)
Updated VLOGIC Reference Voltage timing figure (Section 4.4)
Added default values to registers (all of Section 8)
Updated FS_SEL description (Section 8.3)
Updated package outline drawing and dimensions (Section 9.2)
Updated Reliability (Section 10.1 and 10.2)
Removed Environmental Compliance (Section 11)
03/30/2010
1.4
Removed confidentiality mark
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
5 of 39
1.2 Purpose and Scope
This document is a preliminary product specification, providing a description, specifications, and design related
information for the ITG-3200TM. Electrical characteristics are based upon simulation results and limited
characterization data of advanced samples only. Specifications are subject to change without notice. Final
specifications will be updated based upon characterization of final silicon.
1.3 Product Overview
The ITG-3200 is the world’s first single-chip, digital-output, 3-axis MEMS gyro IC optimized for gaming, 3D mice,
and 3D remote control applications. The part features enhanced bias and sensitivity temperature stability, reducing the
need for user calibration. Low frequency noise is lower than previous generation devices, simplifying application
development and making for more-responsive remote controls.
The ITG-3200 features three 16-bit analog-to-digital converters (ADCs) for digitizing the gyro outputs, a user-selectable
internal low-pass filter bandwidth, and a Fast-Mode I2C (400kHz) interface. Additional features include an embedded
temperature sensor and a 2% accurate internal oscillator. This breakthrough in gyroscope technology provides a
dramatic 67% package size reduction, delivers a 50% power reduction, and has inherent cost advantages compared to
competing multi-chip gyro solutions.
By leveraging its patented and volume-proven Nasiri-Fabrication platform, which integrates MEMS wafers with
companion CMOS electronics through wafer-level bonding, InvenSense has driven the ITG-3200 package size down to
a revolutionary footprint of 4x4x0.9mm (QFN), while providing the highest performance, lowest noise, and the lowest
cost semiconductor packaging required for handheld consumer electronic devices. The part features a robust 10,000g
shock tolerance, as required by portable consumer equipment.
For power supply flexibility, the ITG-3200 has a separate VLOGIC reference pin, in addition to its analog supply pin,
VDD, which sets the logic levels of its I2C interface. The VLOGIC voltage may be anywhere from 1.71V min to VDD
max.
1.4 Applications
Motion-enabled game controllers
Motion-based portable gaming
Motion-based 3D mice and 3D remote controls
“No Touch” UI
Health and sports monitoring
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
6 of 39
2 Features
The ITG-3200 triple-axis MEMS gyroscope includes a wide range of features:
Digital-output X-, Y-, and Z-Axis angular rate sensors (gyros) on one integrated circuit with a sensitivity of
14.375 LSBs per °/sec and a full-scale range of ±2000°/sec
Three integrated 16-bit ADCs provide simultaneous sampling of gyros while requiring no external multiplexer
Enhanced bias and sensitivity temperature stability reduces the need for user calibration
Low frequency noise lower than previous generation devices, simplifying application development and making
for more-responsive motion processing
Digitally-programmable low-pass filter
Low 6.5mA operating current consumption for long battery life
Wide VDD supply voltage range of 2.1V to 3.6V
Flexible VLOGIC reference voltage allows for I2C interface voltages from 1.71V to VDD
Standby current: 5µA
Smallest and thinnest package for portable devices (4x4x0.9mm QFN)
No high pass filter needed
Turn on time: 50ms
Digital-output temperature sensor
Factory calibrated scale factor
10,000 g shock tolerant
Fast Mode I2C (400kHz) serial interface
On-chip timing generator clock frequency is accurate to +/-2% over full temperature range
Optional external clock inputs of 32.768kHz or 19.2MHz to synchronize with system clock
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
7 of 39
3 Electrical Characteristics
3.1 Sensor Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25°C.
Conditions
Min
Typical
Max
Unit
Note
FS_SEL=3
±2000
º/s
4
16
Bits
3
FS_SEL=3
14.375
LSB/(º/s)
3
25°C
-6
+6
%
1
±10
%
2
Best fit straight line; 25°C
0.2
%
6
2
%
6
±40
º/s
1
-40°C to +85°C
±40
º/s
2
Sine wave, 100mVpp; VDD=2.2V
0.2
º/s
5
Sine wave, 100mVpp; VDD=2.2V
0.2
º/s
5
Sine wave, 100mVpp; VDD=2.2V
4
º/s
5
Static
0.1
º/s/g
6
FS_SEL=3
100Hz LPF (DLPFCFG=2)
0.38
º/s-rms
1
At 10Hz
0.03
º/s/√Hz
2
30
33
36
kHz
1
27
30
33
kHz
1
24
27
30
kHz
1
Between any two axes
1.7
kHz
1
DLPFCFG=0
to ±1º/s of Final
50
ms
6
-30 to +85
ºC
2
280
LSB/ºC
2
35oC
-13,200
LSB
1
35oC
TBD
°C
Best fit straight line (-30°C to +85°C)
±1
°C
2, 5
-40
85
ºC
Notes:
1. Tested in production
2. Based on characterization of 30 pieces over temperature on evaluation board or in socket
3. Based on design, through modeling and simulation across PVT
4. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
5. Based on characterization of 5 pieces over temperature
6. Tested on 5 parts at room temperature
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
8 of 39
3.2 Electrical Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
VDD POWER SUPPLY
Operating Voltage Range
2.1
3.6
V
2
Power-Supply Ramp Rate
Monotonic ramp. Ramp rate
is 10% to 90% of the final
value (see Figure in Section
4.4)
0
5
ms
2
Normal Operating Current
6.5
mA
1
Sleep Mode Current
5
µA
5
VLOGIC REFERENCE
VOLTAGE
Voltage Range
VLOGIC must be ≤VDD at all
times
1.71
VDD
V
VLOGIC Ramp Rate
Monotonic ramp. Ramp rate is
10% to 90% of the final value
(see Figure in Section 4.4)
1
ms
6
Normal Operating Current
100
µA
START-UP TIME FOR
REGISTER READ/WRITE
20
ms
5
I2C ADDRESS
AD0 = 0
1101000
6
AD0 = 1
1101001
6
DIGITAL INPUTS (AD0,
CLKIN)
VIH, High Level Input Voltage
0.9*VLOGIC
V
5
VIL, Low Level Input Voltage
0.1*VLOGIC
V
5
CI, Input Capacitance
5
pF
7
DIGITAL OUTPUT (INT)
VOH, High Level Output Voltage
OPEN=0, Rload=1MΩ
0.9*VLOGIC
V
2
VOL, Low Level Output Voltage
OPEN=0, Rload=1MΩ
0.1*VLOGIC
V
2
VOL.INT1, INT Low-Level Output
Voltage
OPEN=1, 0.3mA sink current
0.1
V
2
Output Leakage Current
OPEN=1
100
nA
4
tINT, INT Pulse Width
LATCH_INT_EN=0
50
µs
4
Notes:
1. Tested in production
2. Based on characterization of 30 pieces over temperature on evaluation board or in socket
4. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
5. Based on characterization of 5 pieces over temperature
6. Guaranteed by design
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
9 of 39
3.3 Electrical Specifications, continued
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25°C.
Parameters
Conditions
Typical
Units
Notes
I2C I/O (SCL, SDA)
VIL, LOW-Level Input Voltage
-0.5 to 0.3*VLOGIC
V
2
VIH, HIGH-Level Input Voltage
0.7*VLOGIC to VLOGIC + 0.5V
V
2
Vhys, Hysteresis
0.1*VLOGIC
V
2
VOL1, LOW-Level Output Voltage
3mA sink current
0 to 0.4
V
2
IOL, LOW-Level Output Current
VOL = 0.4V
VOL = 0.6V
3
6
mA
mA
2
2
Output Leakage Current
100
nA
4
tof, Output Fall Time from VIHmax to
VILmax
Cb bus cap. in pF
20+0.1Cb to 250
ns
2
CI, Capacitance for Each I/O pin
10
pF
5
Notes:
2. Based on characterization of 5 pieces over temperature.
4. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
5. Guaranteed by design
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
10 of 39
3.4 Electrical Specifications, continued
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.71V to VDD, TA=25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
INTERNAL CLOCK SOURCE
CLKSEL=0, 1, 2, or 3
Sample Rate, Fast
DLPFCFG=0
SAMPLERATEDIV = 0
8
kHz
4
Sample Rate, Slow
DLPFCFG=1,2,3,4,5, or 6
SAMPLERATEDIV = 0
1
kHz
4
Clock Frequency Initial Tolerance
CLKSEL=0, 25°C
-2
+2
%
1
CLKSEL=1,2,3; 25°C
-1
+1
%
1
Frequency Variation over Temperature
CLKSEL=0
-15 to +10
%
2
CLKSEL=1,2,3
+/-1
%
2
PLL Settling Time
CLKSEL=1,2,3
1
ms
3
EXTERNAL 32.768kHz CLOCK
CLKSEL=4
External Clock Frequency
32.768
kHz
3
External Clock Jitter
Cycle-to-cycle rms
1 to 2
µs
3
Sample Rate, Fast
DLPFCFG=0
SAMPLERATEDIV = 0
8.192
kHz
3
Sample Rate, Slow
DLPFCFG=1,2,3,4,5, or 6
SAMPLERATEDIV = 0
1.024
kHz
3
PLL Settling Time
1
ms
3
EXTERNAL 19.2MHz CLOCK
CLKSEL=5
External Clock Frequency
19.2
MHz
3
Sample Rate, Fast
DLPFCFG=0
SAMPLERATEDIV = 0
8
kHz
3
Sample Rate, Slow
DLPFCFG=1,2,3,4,5, or 6
SAMPLERATEDIV = 0
1
kHz
3
PLL Settling Time
1
ms
3
Charge Pump Clock Frequency
Frequency
1st Stage, 25°C
8.5
MHz
5
2nd Stage, 25°C
68
MHz
5
Over temperature
+/-15
%
5
Notes:
1. Tested in production
2. Based on characterization of 30 pieces over temperature on evaluation board or in socket
3. Based on design, through modeling and simulation across PVT
4. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
5. Based on characterization of 5 pieces over temperature.
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
11 of 39
3.5 I2C Timing Characterization
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.8V±5%, 2.5V±5%, 3.0V±5%, or 3.3V±5%,
TA=25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
I2C TIMING
I2C FAST-MODE
fSCL, SCL Clock Frequency
0
400
kHz
1
tHD.STA, (Repeated) START Condition Hold Time
0.6
us
1
tLOW, SCL Low Period
1.3
us
1
tHIGH, SCL High Period
0.6
us
1
tSU.STA, Repeated START Condition Setup Time
0.6
us
1
tHD.DAT, SDA Data Hold Time
0
us
1
tSU.DAT, SDA Data Setup Time
100
ns
1
tr, SDA and SCL Rise Time
Cb bus cap. from 10 to 400pF
20+0.1Cb
300
ns
1
tf, SDA and SCL Fall Time
Cb bus cap. from 10 to 400pF
20+0.1Cb
300
ns
1
tSU.STO, STOP Condition Setup Time
0.6
us
1
tBUF, Bus Free Time Between STOP and START
Condition
1.3
us
1
Cb, Capacitive Load for each Bus Line
400
pF
2
tVD.DAT, Data Valid Time
0.9
us
1
tVD.ACK, Data Valid Acknowledge Time
0.9
us
1
Notes:
1. Based on characterization of 5 pieces over temperature on evaluation board or in socket
2. Guaranteed by design
I2C Bus Timing Diagram
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
12 of 39
3.6 Absolute Maximum Ratings
Stresses above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute
maximum ratings conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, VDD
-0.5V to +6V
VLOGIC Input Voltage Level
-0.5V to VDD + 0.5V
REGOUT
-0.5V to 2V
Input Voltage Level (CLKIN, AD0)
-0.5V to VDD + 0.5V
SCL, SDA, INT
-0.5V to VLOGIC + 0.5V
CPOUT (2.1V ≤ VDD ≤ 3.6V )
-0.5V to 30V
Acceleration (Any Axis, unpowered)
10,000g for 0.3ms
Operating Temperature Range
-40°C to +105°C
Storage Temperature Range
-40°C to +125°C
Electrostatic Discharge (ESD) Protection
1.5kV (HBM); 200V
(MM)
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
13 of 39
4 Applications Information
4.1 Pin Out and Signal Description
Number
Pin
Pin Description
1
CLKIN
Optional external reference clock input. Connect to GND if unused.
8
VLOGIC
Digital IO supply voltage. VLOGIC must be ≤ VDD at all times.
9
AD0
I2C Slave Address LSB
10
REGOUT
Regulator filter capacitor connection
12
INT
Interrupt digital output (totem pole or open-drain)
13
VDD
Power supply voltage
18
GND
Power supply ground
11
RESV-G
Reserved - Connect to ground.
6, 7, 19, 21, 22
RESV
Reserved. Do not connect.
20
CPOUT
Charge pump capacitor connection
23
SCL
I2C serial clock
24
SDA
I2C serial data
2, 3, 4, 5, 14, 15, 16, 17
NC
Not internally connected. May be used for PCB trace routing.
ITG-3200
+Z
+X
+Y
7 8 9 10 11 12
RESV
VLOGIC
AD0
REGOUT
RESV-G
INT
13
18
17
16
15
14
NC
NC
NC
VDD
NC
GND
6
1
2
3
4
5
NC
NC
NC
RESV
NC
CLKIN
24 23 22 21 20 19
RESV
CPOUT
RESV
RESV
SCL
SDA
ITG-3200
QFN Package
24-pin, 4mm x 4mm x 0.9mm Orientation of Axes of Sensitivity
and Polarity of Rotation
Top View
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
14 of 39
4.2 Typical Operating Circuit
AD0
Typical Operating Circuit
7 8 9 10 11 12
13
18
17
16
15
14
6
1
2
3
4
5
24 23 22 21 20 19
ITG-3200
CLKIN
GND
GND
INT
GND
VDD
SCL
SDA
C1
2.2nF
C3
0.1µF
C2
0.1µF
VLOGIC
GND
C4
10nF
GND
GND
4.3 Bill of Materials for External Components
Component
Label
Specification
Quantity
Charge Pump Capacitor
C1
Ceramic, X7R, 2.2nF ±10%, 50V
1
VDD Bypass Capacitor
C2
Ceramic, X7R, 0.1µF ±10%, 4V
1
Regulator Filter Capacitor
C3
Ceramic, X7R, 0.1µF ±10%, 2V
1
VLOGIC Bypass Capacitor
C4
Ceramic, X7R, 10nF ±10%, 4V
1
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
15 of 39
4.4 Recommended Power-On Procedure
TVLGR
VLOGIC
VDD
TVDDR
All Voltages at 0V
Power-Up Sequencing
1. TVDDR is VDD rise time: Time for VDD to
rise from 10% to 90% of its final value
2. TVDDR is ≤5msec
3. TVLGR is VLOGIC rise time: Time for
VLOGIC to rise from 10% to 90% of its
final value
4. TVLGR is ≤1msec
5. TVLG-VDD is the delay from the start of
VDD ramp to the start of VLOGIC rise
6. TVLG-VDD is 0 to 20msec but VLOGIC
amplitude must always be ≤VDD
amplitude
7. VDD and VLOGIC must be monotonic
ramps
90%
10%
90%
10%
TVLG - VDD
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
16 of 39
5 Functional Overview
5.1 Block Diagram
VDD
CLOCK ITG-3200
Charge
Pump
AD0
SCL
SDA
Temp
Sensor ADC
ADCY Gyro Signal
Conditioning
ADCX Gyro Signal
Conditioning
Bias & LDO
1
9
23
24
I2C Serial
Interface
GND REGOUT
Config
Register
Clock
CPOUT
Interrupt INT
12
Sensor
Register
20 13 18 10
Interrupt
Status
Register
VLOGIC
8
Optional
ADCZ Gyro Signal
Conditioning
Factory Cal
FIFO
5.2 Overview
The ITG-3200 consists of the following key blocks and functions:
Three-axis MEMS rate gyroscope sensors with individual 16-bit ADCs and signal conditioning
I2C serial communications interface
Clocking
Sensor Data Registers
Interrupts
Digital-Output Temperature Sensor
Bias and LDO
Charge Pump
5.3 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning
The ITG-3200 consists of three independent vibratory MEMS gyroscopes, which detect rotational rate about the X
(roll), Y (pitch), and Z (yaw) axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a
deflection that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to
produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit
Analog-to-Digital Converters (ADCs) to sample each axis.
The full-scale range of the gyro sensors is preset to ±2000 degrees per second (°/s). The ADC output rate is
programmable up to a maximum of 8,000 samples per second down to 3.9 samples per second, and user-selectable low-
pass filters enable a wide range of cut-off frequencies.
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
17 of 39
5.4 I2C Serial Communications Interface
The ITG-3200 communicates to a system processor using the I2C serial interface, and the device always acts as a slave
when communicating to the system processor. The logic level for communications to the master is set by the
voltage on the VLOGIC pin. The LSB of the of the I2C slave address is set by pin 9 (AD0).
5.5 Clocking
The ITG-3200 has a flexible clocking scheme, allowing for a variety of internal or external clock sources for the
internal synchronous circuitry. This synchronous circuitry includes the signal conditioning, ADCs, and various control
circuits and registers. An on-chip PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
An internal relaxation oscillator (less accurate)
Any of the X, Y, or Z gyros’ MEMS oscillators (with an accuracy of ±2% over temperature)
Allowable external clocking sources are:
32.768kHz square wave
19.2MHz square wave
Which source to select for generating the internal synchronous clock depends on the availability of external sources and
the requirements for clock accuracy. There are also start-up conditions to consider. When the ITG-3200 first starts up,
the device operates off of its internal clock until programmed to operate from another source. This allows the user, for
example, to wait for the MEMS oscillators to stabilize before they are selected as the clock source.
5.6 Sensor Data Registers
The sensor data registers contain the latest gyro and temperature data. They are read-only registers, and are accessed
via the Serial Interface. Data from these registers may be read at any time, however, the interrupt function may be used
to determine when new data is available.
5.7 Interrupts
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT
pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an
interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock sources); and (2) new
data is available to be read from the Data registers. The interrupt status can be read from the Interrupt Status register.
5.8 Digital-Output Temperature Sensor
An on-chip temperature sensor and ADC are used to measure the ITG-3200 die temperature. The readings from the
ADC can be read from the Sensor Data registers.
5.9 Bias and LDO
The bias and LDO sections take in an unregulated VDD supply from 2.1V to 3.6V and generate the internal supply and
the references voltages and currents required by the ITG-3200. The LDO output is bypassed by a capacitor at
REGOUT. Additionally, the part has a VLOGIC reference voltage which sets the logic levels for its I2C interface.
5.10 Charge Pump
An on-board charge pump generates the high voltage (25V) required to drive the MEMS oscillators. Its output is
bypassed by a capacitor at CPOUT.
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
18 of 39
6 Digital Interface
6.1 I2C Serial Interface
The internal registers and memory of the ITG-3200 can be accessed using I2C at up to 400kHz.
Serial Interface
Pin Number
Pin Name
Pin Description
8
VLOGIC
Digital IO supply voltage. VLOGIC must be ≤ VDD at all times.
9
AD0
I2C Slave Address LSB
23
SCL
I2C serial clock
24
SDA
I2C serial data
6.1.1 I2C Interface
I2C is a two wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ITG-3200 always operates as a slave device when communicating to the system processor, which thus acts as the
master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400kHz.
The slave address of the ITG-3200 devices is b110100X which is 7 bits long. The LSB bit of the 7 bit address is
determined by the logic level on pin 9. This allows two ITG-3200 devices to be connected to the same I2C bus. When
used in this configuration, the address of the one of the devices should be b1101000 (pin 9 is logic low) and the address
of the other should be b1101001 (pin 9 is logic high). The I2C address is stored in register 0 (WHO_AM_I register).
I2C Communications Protocol
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a
HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy
until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line
while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL S
START condition STOP condition
P
START and STOP Conditions
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
19 of 39
Data Format / Acknowledge
I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per data transfer.
Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is
generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding
it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can
hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and
releases the clock line (see figure below).
DATA OUTPUT BY
TRANSMITTER (SDA)
DATA OUTPUT BY
RECEIVER (SDA)
SCL FROM
MASTER
START
condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
1 2 8 9
Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an
8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave
device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device.
Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line
LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with
a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START
condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on
the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with
the exception of start and stop conditions.
SDA
START
condition
SCL
ADDRESS R/W ACK DATA ACK DATA ACK STOP
condition
S P
1 – 7 8 9 1 – 7 8 9 1 – 7 8 9
Complete I2C Data Transfer
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
20 of 39
To write the internal ITG-3200 device registers, the master transmits the start condition (S), followed by the I2C address
and the write bit (0). At the 9th clock cycle (when the clock is high), the ITG-3200 device acknowledges the transfer.
Then the master puts the register address (RA) on the bus. After the ITG-3200 acknowledges the reception of the
register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer
may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue
outputting data rather than transmitting a stop signal. In this case, the ITG-3200 device automatically increments the
register address and loads the data to the appropriate register. The following figures show single and two-byte write
sequences.
Single-Byte Write Sequence
Burst Write Sequence
To read the internal ITG-3200 device registers, the master first transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when clock is high), the ITG acknowledges the transfer. The master
then writes the register address that is going to be read. Upon receiving the ACK signal from the ITG-3200, the master
transmits a start signal followed by the slave address and read bit. As a result, the ITG-3200 sends an ACK signal and
the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK
condition is defined such that the SDA line remains high at the 9th clock cycle. To read multiple bytes of data, the
master can output an acknowledge signal (ACK) instead of a not acknowledge (NACK) signal. In this case, the ITG-
3200 automatically increments the register address and outputs data from the appropriate register. The following
figures show single and two-byte read sequences.
Single-Byte Read Sequence
Burst Read Sequence
Master
S
AD+W
RA
DATA
P
Slave
ACK
ACK
ACK
Master
S
AD+W
RA
DATA
DATA
P
Slave
ACK
ACK
ACK
ACK
Master
S
AD+W
RA
S
AD+R
NACK
P
Slave
ACK
ACK
ACK
DATA
Master
S
AD+W
RA
S
AD+R
ACK
NACK
P
Slave
ACK
ACK
ACK
DATA
DATA
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
21 of 39
I2C Terms
Signal
Description
S
Start Condition: SDA goes from high to low while SCL is high
AD
Slave I2C address
W
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
NACK
Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA
ITG-3200 internal register address
DATA
Transmit or received data
P
Stop condition: SDA going from low to high while SCL is high
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
22 of 39
7 Register Map
Addr
Hex
Addr
Decimal
Register Name
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
WHO_AM_I
R/W
-
ID
-
15
21
SMPLRT_DIV
R/W
SMPLRT_DIV
16
22
DLPF_FS
R/W
-
-
-
FS_SEL
DLPF_CFG
17
23
INT_CFG
R/W
ACTL
OPEN
LATCH_
INT_EN
INT_
ANYRD_
2CLEAR
-
ITG_RDY
_EN
-
RAW_
RDY_ EN
1A
26
INT_STATUS
R
-
-
-
-
-
ITG_RDY
-
RAW_
DATA_
RDY
1B
27
TEMP_OUT_H
R
TEMP_OUT_H
1C
28
TEMP_OUT_L
R
TEMP_OUT_L
1D
29
GYRO_XOUT_H
R
GYRO_XOUT_H
1E
30
GYRO_XOUT_L
R
GYRO_XOUT_L
1F
31
GYRO_YOUT_H
R
GYRO_YOUT_H
20
32
GYRO_YOUT_L
R
GYRO_YOUT_L
21
33
GYRO_ZOUT_H
R
GYRO_ZOUT_H
22
34
GYRO_ZOUT_L
R
GYRO_ZOUT_L
3E
62
PWR_MGM
R/W
H_RESET
SLEEP
STBY_XG
STBY_YG
STBY_ZG
CLK_SEL
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
23 of 39
8 Register Description
This section details each register within the InvenSense ITG-3200 gyroscope. Note that any bit that is not defined
should be set to zero in order to be compatible with future InvenSense devices.
The register space allows single-byte reads and writes, as well as burst reads and writes. When performing burst reads
or writes, the memory pointer will increment until either (1) reading or writing is terminated by the master, or (2) the
memory pointer reaches certain reserved registers between registers 33 and 60.
8.1 Register 0 – Who Am I
Type: Read/Write
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
-
ID
-
Description:
This register is used to verify the identity of the device.
Parameters:
ID Contains the I2C address of the device, which can also be changed by writing to this register.
The Power-On-Reset value of Bit6: Bit1 is 110 100.
8.2 Register 21 – Sample Rate Divider
Type: Read/Write
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
15
21
SMPLRT_DIV
00h
Description:
This register determines the sample rate of the ITG-3200 gyros. The gyros outputs are sampled internally at
either 1kHz or 8kHz, determined by the DLPF_CFG setting (see register 22). This sampling is then filtered
digitally and delivered into the sensor registers after the number of cycles determined by this register. The
sample rate is given by the following formula:
Fsample = Finternal / (divider+1), where Finternal is either 1kHz or 8kHz
As an example, if the internal sampling is at 1kHz, then setting this register to 7 would give the following:
Fsample = 1kHz / (7 + 1) = 125Hz, or 8ms per sample
Parameters:
SMPLRT_DIV Sample rate divider: 0 to 255
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
24 of 39
8.3 Register 22 – DLPF, Full Scale
Type: Read/Write
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
16
22
-
FS_SEL
DLPF_CFG
00h
Description:
This register configures several parameters related to the sensor acquisition.
The FS_SEL parameter allows setting the full-scale range of the gyro sensors, as described in the table below.
The power-on-reset value of FS_SEL is 00h. Set to 03h for proper operation.
FS_SEL
FS_SEL
Gyro Full-Scale Range
0
Reserved
1
Reserved
2
Reserved
3
±2000°/sec
The DLPF_CFG parameter sets the digital low pass filter configuration. It also determines the internal
sampling rate used by the device as shown in the table below.
DLPF_CFG
DLPF_CFG
Low Pass Filter Bandwidth
Internal Sample Rate
0
256Hz
8kHz
1
188Hz
1kHz
2
98Hz
1kHz
3
42Hz
1kHz
4
20Hz
1kHz
5
10Hz
1kHz
6
5Hz
1kHz
7
Reserved
Reserved
Parameters:
FS_SEL Full scale selection for gyro sensor data
DLPF_CFG Digital low pass filter configuration and internal sampling rate configuration
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
25 of 39
DLPF Characteristics: The gain and phase responses of the digital low pass filter settings (DLPF_CFG) are
shown below:
Gain and Phase vs. Digital Filter Setting
Gain and Phase vs. Digital Filter Setting, Showing Passband Details
-50
-40
-30
-20
-10
0
Magnitude (dB)
100101102103
-90
-45
0
Phase (deg)
Bode Diagram
Frequency (Hz)
6 5 4 3 2 1 0
6 5 4 3 2 1 0
-6
-4
-2
0
2
Magnitude (dB)
100101102103
-15
-10
-5
0
Phase (deg)
Bode Diagram
Frequency (Hz)
6 5 4 3 2 1 0
6 5 4 3 2 1 0
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
26 of 39
8.4 Register 23 – Interrupt Configuration
Type: Read/Write
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
17
23
ACTL
OPEN
LATCH_
INT_EN
INT_
ANYRD_
2CLEAR
0
ITG_RDY_
EN
0
RAW_
RDY_ EN
00h
Description:
This register configures the interrupt operation of the device. The interrupt output pin (INT) configuration can
be set, the interrupt latching/clearing method can be set, and the triggers for the interrupt can be set.
Note that if the application requires reading every sample of data from the ITG-3200 part, it is best to enable
the raw data ready interrupt (RAW_RDY_EN). This allows the application to know when new sample data is
available.
Parameters:
ACTL Logic level for INT output pin – 1=active low, 0=active high
OPEN Drive type for INT output pin – 1=open drain, 0=push-pull
LATCH_INT_EN Latch mode – 1=latch until interrupt is cleared, 0=50us pulse
INT_ANYRD_2CLEAR Latch clear method – 1=any register read, 0=status register read only
ITG_RDY_EN Enable interrupt when device is ready (PLL ready after changing clock source)
RAW_RDY_EN Enable interrupt when data is available
0 Load zeros into Bits 1 and 3 of the Interrupt Configuration register.
8.5 Register 26 – Interrupt Status
Type: Read only
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
1A
26
-
-
-
-
-
ITG_RDY
-
RAW_
DATA_
RDY
00h
Description:
This register is used to determine the status of the ITG-3200 interrupts. Whenever one of the interrupt sources
is triggered, the corresponding bit will be set. The polarity of the interrupt pin (active high/low) and the latch
type (pulse or latch) has no affect on these status bits.
Use the Interrupt Configuration register (23) to enable the interrupt triggers. If the interrupt is not enabled, the
associated status bit will not get set.
In normal use, the RAW_DATA_RDY interrupt is used to determine when new sensor data is available in either
the sensor registers (27 to 32).
Interrupt Status bits get cleared as determined by INT_ANYRD_2CLEAR in the interrupt configuration
register (23).
Parameters:
ITG_RDY PLL ready
RAW_DATA_RDY Raw data is ready
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
27 of 39
8.6 Registers 27 to 34 – Sensor Registers
Type: Read only
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1B
27
TEMP_OUT_H
1C
28
TEMP_OUT_L
1D
29
GYRO_XOUT_H
1E
30
GYRO_XOUT_L
1F
31
GYRO_YOUT_H
20
32
GYRO_YOUT_L
21
33
GYRO_ZOUT_H
22
34
GYRO_ZOUT_L
Description:
These registers contain the gyro and temperature sensor data for the ITG-3200 parts. At any time, these values
can be read from the device; however it is best to use the interrupt function to determine when new data is
available.
Parameters:
TEMP_OUT_H/L 16-bit temperature data (2’s complement format)
GYRO_XOUT_H/L 16-bit X gyro output data (2’s complement format)
GYRO_YOUT_H/L 16-bit Y gyro output data (2’s complement format)
GYRO_ZOUT_H/L 16-bit Y gyro output data (2’s complement format)
8.7 Register 62 – Power Management
Type: Read/Write
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
3E
62
H_RESET
SLEEP
STBY
_XG
STBY
_YG
STBY
_ZG
CLK_SEL
00h
Description:
This register is used to manage the power control, select the clock source, and to issue a master reset to the
device.
Setting the SLEEP bit in the register puts the device into very low power sleep mode. In this mode, only the
serial interface and internal registers remain active, allowing for a very low standby current. Clearing this bit
puts the device back into normal mode. To save power, the individual standby selections for each of the gyros
should be used if any gyro axis is not used by the application.
The CLK_SEL setting determines the device clock source as follows:
CLK_SEL
CLK_SEL
Clock Source
0
Internal oscillator
1
PLL with X Gyro reference
2
PLL with Y Gyro reference
3
PLL with Z Gyro reference
4
PLL with external 32.768kHz reference
5
PLL with external 19.2MHz reference
6
Reserved
7
Reserved
On power up, the ITG-3200 defaults to the internal oscillator. It is highly recommended that the device is
configured to use one of the gyros (or an external clock) as the clock reference, due to the improved stability.
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
28 of 39
Parameters:
H_RESET Reset device and internal registers to the power-up-default settings
SLEEP Enable low power sleep mode
STBY_XG Put gyro X in standby mode (1=standby, 0=normal)
STBY_YG Put gyro Y in standby mode (1=standby, 0=normal)
STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal)
CLK_SEL Select device clock source
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
29 of 39
9 Assembly
9.1 Orientation
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation.
ITG-3200
+Z
+X
+Y
Orientation of Axes of Sensitivity
and Polarity of Rotation
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
30 of 39
9.2 Package Dimensions
Package Dimensions
Top View
Bottom View
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
31 of 39
9.3 Package Marking Specification
InvenSense
ITG-3200
XXXXXX-XX
XX YYWW X
Lot traceability code
Foundry code
Package Vendor Code
Rev Code
YY = Year Code
WW = Work Week
TOP VIEW
Part number
Package Marking Specification
9.4 Tape & Reel Specification
Tape Dimensions
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
32 of 39
Reel Outline Drawing
Reel Dimensions and Package Size
PKG
SIZE
REEL (mm)
L
V
W
Z
4x4
330
100
13.2
2.2
Tape and Reel Specification
Reel Specifications
Quantity Per Reel
5,000
Reels per Box
1
Boxes Per Carton (max)
3 full pizza boxes packed in the center of the carton,
buffered by two empty pizza boxes (front and back).
Pcs/Carton (max)
15,000
Package Orientation
Pin 1
User Direction of
Feed
Cover Tape
(Anti-Static)
Carrier Tape
(Anti-Static)
Label
Reel
Terminal Tape
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
33 of 39
9.5 Label
9.6 Packaging
Moisture Barrier Bag
With Labels
Anti-static Label
Moisture-Sensitive
Caution Label
Tape & Reel Label
Reel in Box
Box with Tape & Reel Label
Location of Label
Moisture-Sensitive Caution Label
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
34 of 39
9.7 Soldering Exposed Die Pad
The ITG-3200 has very low active and standby current consumption. The exposed die pad is not required for heat
sinking, and should not be soldered to the PCB since soldering to it contributes to performance changes due to package
thermo-mechanical stress.
9.8 Component Placement
Testing indicates that there are no specific design considerations other than generally accepted industry design practices
for component placement near the ITG-3200 multi-axis gyroscope to prevent noise coupling, and thermo-mechanical
stress.
9.9 PCB Mounting and Cross-Axis Sensitivity
Orientation errors of the gyroscope mounted to the printed circuit board can cause cross-axis sensitivity in which one
gyro responds to rotation about another axis, for example, the X-axis gyroscope responding to rotation about the Y or Z
axes. The orientation mounting errors are illustrated in the figure below.
Package Gyro Axes ( ) Relative to PCB Axes ( ) with Orientation Errors (Θ and Φ)
ITG-3200
Φ
ΘX
Y
Z
The table below shows the cross-axis sensitivity as a percentage of the specified gyroscope’s sensitivity for a given
orientation error.
Cross-Axis Sensitivity vs. Orientation Error
Orientation Error
(θ or Φ)
Cross-Axis Sensitivity
(sinθ or sinΦ)
0º
0%
0.5º
0.87%
1º
1.75%
The specification for cross-axis sensitivity in Section 3 includes the effect of the die orientation error with respect to the
package.
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
35 of 39
9.10 MEMS Handling Instructions
MEMS (Micro Electro-Mechanical Systems) are a time-proven, robust technology used in hundreds of millions of
consumer, automotive and industrial products. MEMS devices consist of microscopic moving mechanical structures.
They differ from conventional IC products even though they can be found in similar packages. Therefore, MEMS
devices require different handling precautions than conventional ICs prior to mounting onto printed circuit boards
(PCBs).
The ITG-3200 gyroscope has a shock tolerance of 10,000g. InvenSense packages its gyroscopes as it deems proper for
protection against normal handling and shipping. It recommends the following handling precautions to prevent potential
damage.
Individually packaged or trays of gyroscopes should not be dropped onto hard surfaces. Components placed in trays
could be subject to g-forces in excess of 10,000g if dropped.
Printed circuit boards that incorporate mounted gyroscopes should not be separated by manually snapping apart.
This could also create g-forces in excess of 10,000g.
9.11 Gyroscope Surface Mount Guidelines
Any material used in the surface mount assembly process of the MEMS gyroscope should be free of restricted RoHS
elements or compounds. Pb-free solders should be used for assembly.
In order to assure gyroscope performance, several industry standard guidelines need to be considered for surface
mounting. These guidelines are for both printed circuit board (PCB) design and surface mount assembly and are
available from packaging and assembly houses.
When using MEMS gyroscope components in plastic packages, package stress due to PCB mounting and assembly
could affect the output offset and its value over a wide range of temperatures. This is caused by the mismatch between
the Coefficient Temperature Expansion (CTE) of the package material and the PCB. Care must be taken to avoid
package stress due to mounting.
9.12 Reflow Specification
The approved solder reflow curve shown in the figure below conforms to IPC/JEDEC J-STD-020D.01
(Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices) with a maximum peak
temperature (Tc = 260°C). This is specified for component-supplier reliability qualification testing using lead-free
solder for package thicknesses less than 1.6 mm. The reliability qualification pre-conditioning used by InvenSense
incorporates three of these conforming reflow cycles. All temperatures refer to the topside of the QFN package, as
measured on the package body surface. Customer solder-reflow processes should use the solder manufacturer’s
recommendations, making sure to never exceed the constraints listed in the table and figure below, as these represent
the maximum tolerable ratings for the device. For optimum results, production solder reflow processes should use
lower temperatures, reduced exposure times to high temperatures, and lower ramp-up and ramp-down rates than those
listed below.
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
36 of 39
Approved IR/Convection Solder Reflow Curve
Temperature Set Points for IR / Convection Reflow Corresponding to Figure Above
Step
Setting
CONSTRAINTS
Temp (°C)
Time (sec)
Rate (°C/sec)
A
Troom
25
B
TSmin
150
C
TSmax
200
60 < tBC < 120
D
TLiquidus
217
r(TLiquidus-TPmax) < 3
E
TPmin
[< TPmax-5°C, 250°C]
255
r(TLiquidus-TPmax) < 3
F
TPmax
[< TPmax, 260°C]
260
tAF < 480
r(TLiquidus-TPmax) < 3
G
TPmin
[< TPmax-5°C, 250°C]
255
tEG < 30
r(TPmax-TLiquidus) < 4
H
TLiquidus
217
60 < tDH < 120
I
Troom
25
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
37 of 39
9.13 Storage Specifications
The storage specification of the ITG-3200 gyroscope conforms to IPC/JEDEC J-STD-020C Moisture Sensitivity Level
(MSL) 3.
Storage Specifications for ITG-3200
Calculated shelf-life in moisture-sealed bag
12 months -- Storage conditions: <40°C and <90% RH
After opening moisture-sealed bag
168 hours -- Storage conditions: ambient ≤30°C at 60% RH
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
38 of 39
10 Reliability
10.1 Qualification Test Policy
InvenSense’s products complete a Qualification Test Plan before being released to production. The Qualification Test
Plan follows the JEDEC 47D Standards, “Stress-Test-Driven Qualification of Integrated Circuits,” with the individual
tests described below.
10.2 Qualification Test Plan
Accelerated Life Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
High Temperature
Operating Life (HTOL/LFR)
JEDEC JESD22-A108C, Dynamic, 3.63V biased, Tj>125°C
[read-points 168, 500, 1000 hours]
3
77
(0/1)
Steady-State Temperature
Humidity Bias Life (1)
JEDEC JESD22-A101C, 85°C/85%RH
[read-points 168, 500 hours], Information Only 1000 hours]
3
77
(0/1)
High Temperature Storage
Life
JEDEC JESD22-A103C, Cond. A, 125°C Non-Bias Bake
[read-points 168, 500, 1000 hours]
3
77
(0/1)
Device Component Level Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
ESD-HBM
JEDEC JESD22-A114F, Class 2 (1.5KV)
1
3
(0/1)
ESD-MM
JEDEC JESD22-A115-A, Class B (200V)
1
3
(0/1)
Latch Up
JEDEC JESD78B Level 2, 125C, +/- 100mA
1
6
(0/1)
Mechanical Shock
JEDEC JESD22-B104C, Mil-Std-883, method 2002, Cond. D,
10,000g’s, 0.3ms, ±X,Y,Z – 6 directions, 5 times/direction
3
5
(0/1)
Vibration
JEDEC JESD22-B103B, Variable Frequency (random),
Cond. B, 5-500Hz, X,Y,Z – 4 times/direction
3
5
(0/1)
Temperature Cycling (1)
JEDEC JESD22-A104D Condition N, -40°C to +85°C,
Soak Mode 2, 100 cycles
3
77
(0/1)
Board Level Tests
TEST
Method/Condition/
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
Board Mechanical Shock
JEDEC JESD22-B104C,Mil-Std-883, method 2002, Cond. D,
10,000g’s, 0.3ms, +-X,Y,Z – 6 directions, 5 times/direction
1
5
(0/1)
Board T/C
JEDEC JESD22-A104D Condition N, -40°C to +85°C,
Soak Mode 2, 100 cycles
1
40
(0/1)
(1) – Tests are preceded by MSL3 Preconditioning in accordance with JEDEC JESD22-A113F
ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
39 of 39
This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use, or
for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice.
InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance,
without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this
document. InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of
products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask
work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or
otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks
that are registered trademarks are the property of their respective companies. InvenSense sensors should not be used or sold in the development,
storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as
in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant
equipment, disaster prevention and crime prevention equipment.
InvenSense, InvenSense logo, ITG, and ITG-3200 are trademarks of InvenSense, Inc.
©2009 InvenSense, Inc. All rights reserved.